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In this paper, we present a rectification process through electron emission from sharp tips under a high electric field of 109–1010 V/m based on the Fowler–Nordheim theory. A large planar array of ...

A rectification concept based on field electron emission in a nanoantenna is proposed. The device consists of three parts, i.e., an aspherical micro-lens, a nanoantenna, and an electron collector e...

A single-inductor multiple-output (SIMO) converter with constant frequency auto-buck-boost feature is presented in this paper. This converter can supply more than one output. Some applications of this converter include their use in mobile phones and medical devices that require different voltages. This paper deals with a single-inductor dual-output (SIDO) converter for simplicity, which can be generalized to multiple outputs. Here, according to the mode in which the converter works and the maximum load current, which is about 1 rnA, the outputs work completely independent, which means changing the load in one output does not affect the other output. The converter operates in discontinuous conduction mode (DCM), and the time-multiplexing control (TMC) method and pulse width modulation (PWM) are used in its controller. An analog to digital converter (ADC) is used to monitor the output voltage. The switching frequency in this converter is 5 kHz, and due to the possibility of changing the load at the output, the optimal duty cycle value for each output channel is set by the measured voltage. In this paper, the goal is to generate stable voltage and reduce cross regulations to the minimum possible value or even to zero and consider regular timing for switches by the controller.

In this paper, a new analog CMOS current-mode divider is presented based on a new voltage controlled resistor. The proposed divider can be used in analog computation, fuzzy logic controllers (FLC), neural network, etc. The advantages of the improved structure are simplicity, wide bandwidth, wide dynamic range, low supply voltage requirements, low-power consumption and low active area. The post-layout simulations of the proposed divider implemented in a 0.18-□m CMOS process was performed with HSPICE software. In this case, supply was 0.9-V and divider has less than maximum 1% linear error. Also, the total power consumption was 42-□W at more than 350-MHz bandwidth and occupied area was about 370-□ $m^{2}$ .

This paper presents an eight-phase LC voltage controlled oscillator (VCO) using a super-harmonic coupling technique. Eight various phases are created in which there is 45 degrees phase difference between continued outputs. Four oscillators are coupled by two nmos transistor used in each stage acting as a mixer to generate proper second harmonic signals. Second harmonic signal is injected to the center tap of the tank inductor in the next stage. The proposed VCO is simulated in silterra $.18\ \mu\mathrm{m}$ BCD process with the area of $.7\times 0.7\ \mathrm{mm}^{2}$ . The VCO can be tuned from 22.2 GHz to 25.1 GHz, a frequency tuning range of 12.3% at 1.8V supply. With each VCO consuming 2.2 mW DC power (8.8 mW total), the phase noise is −107 dBc/Hz at 1 MHz offset when VCO output frequency is 24 GHz. Maximum FOM of the proposed VCO is 190.16 dB. Comparison results show that the proposed VCO is among the best works.

A two-stage wideband low-noise amplifier (LNA) using source-follower feedback (SFF) is presented. A novel approach using a combination of asymmetrical inductive peaking and SFF is used to alleviate the trade-off between input matching and noise figure, thus making more space for design. A peaking inductor in the gate of the NMOS in the first stage is added to resonate with the capacitance of the node, resulting better input matching. In addition, a second stage is added to widen gain bandwidth using inductive load. Simulated in TSMC $\mathbf{0.18}-\mu\mathbf{m}$ CMOS technology for 1-6.7 GHz, voltage gain of 12.5 dB and a NF of 2.2dB over the 3-dB bandwidth is achieved. The LNA consumes 9.3 mW from a 1.8 V supply.

Rectifiers are an integral part of power harvesting systems. In this paper, the literature on RF power rectifiers is surveyed, starting from the well-known voltage doubler. Effects of using low turn-on voltage devices on forward and reverse losses, and therefore, on conversion efficiency, is discussed. Samples of rectifiers with external devices, such as Schottky diodes are presented. Idea of external Vth cancellation through a rechargeable battery, self Vth cancellation, and floating gate transistors with charge injection onto the gates are demonstrated. Then, standard bridge rectifier and its modified versions, including Vth cancellation technique, are explained. Using low voltage devices in other technologies, such as silicon on sapphire and silicon on isolator are also discussed. After literature survey, the bridge rectifier is studied in detail, to extract guidelines for efficiency enhancement. Bridge rectifier has high PCE, because the transistors have a dynamic bias that lowers their forward and reverse losses, simultaneously. Then, the effect of transistor threshold voltages on the bridge rectifier performance is investigated. We propose to shift peak region in the efficiency curve to a desired output voltage, based on which, two modified rectifiers are introduced. A single stage modified bridge rectifier is proposed with 3.3 V transistors, that achieves efficiency of around 80% at 0.9 V output. Then, a two stage modified bridge rectifier is proposed, that uses a combination of 1.8 and 3.3 V transistors to remove the need to source-bulk connection in NMOS transistors (that requires triple-well CMOS technology). Simulations predict around 80% efficiency at 1.7 V output.

In this paper, using the concept of impulse sensitivity function (ISF) in Hajimiri's phase noise model, a novel circuit method for phase noise reduction in LC cross coupled oscillators is proposed. Based on the proposed technique, at outputs zero crossing points, where ISF is maximum, current supplying to the transistor pair is stopped by two added transistors. Due to the shaped effective ISF waveform and also reduction of its RMS value, phase noise is decreased. In addition, the cascode structure of the proposed technique leads to more phase noise reduction due to the suppression of the transistors noise power. The proposed circuit is designed for 10 GHz output frequency and inductor quality factor of 12, and simulated in a standard 0.18 µm CMOS technology with a 1.8 V supply. Compared to the simple cross coupled oscillator, phase noise at 1 MHz and power consumption are reduced by 8 dB and 26%, respectively. The phase noise and FOM for the proposed oscillator at 1 MHz offset frequency are ýý107.8 dBc/Hz and 186.2 dB, respectively.

In this paper, a low phase noise oscillator using tail current shaping method is presented. The current shaping is achieved using two paths for current disconnection and current injection, as a result of which, the total tail current is shaped to a sharp and sawtooth waveform, close to an impulse. Each switching transistor is ON only in 22% of an oscillation period, and tail current is mostly supplied to these transistors near the outputs peak points. In those moments, the oscillator sensitivity to noise sources is minimum. The proposed oscillator is designed and simulated in 0.18 μm RF CMOS technology with 1.8 V supply, and using the inductor model offered by the process, with quality factor of 11. Post layout simulations predict an oscillation frequency of 1.65 GHz, and phase noise of −127.7 dBc/Hz at 1 MHz offset, which is 6.3 dB better than that of simple cross coupled oscillator with the same core oscillator power consumption of 2.2 mW. The proposed circuit, however, consumes an extra power of about 1.9 mW for the added current shaping circuits. Compared to conventional tail current shaping technique, the proposed oscillator offers better tail current shaping, and a much higher start-up current and gain, which is desirable.

In this work, one of local stereo vision algorithms named SAD approach, which is used in image depth estimation, has been surveyed, and an efficient and real-time new hardware implementation has been proposed. The proposed method has been verified and tested using C implementation. The acceptable simulation results along with the detailed explanation of numerous pre-processing steps are also presented. Our innovations could be divided into two sections: architecture and algorithm. In architecture section, by using a specific architecture, memory access has been lowered and therefore, speed has been increased. In algorithm section, a part of local algorithm, known as refinement, has been substituted with a simpler and more efficient algorithm. Cyclone IV has been utilized as our hardware platform. In this article, this point would demonstrate how to use an exact but less complicated controller, which results in less area, and how to use pipeline architecture and remove repetitive and redundant memory accesses, which conduct our stereo vision system to meet the real-time constraints. Suggested hardware implementation could reach to 53fps processing speed with 100MHz clock. No processing IP core has been used. In comparison with related work, our proposed method is more efficient in logic elements usage, and accordingly in power consumption.

The quality of service for the cell-edge users is degraded by inter-cell interference, preventing fulfillment of the LTE-A requirements. The effects of the cell-edge interference can be suppressed by Coordinated Multi-Point (CoMP) transmission/reception techniques. One approach of CoMP in downlink scenario is joint transmission (JT), which is closely related to MIMO communication concept. This leads to incorporation of conventional MIMO detectors for JT. MIMO tone by tone detection demands an extensive computational power. Recently, interpolation based MMSE MIMO detectors have been proposed to reduce the computational power. In this work, the recently proposed floating-point interpolation based MMSE detector is modified to make it suitable for fixed-point implementation. The optimal word-length is determined by simulation-based optimization. The proposed algorithm is implemented on a Virtex-7 FPGA and achieves a clock frequency of 422 MHz, with an optimal word-length of 20 bits. The throughput of the implemented detector exceeds 1.15 Gbps with 0.6 μs latency.

This paper proposes a new super-harmonic coupled quadrature voltage controlled oscillator (QVCO), which oscillates at carrier frequency of 5.4GHz. The structure of the proposed circuit includes two complementary cross coupled oscillator with an extra frequency doubler circuit using mixing operation of triode region transistors to generate anti-phase second harmonic signals. Second harmonic injection takes place at center tap of the tank inductor. Simulation result based on a TSMC 0.18-μ $m$ CMOS technology shows −121.4dBc/Hz phase noise at 1MHz offset frequency, which shows 5dB improvement compared to the conventional complementary P-QVCO. In the proposed method, the quadrature accuracy has lower impact on phase noise. The proposed QVCO dissipates 2.5mA from a 1.8V supply and has a FOM of 189.3dB. The maximum simulated phase error is 3.7°in the presence of 1% tank capacitor mismatch.

This paper presents a 60 mV input voltage start-up system for thermoelectric energy harvesting. A new process tolerant inverter cell is proposed, which is functional at supply voltages as low as 60 mV. Using the proposed unit cell, a ring oscillator has been implemented. The ring oscillator is followed by 40 charge-pump stages, an ultra-low-power level detector, and a boost converter. The energy harvesting system can generate an output voltage of 1 V and delivers a maximum power of 4.5 μW from a 60 mV supply. This system has been implemented in a standard 0.18 μm CMOS technology, uses neither zerothreshold voltage (normally-on) negative-channel metal-oxide semiconductor nor microelectromechanical systems switches and occupies 3.3 mm2.

Summary A low voltage bulk-driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm-C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third-order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than −40 dB over the tuning range of the transconductance, by applying 800 mVppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third-order low-pass Gm-C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from −1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright © 2014 John Wiley & Sons, Ltd.

In this paper, five different nanoantenna structures, i.e. dipole, bowtie, rounded bowtie, rounded cross bowtie and cross bowtie nanoantennas are investigated for solar energy harvesting. Electrical field enhancement by each structure is investigated when different metals (silver, aluminum, gold, and copper) are used to achieve the best performance for solar energy harvesting. Field enhancement in the gap of the nanoantenna is defined as a figure of merit for comparing these structures. Simulations show that cross bowtie nanoantenna has the best performance for solar energy harvesting in the optical and infrared wavelengths. Moreover, genetic algorithm is used for optimizing nanoantenna geometry through Finite Element Method (FEM). Finally, the effect of thin layer oxidations on the cross bowtie nanoantenna is investigated, and the main fabrication issues such as effect of the manufacturing tolerances on the nanoantenna performance are discussed.

In this paper, a novel circuit method is proposed to reduce 1/f3 (close-in) phase noise in a cross-coupled LC Voltage Control Oscillator (VCO) by suppressing flicker noise power of the tail transistor. Using an added resistor between drain and gate of the tail transistor, that works as a negative feedback, the tail transistor flicker noise is suppressed, and therefore, the 1/f3 output phase noise is reduced by 5.7[Formula: see text]dB. Also, the added resistor helps in better tail current shaping for phase noise reduction. The proposed oscillator is designed in a 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V supply and 3.6[Formula: see text]mW power consumption. Post-layout simulations predict a phase noise of [Formula: see text][Formula: see text]dBc/Hz for the proposed oscillator at 100[Formula: see text]KHz offset from 3.1[Formula: see text]GHz carrier frequency. Mathematical analysis is included in the paper for confirmation of the phase noise performance enhancement. The Figure of Merit (FOM) of the proposed oscillator is 188.3 and 190.6[Formula: see text]dBc/Hz at 100[Formula: see text]KHz and 1[Formula: see text]MHz offsets, respectively.

Communication systems require a wide gain range. For example the code-division multiple access system (CDMA) requires more than 80 dB of gain range so that, many variable gain amplifiers (VGAs) must be used, resulting in high power consumption and low linearity because of VGA non-linearity factors. In this paper, a one-stage VGA in 0.18 μm technology is presented. The VGA based on the class AB power amplifier is designed and simulated for a high linearity and an 80 dB tuning range. For the linear-in-decibel tuning range, transistors in sub-threshold region is used. The current control circuit of the VGA changes gain continuously from ?68 to 18 dB at 0.5 GHz and ?60 to 20 dB at 1 GHz with gain error of less than 2 dB. The power consumption enjoys a highest value about 13.5 mW in the maximum gain and P1dB is also about ?3.4 dBm at 0.5 GHz and 2.2 dBm at 1 GHz.

Reducing the power consumption of a passive radio frequency identification (RFID) tag is the key in many applications. As the modulator is usually the most power-hungry block in an RFID tag, this paper proposes a power-saving modulator. The proposed modulator uses phase shift keying (PSK) backscatter modulation which allows tag to communicate data from its memory to a reader by PSK modulation. The proposed modulator uses a MOSCAP as a variable impedance and is designed in a new one-inverter structure in compare to the conventional varactor-based modulators designed in two-inverter structure, as this modulator needs just a low voltage swing to drive its MOSCAP. Using MOSCAP as the variable capacitance leads to a low voltage design. Also, the fundamental equations required for determination of the capacitive impedance seen by the antenna is presented. This impedance is the master key in modulator design. The modulator has been designed, simulated and optimized in 0.18 μm CMOS technology. All possible simulation results are presented to approve its compatible operation with C1 G2 EPC global standard. The power consumption of less than 46 nW is achieved in all process corner cases at 0.8 V power supply.

Large digital chips use a significant amount of energy to broadcast a low-skew, multigigahertz clock to millions of latches located throughout the chip. Every clock cycle, the large aggregate capacitance of the clock network is charged from the supply and then discharged to ground. Instead of wasting this stored energy, it is possible to recycle the energy by controlling its delivery to another part of the chip using an on-chip dc-dc converter. The clock driver and switching converter circuits share many compatible characteristics that allow them to be merged into a single design and fully integrated on-chip. Our buck converter prototype, manufactured in 90-nm CMOS, provides a proof-of-concept that clock network energy can be recycled to other parts of the chip, thus lowering overall energy consumption. It also confirms that monolithic multigigahertz switching converters utilizing zero-voltage switching can be implemented in deep-submicrometer CMOS. With multigigahertz operation, fully integrated inductors and capacitors use a small amount of chip area with low losses. Combining the clock driver with the power converter can share the large MOSFET drivers necessary as well as being energy and space efficient. We present an analysis of the losses which we confirm by experimentally comparing the merged circuit with a conventional clock driver.

This paper describes an ultra low power receiver RF front-end to be utilized for wireless sensor network (WSN) applications. The design of the LV cell (LNA and VCO) that is proposed in this paper is suitable for direct conversion architecture, while the conventional LMV cell (LNA, Mixer, and VCO) is used only in low-IF architectures, due to the prohibitive high flicker noise. A passive mixer is utilized instead of an active mixer and a capacitor is added to block the DC current flowing into the mixer. So, flicker noise corner frequency is reduced to 13.8kHz. The proposed design can be used more easily compared to conventional LMV cell in a low voltage technology, because of the stacking of only two blocks (LNA and VCO), while three blocks of LNA, mixer, and VCO are stacked in the conventional LMV cell. The proposed receiver RF front-end consumes 1mW in 0.18@mm CMOS technology with a 1.2V supply source. NF and IIP3 are 4.7dB and -7dBm, respectively.

In order to reduce the power consumption of RFID tags and increase the reading range of RFID systems, this paper proposes an ASK demodulator that uses a new approach to reduce the threshold voltage of diode connected MOS transistors as an obstacle in the design of the envelope detector. Also, an ultra low power comparator is used for further power reduction. This circuit has been simulated in a 0.18 μm CMOS technology to satisfy EPC Class 1 Generation 2 standard protocol emphasizing on the reduction of power consumption. The proposed circuit can correctly demodulate the minimum input RF signal amplitude of 180 mV for modulation depths of 55---100 % with 40---160 kb/s data rates. A total power consumption of less than 290 nW is achieved at a 1.2 V power supply. Effects of the input signal additive white noise as well as the process and temperature variations on the signal demodulation is also investigated in this paper.

A low voltage low power operational transconductance amplifier (OTA) based on a bulk driven cell and its application to implement a tunable Gm-C filter is presented. The linearity of the OTA is improved by attenuation and source degeneration techniques. The attenuation technique is implemented by bulk driven cell which is used for low supply voltage circuits. The OTA is designed to operate with a 0.9 V supply voltage and consumes 58.8 μW power. A 600 mVppd sine wave input signal at 1 MHz frequency shows total harmonic distortion (THD) better than -40 dB over the tuning range of the transconductance. The OTA has been used to realize a tunable Gm-C low-pass filter with gain tuning from 5 dB to 21 dB with 4 dB gain steps, which results in power consumptions of 411.6 to 646.8 μW. This low voltage filter can operate as channel select filter and variable gain amplifier (VGA) for wireless sensor network (WSN) applications. The proposed OTA and filter have been simulated in 0.18 μm CMOS technology. Corner case and temperature simulation results are also included to forecast process and temperature variation affects after fabrication.

This paper presents a compact, low power 12.5Gb/s backplane receiver in a 90nm CMOS technology. The receiver incorporates an analog equalizer, which is designed using active inductor circuit, and a 1-tap speculative decision-feedback- equalizer (DFE). The proposed active inductor circuit provides wider tuning range and higher inductive impedance with respect to the previous reported topologies, using negative impedance implemented by a cross coupled transistor pair, at the output nodes of active inductor circuit. The DFE is designed in half rate architecture utilizing an improved front end sample and hold to speculate the first feedback tap while consuming low power and imposing small capacitive load on the analog equalizer block. The input capacitance of the DFE block is alleviated more by changing the place of multiplexer in the DFE architecture. Furthermore power consumption reduction in DFE architecture is achieved by using a novel high speed slicer with rail-to-rail swing in the output to avoid implementing latches and MUXs in the next stages in CML topology. The receiver consumes 6.6mW from a 1.2V supply while delivering 12.5Gb/s data over 5'' NELCO 4000-6 channel in the presence of two aggressor far-end-crosstalk (FEXT) signals.

A novel structure with low phase noise and low power dissipation fully differential cross-coupled CMOS LC-DCO is presented. Two effective techniques including adding two digitizer and utilizing two top switching transistors, are used in order to optimize the phase noise. The performance of the proposed DCO well meets all the requirements for low phase noise and low power All-Digital Phase Locked-Loop (ADPLL). Simulation results are obtained by the Cadence IC Design software in 90nm CMOS technology with Spectre simulator. Carrier frequency of Proposed DCO is tuned in the range of 10 to 10.7 GHZ. The measured phase noise at 1 MHz offset from the 10 GHz carrier frequency is around −116 dBc/Hz, while the DCO consumes 4.9 mw at the 1.2 volt supply voltage and finally, FOM is −189 dBc/Hz.

The frequency-translating hybrid analog-to-digital converter (FTH-ADC) architecture is based on frequency interleaving and decomposing the wideband analog input signal into narrower-bandwidth analog baseband subbands, digitizing them, and performing further signal processing in the digital domain. In this paper, digital compensation techniques to enhance the performance of the FTH-ADC system in the presence of errors due to a variety of mismatches are presented. The effectiveness of these techniques to enhance the performance of the system is confirmed using a proof-of-concept two-channel prototype.

Power consumption of a multi-GHz local clock driver is reduced by returning energy stored in the clock-tree load capacitance back to the on-chip power-distribution grid. We call this type of return energy recycling. To achieve a nearly square clock waveform, the energy is transferred in a non-resonant way using an on-chip inductor in a configuration resembling a full-bridge DC-DC converter. A zero-voltage switching technique is implemented in the clock driver to reduce dynamic power loss associated with the high switching frequencies. A prototype implemented in 90 nm CMOS shows a power savings of 35% at 4 GHz. The area needed for the inductor in this new clock driver is about 6% of a local clock region.

A fully integrated 0.18 mum DC-DC buck converter using a low-swing ldquostacked driverrdquo configuration is reported in this paper. A high switching frequency of 660 MHz reduces filter components to fit on chip, but this suffers from high switching losses. These losses are reduced using: 1) low-swing drivers; 2) supply stacking; and 3) introducing a charge transfer path to deliver excess charge from the positive metal-oxide semiconductor drive chain to the load, thereby recycling the charge. The working prototype circuit converts 2.2 to 0.75-1.0 V at 40-55 mA. Design and simulation of an improved circuit is also included that further improves the efficiency by enhancing the charge recycling path, providing automated zero voltage switching (ZVS) operation, and synchronizing the half-swing gating signals.

This paper describes a low-cost, reliable and easily used long-distance health monitoring system, named teleexamination system. In this equipment, the patient is examined online in a live communication platform. Personal computers and/or smart phones as the main processing cores of this system are available everywhere and reduce the final cost of the telemedicine systems. In our proposed system, a bidirectional audio-visual connection is established. By means of a few added special devices for monitoring different body parameters, the doctor could listen to patient’s heart sound as well as measure the body temperature, heart rate, and ECG, and finally prescribe the medicine. This system can be used in many places including, wherever doctors are not available, such as in rural areas, or for disabled people, who are not able to go to a hospital.

In cellular mobile networks, the performance of cell-edge users is limited by high interference signal from neighboring cells. Recently, in modern cellular communication systems, such as LTE-Advanced, the Coordinated Multi-Point Transmission technology is considered to improve the cell-edge users performance. In downlink of a CoMP scenario, the joint transmission can significantly reduce the interference. In this technique, the data signal is jointly transmitted from multiple-cell to the user equipment. However, in this technique the statistical properties of MIMO channel from the cells to the user affect the performance of MIMO detector, which can be expressed by the condition number. This paper presents an analysis of condition number of multiple MIMO channel in joint transmission scenario and proposes a low complexity adaptive LR-MMSE MIMO detection scheme. The computational complexity of proposed detection scheme is reduced by more than 36.5% in comparison to conventional LR-aided detector, while its performance is close to the performance of conventional LR-aided MIMO detector.

Increasing requirement for high speed serial links has necessitated a great effort in this field. An important part of a serial link which is its speed bottleneck is clock data recovery circuit. Phase detector is a prominent component in a CDR which is challenging in high speed structures as it samples high speed and mostly distorted received data and decides its phase relation with local clock signal. In this study we propose a binary quarterrate phase detection technique. It uses slope and data detection concept; however, it introduces a novel slope detection technique to alleviate speed limitations of its baud-rate counterparts. Moreover a novel analog majority voting and de-multiplexing features are included in the structure of this phase detector circuit so that wrong decisions are avoided more effectively without any power overhead. Implementing in 0.18 um CMOS technology we present simulation results for 16 Gbps pseudorandom input data.

This paper presents intelligent lighting control system for smart home. The AC power source is converted down with an AC to DC switching power supply, then is delivered to some LEDs with an LED driver. This paper proposes two methods of lighting control. In the manual control method, LED is controlled with a PWM signal. In fact, according to the user command, it generates the proper duty cycle in a PWM signal. In the automatic control method, the LED is controlled with a signal generated by the PID control algorithm. In this method, the photocell measures the ambient light level and with reference to the input command by the user, proper PWM signal is generated. Circuit schematics and the implementation details are presented. A laboratory prototype is also designed and tested to verify the feasibility, and the experimental results are demonstrated.

Currently need for ultra low power wireless transmitters in medical applications are inevitable. In this paper a new transmitter for body-worn and implantable sensor nodes is presented. Most of the sensor nodes supply their power using energy harvesting instead of a battery, since the power earned by harvesting is limited, so the average and the peak power consumption of the sensor node must be minimized. transmitter blocks which implemented in sensor nodes are too power consuming. So we propose a new low power Binary Frequency Shift Keying (BFSK) transmitter based on sub-harmonic current mode injection locking, and edge combining technique. A 34MHz reference clock is used and the frequency of reference clock multiplied by 12 for desired carrier frequency. The phase noise of the carrier at 1MHz frequency offset is -110.3dBc, total power consumption is about 168μW. The output carrier frequency is 408MHz. BFSK modulation scheme is used at the frequency much lower than the carrier frequency in order to reduce the power consumption.

This paper presents a new zero current detection (ZCD) circuit with no static power consumption. Proposed ZCD can be used in low input voltage boost converters such as thermoelectric energy harvesters. Also a delay-based timing system has been proposed. Introduced timing circuit can build independent on/off times which enables different frequency and duty cycle variations. This enables lower switching frequency at light loads and improves efficiency. Proposed system has been designed and simulated in 0.18μm CMOS technology and achieves maximum efficiency of 63%.

This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output driver for a wireline transmitter is designed in a 90nm CMOS technology. To model nonidealities of the active-inductor that affects the transmitter performance, an accurate large-signal, wide-band characterization technique, based on Least Square Estimation is described. Amplification of high frequency components of 10 Gb/s and 12.5 Gb/s transmitted signals over two kinds of NELCO channels using active inductors in the transmitter side, improves SNDR in the receiver side by 3 dB, as compared to the case with no inductor peaking, for the same power consumption. The transmitter circuit consumes 8.4 mW from a 1.2V power supply.

A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer instead of CML architecture. An accurate characterization of DFE, based on Least Square Estimation and using random sequence, with certain probabilistic characteristics suitable for intended operating conditions, is described. The Proposed 3-tap DFE consumes 4mW from a 1.2V supply when equalizing 10 Gb/s data passed over a 10″ NELCO channel with 15dB of loss at 5 GHz.

In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit resolution, following six 1.5-bit stages with a 2-bit flash ADC at the end. For more power efficiency, stage scaling for the first three stages was also applied. Simulation results in HSPICE using a standard 0.18μm CMOS technology showed a SNDR and SFDR of 59.97dB and 64.8dB, respectively, for a 49.2MHz 2-Vp-p input signal. ADC power consumption excluding buffers and bonding-pads is 6.67mW from a 1.8V supply voltage.

A PMOS-based active inductor circuit for high-speed I/O applications is presented. The active inductor can operate with low voltage headroom and requires no voltage boosting. A prototype output driver circuit using the active inductor is implemented in 90 nm CMOS. The peaking frequency and its corresponding gain magnitude of the active-inductor circuit can be adjusted to facilitate channel loss compensation. Operating at 10 Gb/s over a 6-in FR4 channel, as compared to the case when the active-inductor structure is disabled, the use of active inductor circuit in the transmitter side increases the vertical eye opening at the receiver side by a factor of two and reduces the peak-to-peak jitter of the received data by 30%. By keeping the current of the active inductor above a certain value, impedance variations are minimized and appropriate impedance matching is achieved (S22 less than -10 dB). The active-inductor circuit occupies 17 times 25 mum2 and has a low overhead power consumption of 0.8 mW, i.e., ~10% of the overall power of the prototype output driver.

Design technologies for integrated systems beyond the current CMOS era will present unprecedented advantages such as very high device densities and challenges such as soaring power dissipation issues. Most of the research effort in the emerging area of nanoelectronics has revolved around creating novel devices to replace the traditional CMOS transistor. The development of higher-level communication architectures necessary for integrating such devices into high performance systems has not received the same level of attention so far. With the current trend of CMOS scaling, traditional planar metal-based on-chip interconnect schemes are projected to be the principal bottleneck in meeting the performance needs and specifications of Systems on Chip (SoCs). Three-dimensional integration and on-chip optical and RF communication links have been envisioned as promising alternatives. In this paper we explore the possibility of having an on-chip wireless communication infrastructure using carbon nanotube antennas operating in optical frequencies, and the effect of variations in nanotube properties on the communication behavior.

The design and manufacture of a prototype chip level power supply is described, with both simulated and experimental results. Of particular interest is the inclusion of a fully integrated on-chip LC filter. A high switching frequency of 660 MHz and the design of a device drive circuit reduce losses by supply stacking, low-swing signaling and charge recycling. The paper demonstrates that a chip level converter operating at high frequency can be built and shows how this can be achieved, using zero voltage switching techniques similar to those commonly used in larger converters. Both simulations and experimental data from a fabricated circuit in 0.18mum CMOS are included. The circuit converts 2.2V to 0.75~1.0V at ~55 mA.

This paper advocates dasiareduce, reuse, recyclepsila as a complete energy savings strategy. While reduction has been common to date, there is growing need to emphasize reuse and recycling as well. We design a DC-DC buck converter to demonstrate the 3 techniques: reduce with low-swing and zero voltage switching (ZVS), reuse with supply stacking, and recycle with regulated delivery of excess energy to the output load. The efficiency gained from these 3 techniques helps offset the loss of operating drivers at very high switching frequencies which are needed to move the output filter completely on-chip. A prototype was fabricated in 0.18 mum CMOS, operates at 660 MHz, and converts 2.2 V to 0.75-1.0 V at ~50 mA.

Large digital chips use a significant amount of energy to distribute a multi-GHz clock. By discharging the clock network to ground every cycle, the energy stored in this large capacitor is wasted. Instead, the energy can be recovered using an on-chip DC-DC converter. This paper investigates the integration of two DC-DC converter topologies, boost and buck-boost, with a high-speed clock driver. The high operating frequency significantly shrinks the required size of the L and C components so they can be placed on-chip; typical converters place them off-chip. The clock driver and DC-DC converter are able to share the entire tapered buffer chain, including the widest drive transistors in the final stage. To achieve voltage regulation, the must be modulated; implying only single-edge-triggered flops should be used. However, this minor drawback is eclipsed by the benefits: by recovering energy from the clock, the output power can actually exceed the additional power needed to operate the converter circuitry, resulting in an effective efficiency greater than 100%. Furthermore, the converter output can be used to operate additional power-saving features like low-voltage islands or body bias voltages.

In this paper, a proof-of-concept prototype of a two-channel frequency-translating hybrid (FTH) analog-to-digital converter (ADC) is implemented using off-the shelf components. The FTH structure is suitable for high-bandwidth ADCs. In this architecture, the wideband input signal is decomposed into smaller frequency subbands (channels). Each channel consists of a two-path system that frequency translates its input signal to baseband, lowpass filters each path signal using identical analog baseband filters, and samples and digitizes each path signal using identical baseband lower-speed ADC circuits. Unlike conventional parallel architectures, sampling is accomplished after splitting the signal into narrow baseband components alleviating the need for high-speed S/H circuitry. After digitizing the signal in each channel, the low-rate subband samples are upconverted back to their respective center frequencies, filtered, and recombined to reconstruct the digital representation of the original wideband input signal. The digital filters are optimized to minimize the reconstruction error. It is shown that the effects of many major analog non- idealities can be compensated in the digital domain.

In this paper, a high-speed encoder intended for a 5GS/S 4-bit flash analog-to-digital converter (ADC) is presented. To meet the speed and power targets of the ADC, low-swing signaling is used in all the internal sub-blocks of the ADC including the encoder. To further enhance the speed performance of the encoder, 2-stage pipelining is utilized. In addition, the encoder is implemented in current mode logic (CML). The circuit is designed and simulated in a 0.18 mum CMOS technology. It consumes 4 mW from a 1.8 V supply while operating at 5 GHz

A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 /spl mu/m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages.

Carbon nanotubes have promising electron emission characteristics. We report on photo-electron emitters made from sparse collections of single-walled carbon nanotubes resting on a silicon dioxide surface. A 266 nm ultraviolet laser was used. The measured emission current suggests a level of optical power absorption of approximately an order of magnitude higher than what is expected purely based on the surface area of the nanotubes; it appears that a more efficient mechanism is at work. We also present simulation results and discuss whether optical antenna effects could provide an insight.