1. Bidirectional Peripheral Nerve Interface With 64 Second-Order Opamp-Less ΔΣ ADCs and Fully Integrated Wireless Power/Data Transmission
- Author
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Jianxiong Xu, Aly Shoukry, Chenxi Tang, Roman Genov, Samantha Unger, Paul B. Yoo, Maged ElAnsary, Liam Long, Parisa Sabetian, Jaimin Joshi, Gairik Dutta, José Zariffa, Jose Sales Filho, Camilo Tejeiro, and Enver G. Kilinc
- Subjects
Physics ,business.industry ,020208 electrical & electronic engineering ,Electrical engineering ,02 engineering and technology ,Signal ,Noise shaping ,law.invention ,Frequency-division multiplexing ,CMOS ,law ,Peripheral nerve interface ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Operational amplifier ,Electrical and Electronic Engineering ,business ,Electrical impedance ,Data transmission - Abstract
An active probe and microstimulator SoC for interfacing with peripheral nerves is presented. It performs 64-channel artifact-tolerant neural recording, cuff imbalance compensation by impedance sensing, and neurostimulation for the closed-loop operation. Each recording channel is a second-order opamp-less $\Delta \Sigma $ ADC that consumes 140 nW and occupies 0.01 mm2 area in 130 nm CMOS. The single-loop $\Delta \Sigma $ architecture achieves second-order noise shaping with two passive integrators. To the best of our knowledge, this yields the lowest power and area of any second-order $\Delta \Sigma $ ADC and the lowest FOM (fJ/conv. step) of any passive second-order $\Delta \Sigma $ ADC (27 fJ/conv. step). The SoC uniquely performs multi-modal input signal recording: voltage (for neural recording) and current (for impedance sensing) are measured concurrently using frequency multiplexing. The SoC also features a 60 MHz energy-efficient inductive powering link and a 600 MHz RF data communication link. The prototype is validated in vivo in the rat sciatic nerve for electroneurogram (ENG) sensing and the correction of impedance-imbalance in cuff electrodes.
- Published
- 2021
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