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Humans spend more than 90% of their day in buildings, where their health and productivity are demonstrably linked to thermal comfort. Building thermal comfort systems account for the largest share of U.S energy consumption. Despite this high-energy cost, due to building design complexity and the variety of building occupant needs, addressing thermal comfort in buildings remains a difficult problem. To overcome this challenge, this paper presents an Internet of Things (IoT) approach to efficiently model and control comfort in buildings. In the model phase, a method to access and exploit wearable device data to build a personal thermal comfort model has been presented. Various supervised machine-learning algorithms are evaluated to produce accurate personal thermal comfort models for each building occupant that exhibit superior performance compared to a general model for all occupants. The developed comfort models were used to simulate an intelligent comfort controller that uses the particle swarm optimization(PSO) method to search for optimal control parameter values to achieve maximum comfort. Finally, a framework for experimental validation of the new proposed comfort controller that interactively works with the HVAC element has been introduced.

In many refrigeration and air-conditioning systems, the automatic controller in electronic expansion valves have been employed as a component responsible for controlling the valve opening so that the superheat at the outlet of the evaporator remains within the desired limits. In most of these controllers, the control parameters are tuned once for a certain operating point and remain unaltered even when the operating conditions change. For a strongly nonlinear plant with a dramatically time varying characteristics, linear time invariant(LTI) prediction accuracy might degrade significantly that the performance of traditional model predictive controller(MPC) becomes unacceptable. This work presents an Adaptive-Model Predictive Control mechanism to address this degradation where the parameters are tuned continuously through recursive estimation and update approaches, making MPC insensitive to prediction errors, so as to achieve the optimal superheat output.

In this paper, the mass optimization of four bar linkages is carried out using genetic algorithms (GA) with single and dual constraints. The single constraint of bending stress and the dual constraints of bending and buckling stresses are imposed. From the movement response of the bar linkage mechanism, the analysis of the mechanism is developed using the combination of kinematics, kinetics, and finite element analysis (FEA). A penalty-based transformation technique is used to convert the constrained problem into an unconstrained one. Lastly, a detailed comparison on the effect of single constraint and of dual constraints is presented.

The present trend in electronics packaging is the stacking of die at the wafer or chip level. However to ensure stacked chip packages maintain overall low height and weight package profile, silicon wafers have to undergo extensive wafer thinning processes. In this work, a systematic approach to thinning silicon wafers down to sub-40μm in thickness is presented. This paper will cover a detailed three stage wafer thinning method, which includes the mechanical back-lapping method for the bulk removal process and a combination of mechanical polishing and spin-spray wet chemical etch method for the fine removal wafer thinning process. The results will show that by just utilizing the mechanical back-lapping and mechanical polishing process the wafers can be easily thinned from 380μm to less than 50μm with ±2.5μm Total Thickness Variation (TTV). These back-lapped wafers are then further thinned by the spin-spray etching method to achieve final wafer thickness of less than 40μm. The paper will also show that by utilizing a modified carrier wafer, the handling of these sub-40μm ultra-thin wafers do not require custom made tools and can be easily integrated into existing wafer handling tools.

Genetic Algorithms (GA) are adaptive search algorithms based on the theory of natural selection and survival of the fittest. In this study, GA was used to derive a thermal compact model of a micro lead frame package. The GA derived model was then used to compute the junction temperature (T/sub j/) of the package for various boundary conditions. The results obtained were checked against simulation results of a detailed thermal model and were found to be within /spl plusmn/1.5% of error. Computational time taken by the detailed finite element model required approximately 4 min whereas the GA derived model took less than 35 s to generate the T/sub j/ of the package. Further, the study shows the feasibility and potential of applying GA as a powerful tool for optimization.

This paper described a novel smart three axis compliant (STAC) interconnect targeted to revolutionize chip-to-chip and chip-to-board high-density 3D integration for ultra-thin Si dies (les75mum) at the wafer level. The STAC interconnect is a three dimensionally compliant interconnect which allows stacked ultra-thin chips to move or flex freely during operation with negligible stress imposed on the die. The paper showed that these interconnects could accommodate mismatches of board or package coefficient of thermal expansion (CTE) from chip CTE. STAC interconnects were fabricated using MEMS technologies to support super-fine-pitch (ap20mum pitch) interconnection. These interconnects are batch processed and die containing them can be stacked either at the wafer-level or at the die-level

A thermal response model for designing thermal energy storage heatsink utilized for electronics cooling is developed in this paper. In this study, thermal energy storage (TES) heatsink made out of aluminum with paraffin as the phase change material (PCM) is considered. By using numerical simulation, stabilization time and maximum operating temperature to transition temperature difference is obtained for varying fin thicknesses, fin height, number of fins and PCM volume. The numerical simulation results were then compared with existing experimental work. The numerical results matched the melting temperature variation obtained by the experimental work. The validated numerical results are then used to train the artificial neural networks (ANN) to predict stabilization time and maximum operating temperature to transition temperature difference for new fin thicknesses, fin height, number of fins and PCM volume. Finally the optimization of the fin thickness, fin height, number of fins and PCM volume of the thermal energy storage heatsink is obtained by embedding the trained ANN as a fitness function into genetic algorithms (GA). The objective of optimization is to maximize stabilization time and to minimize maximum operating temperature to transition temperature difference. Finally the optimized results for the TES heatsink is used to build a new computer model for numerical analysis. The final optimized model results and the validated preliminary model results are then compared. The final results will show a significant improvement from the validated model. Further the study will show that by combining ANN and GA, a superior tool for optimization is realized.Copyright © 2005 by ASME

The current trend in wafer-level three-dimensional integration is by copper-filled through-silicon vias (TSVs) which considerably minimize signal transmission time due to the short wiring length required to integrate vertically stacked chips. However, the present wire bonding technology widely used in peripheral integration of stacked chips cannot integrate TSV based chip stacks. This article describes the fabrication methodology of a thin film compliant interconnect referred to as Smart Three Axis Compliant (STAC) interconnects which can be directly integrated onto TSV based chip stacks. These batch processed compliant interconnects are successfully fabricated utilizing microelectromechanical systems technology at the wafer level by magnetron sputtering oppositely stressed layers of TiW films. Once patterned and released, STAC interconnects easily achieve input/output counts of 104∕cm2 or greater, making it suitable to be directly integrated onto through-silicon-via based chip stacks.