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We present a mixed-signal CMOS front-end cell designed for semiconductor pixel detectors for X-[gamma] ray imaging and spectroscopy. The Readout Pixel Cell (RPC) comprises an analog and a digital section to accomplish all the functionality of a spectroscopic-grade signal readout. The analog section includes a low noise charge preamplifier, a two stage shaper amplifier with digitally selectable shaping times from 1 [micro]s to 10 [micro]s, a baseline restorer, a high precision peak stretcher and an output amplifier. The digital section includes an amplitude discriminator with coarse and fine digital control of the threshold level, a peak discriminator, a current-mode trigger generator, a logic circuit to accomplish the pulse pile-up rejection and the RPC reset after the A/D conversion, the disable functions of the preamplifier and of the discriminators. The RPC has been designed and manufactured in 0.35 [micro]m CMOS technology with a size of 300 [micro]m x 300 [micro]m. The full functionality of the RPC has been successfully tested. At room temperature, the intrinsic equivalent noise charge is 15.7 electrons r.m.s, at 3.3 [micro]s and the minimum noise slope is 22 electrons/pF at 8 [micro]s, the linearitv error is between -1.4% and +1.2% within 1.9 fC input signal dynamic. The RPC has separate voltage supplies (+3.3 V) and grounds for the analog and digital sections and the total power consumption is 495 [micro]W. Index Terms--Application specific integrated circuits, front end electronics, low noise electronics, mixed analog-digital integrated circuits, pixel detectors.

This paper presents a complete read-out channel suitable for large arrays of X-ray detectors to be used for spectrometry applications in space. The system is fully integrated except for the X-ray detector. It basically consists of a front-end circuit for processing the detector signal, a Wilkinson A/D converter for the analog-to-digital conversion and the digital logic required to ensure the correct handshaking between all the blocks of the read-out channel. The system allows us to process the signal provided by the detector down to the final analog-to-digital conversion. All these functionalities are embedded in a single chip that, in its final version, will be bump-bonded to the matrix of X-ray detectors. The chip, designed in a 0.35 [micro]m CMOS technology, achieves an input-referred noise of 34 [e.sup.-.sub.rms], consuming 0.9 mW from a 3.3 V power supply. The on-board A/D converter features 10 bits of resolution with a maximum conversion time of 210 [micro]s. The INL and DNL of the whole read-out channel are equal to [+ or -] 3.3 LSB and [+ or -] 0.2 LSB, respectively. Index Terms--CMOS analog integrated circuits, data acquisition, data conversion, integrated circuits, X-ray spectroscopy.

This paper presents design considerations and implementations of monolithic controllers for smart sensors that make use of micromachined structures such as micromembranes and microcantilevers. Five control techniques are reviewed, and the classic control technique is selected for the design of the controllers. The circuit implementations of an analog proportional controller and a digital proportional-integral-derivative controller are described in detail. The first controller is used for controlling the microhotplate (micromembrane) temperature of a monolithic metal-oxide gas sensor array. The second controller is used for controlling the microcantilever deflection of a monolithic atomic force microscope. The controllers and microsensors are fabricated in standard 0.8-[micro]m CMOS technology combined with post-CMOS micromachining. Chemical measurements and contact-mode imaging are performed to confirm the excellent performance of these monolithic controllers. Index Terms--Analog circuit design, CMOS-based microsensors, proportional (P) and proportional-integral-derivative (PID) control, MEMS.

This paper presents a reconfigurable universal mobile telecommunication systems [(UMTS) and wireless local area network (WLAN) mode)] analog baseband transmitter channel composed of a current steering digital-analog converter (DAC), a transimpedance stage, and a low-pass reconstruction filter. The device operates from a single 1.2-V supply voltage while guaranteeing the high-linearity UMTS/WLAN standard requirements. It can be digitally programmed to process WLAN 802.11a/b/g and UMTS signals, by adjusting the DAC conversion frequency and the low-pass filter cutoff frequency. For the WLAN mode, the DAC operating frequency and the filter bandwidth are set to 100 and 11 MHz, respectively, while for the UMTS mode, they are equal to 50 and 2.11 MHz. The device is realized in a 1.2-V 0.13-/[micro]m standard CMOS technology. The die area occupation, equal to 0.9 [mm.sup.2], has been minimized by optimizing the component sharing for the two operation modes. The proposed circuit achieves a 30.4 dBm third-order output referred intermodulation intercept point (OIP3) for the WLAN mode, and a 31.5 dBm-OIP3 when configured for the UMTS mode, while the spurious-free dynamic range is 58 dB for WLAN mode, and 60 dB for UMTS mode. The power consumption is optimized according to the operation mode and is 19.44 mW in WLAN mode and 16.8 mW in UMTS mode. Index Terms--Digital-analog converter (DAC), reconfigurable system, reconstruction structure, wireless transmitter.

This paper describes a 0.35-[micro]m CMOS fourth-order bandpass analog-digital sigma-delta ([SIGMA][DELTA]) modulator for wideband base stations receivers. The modulator, based on a time-interleaved four-path architecture, achieves an equivalent sampling frequency of 280 MHz, although the building blocks operate at only 70 MHz. In measurements, the prototype chip achieves a dynamic range of 72 dB (12 bits of resolution) with a signal bandwidth of 4.375 MHz centered around an intermediate frequency of 70 MHz. The measured spurious-free dynamic range is 69 dB. The [SIGMA][DELTA] modulator dissipates 480 mW from a 3.3-V supply, including voltage reference buffers and output pads with high-driving capabilities, and occupies 20 [mm.sup.2] of silicon area. Index Terms--Calibration technique, time-interleaved ADC, sigma-delta ([SIGMA][DELTA]) modulator.

In this paper, we propose a digital background adaptive calibration technique for correcting offset and gain mismatches in time-interleaved multipath analog--digital (A/D) sigma--delta ([SIGMA][DELTA]) modulators. The proposed technique allows us to cancel the spurious tones introduced by offset and gain mismatches among the paths only by processing the digital output, without interfering with the operation of the modulator. This solution is also effective for any other time-interleaved A/D converter topology. Simulation results on a high-performance four-path bandpass [SIGMA][DELTA] modulator, operating on a 5-MHz band at a clock frequency of 320 MHz, demonstrate the effectiveness of the proposed calibration technique, which allows us to achieve significant improvements of the signal-to-noise ratio and the spurious-free dynamic range in the presence of mismatches. Index Terms--Analog-digital conversion, calibration, sigma-delta modulation, N-path circuits.

This paper presents a complete set of blocks implemented in the popular MATLAB SIMULINK environment, which allows designers to perform time-domain behavioral simulations of switched-capacitor (SC) sigma--delta ([SIGMA][DELTA]) modulators. The proposed set of blocks takes into account most of the SC [SIGMA][DELTA] modulator nonidealities, such as sampling jitter, kT/C noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). For each block, a description of the considered effect as well as all of the implementative details are provided. The proposed simulation environment is validated by comparing the simulated behavior with the experimental results obtained from two actual circuits, namely a second-order low-pass and a sixth-order bandpass SC [SIGMA][DELTA] modulator. Index Terms--Analog--digital conversion, discrete-time systems, sigma--delta ([SIGMA][DELTA]) modulation.

In this paper, we discuss theoretical and practical issues concerning low-voltage and low-power data converters. By looking at a series of constraints affecting the design of basic elements and building blocks, the paper analyzes different architectures for Nyquist rate data converters and discusses important aspects of low-voltage and low-power operation. Following this, the minimization of power consumption in the very popular sigma-delta technique is considered. A number of hints and indications are provided throughout the paper.