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Silicon quantum dots have been deposited on top of a 3-nm tunnel oxide by Low Pressure Chemical Vapour Deposition (LPCVD) and coated with a 7-nm Chemical Vapour Deposited (CVD) oxide. This stack was then incorporated in Metal-Oxide-Semiconductor structure and used as floating gate of a memory cell. The presence of 3 nm of tunnel oxides allows the injection of the charge by direct tunnel (DT) using low voltages for both program and erase operations. The charge stored in the quantum dots is able to produce a well-detectable flat band shift in the capacitors or, equivalently, a threshold voltage shift in the transistors. Furthermore, due to the presence of SiO 2 between the grains, the lateral charge loss is reduced and, thus, long retention time are possible. In this work we present good memory action characterised by low write voltages, write times of the order of milliseconds and long retention time in spite of the low tunnel oxide thickness. © 2002 Elsevier Science B.V. All rights reserved.

The induced changes of the flatband voltage by the location of holes in a silicon-rich oxide (SRO) film sandwiched between two thin SiO 2 layers [used as gate dielectric in a metal-oxide-semiconductor (MOS) capacitor] can be used as the two states of a memory cell. The principle of operation is based on holes permanently trapped in the SRO layer and reversibly moved up and down, close to the metal and the semiconductor, in order to obtain the two logic states of the memory. The concept has been verified by suitable experiments on MOS structures. The device exhibits an excellent endurance behavior and, due to the low mobility of the holes at low field in the SRO layer, a much longer refresh time compared to conventional dynamic random access memory cells. © 2002 American Institute of Physics.

Double-gate and tri-gate FinFET type memories with nitride (SONOS-like) or Si nanocrystals storage with minimum feature sizes of 10 nm were realized. Strong performance advantages in program / erase characteristics and reliability deeply linked to the FinFET architecture are demonstrated.

FinFETs have been proposed for transistor scaling because of their improved robustness to short channel effects and excellent current drive. Recently, the finFET concept together with discrete trap storage has been studied for Flash memory scaling because of the advantage of reduced floating gate interferences and reduced cell-to-cel cross talk in high-density devices. We have realized Si nano-floating gate (NFM) finFET Flash devices with highly scaled active width and channel length. Improved performances and endurance compared with planar NFM devices are observed in 3D structures (fin width down to 20 nm). Localization of the inversion charge favors low aspect ratio finFET Flash devices with the additional advantage of improved manufacturability.

A novel EPROM (electrically programmable ROM) cell, suitable for production of very-high-density multimegabit memories, is described. The structure is a contactless crosspoint cell whose floating gate is self-aligned to word lines and bit lines. Strong reduction of cell area and contact number is achieved with respect to the conventional cell. Electrical characteristics and reliability behavior of this structure have been studied and are reported together with the fabrication process. It is noted that performances and scalability make this cell interesting for future multimegabit EPROM developments. >

To form crystalline Si dots embedded in SiO2, we have deposited thin films of silicon-rich oxide (SRO) by plasma-enhanced chemical vapor deposition of SiH4 and O2. Then the materials have been annealed in N2 ambient at temperatures between 950°C and 1100°C. Under such processing, the supersaturation of Si in the amorphous SRO film produces the formation of crystalline Si dots embedded in SiO2. The narrow dot size distributions, analyzed by transmission electron microscopy, are characterized by average grain radii and standard deviations down to about 1 nm. The memory functions of such structures has been investigated in MOS capacitors with a SRO film sandwiched between two thin SiO2 layers as insulator and with an n+ polycrystalline silicon gate. The operations of write and storage are clearly detected by measurements of hysteresis in capacitance-voltage characteristics. A model which explains both the occurence of steady-state conduction through the SiO2/SRO/SiO2 stack at a relatively low voltage and the shift of flat-band voltage is presented and discussed. © 2001 Elsevier Science B.V. All rights reserved.

We have studied the effects of nitridation on the leakage current of thin (7-8 nm) gate or tunnel oxides. A polarity dependence of the tunneling current has been found this behavior is related to the presence of a thin silicon oxynitride layer at the SiO2/Si-substrate interface. The oxynitride layer lowers the tunneling current when electrons are injected from the interface where the oxynitride is located (substrate injection). The current flowing across the oxide when electrons are injected from the opposite interface (gate injection) is not influenced by the oxynitride. The increase of nitrogen concentration leads to a decrease of the tunneling current for substrate electron injection.

For the first time, memory devices with optimized high density (2E12#/cm/sup 2/) LPCVD Si nanocrystals have been reproducibly achieved and studied on an extensive statistical basis (from single cell up to 1 Mb test-array) under different programming conditions. An original experimental and theoretical analysis of the threshold voltage shift distribution shows that Si nanocrystals have serious potential to push the scaling of NOR and NAND flash at least to the 35 nm and 65 nm nodes, respectively.