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Gwanghwamun Gate of Gyeongbokgung Palace was dismantled and relocated during the Japanese colonial period, destroyed during the Korean War, reconstructed with reinforced concrete in 1968, and finally erected at its present location in 2010. A pair of Haechi statues located in front of Gwanghwamun was dismantled and relocated several times, and the statues have yet to be returned precisely to their original positions. This study assesses the historical accuracy of their current placement under the Gwanghwamun Square Restructuring Project of the Seoul Metropolitan Government and the Cultural Heritage Administration based on archival photos from the early 1900s, and proposes a method to estimate the original positions of the Haechi through image analysis of contemporary photographs and recent digital camera photos. We estimated the original position of the Haechi before the Japanese colonial period by identifying the shooting location of the archival photo and reproducing contemporary photographs by calculating the angle and distance to the Haechi from the shooting location. The leftmost and rightmost Haechi were originally located about 9.6 m to the east and 7.4 m to the north and about 1.9 m to the west and 8.0 m to the north, respectively, of their current location indicators. As the first attempt to determine the original location of a building and its accessories using archival photos, this study launches a new scientific methodology for the restoration of cultural properties.

Colour is a primary characteristic of visual perception and a very important characteristic to describe cultural heritage works in a variety of shapes, sizes and materials. To quantify colours, portable colorimeters are often carried and used for measuring colour of interest. Spatial resolution of colorimeters is manufacturer and model dependent and typically worse than 3 - 10 mm in diameter. The colour measurement has to be done on site at the time of interest. It poses very significant limitations in colorimetric characterization of cultural heritages. In this paper, the possibility of extraction of colour information from digital photographs, scanned images and video files using customized image processing/analysis software (PicMan) was investigated for cultural heritage characterization applications. As colour information extraction examples, a commercial Gouache paint colour card, a digital photograph, a portrait of a Korean scholar of Joseon Dynasty and a severely deteriorated old medical text book before and after restoration were examined. Colour information from various digital images was successfully extracted from points and regions of interest in RGB, HSV, L*a*b*, Munsell colour and hexadecimal colour code formats. The spatial resolution of colour information extraction is as small as a single pixel in a digital image.

To investigate the effect of implantation temperature on the damage to a Si lattice, room temperature photoluminescence (PL) spectra were measured from highly-channeled MeV 11B+ implanted Si wafers with different implant temperatures (25 °C and 450 °C) after annealing at 950 °C for 3 min in N2. Small pieces from the wafers were used for PL characterization. The implanted Si wafer piece at the elevated temperature resulted in higher overall PL intensity under both excitation wavelengths suggesting lesser lattice damage than the Si wafer implanted at room temperature. Unexpectedly large PL intensity variations were observed from PL area mapping of both wafer pieces. In addition, strange behaviors of localized PL intensity variations, with opposite trends between 670 nm and 827 nm excitation PL measurements were observed near the scribe lines and sample number markings on the backside. The PL intensity was increased under 670 nm excitation while it was decreased under 827 nm excitation. Possible reasons for this strange behavior were discussed based on experimental results and analysis. PL measurement is verified to be very sensitive to the surface condition, interface, bulk and backside conditions of the Si. For reliable PL measurement, backside contamination and scratches, such as scribe lines, should be avoided.

We studied the feasibility of image-based quantitative analysis of foxing stains on collections of old (16th&ndash, 20th century) European books stored in the Rare Book Library of the Seoul National University in Korea. We were able to quantitatively determine the foxing affected areas on books from their photographs using a newly developed image processing software (PicMan) including cultural property characterization applications, specifically. Dimensional and color analysis of photographs were successfully done quantitatively. Histograms of RGB (red, green, blue) pixels of photographs clearly showed the change in color distribution of foxing stains compared to the other areas of the photographs. Several sample images of quantitative measurement of foxing stains and virtually restored images were generated to provide easy visual inspection and comparison between restored images and the original photographs. Image quality, resolution, and digital file format requirements for quantitative analysis are described. Image-based quantitative analysis of foxing stains on paper documents are found to be very promising towards automation for objective characterization of photographs of cultural properties. This technique can be used to create a cultural property digital database. Quantitative and statistical analysis techniques can be introduced to monitor the effect of storage and conservation environment on the cultural properties.

Formation of high integrity junctions with low junction leakage and defects is essential for fabricating high performance devices with advanced node devices. Understanding of implant activation and implant damage recovery mechanisms during annealing process steps is limited. Development of noncontact implant activation and residual damage monitoring techniques would be beneficial.

Formation of low resistivity junctions is essential for fabricating high performance devices with advanced device modes. Significant effort has been expended, industry wide, to develop low resistivity junctions, over the years. However, the understanding of implant activation and implant damage recovery process is not sufficient. Development of noncontact implant residual damage monitoring techniques would be beneficial in process development for advanced node devices. In this study, we have investigated the effect of annealing temperature and time on the sheet resistance (Rs) of dual (P+ 1.0MeV, 4.0 x 1013 cm-2 + B+ 10keV, 3.0 x 1014cm-2) implanted p--Si(100) wafers using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system over a wide range of annealing conditions (350-800oC, 60-150s). Room temperature photoluminescence (RTPL) spectra were measured from all wafers under two different excitation wavelengths (650 and 785 nm) for additional clues on electrical properties of pn junctions, which cannot be obtained from the Rs measurements. Multiwavelength (457.9, 488.0 and 514.5 nm) Raman characterization was done on all wafers for additional insights on the degree of residual lattice damage, after RTA, under different conditions. After all on wafer measurements were completed, secondary ion mass spectroscopy (SIMS) dopant (P and B) depth profiling was done to assess dopant diffusion during the annealing process. Rs values showed strong and systematic change with RTA temperature and time, as expected. RTPL spectra also showed large variations in intensity and wavelength distribution corresponding to the RTA temperature and time. Multiwavelength Raman characterization results showed gradual increase of intensity with the RTA temperature. Three regions of different Raman shift values, corresponding to the Si lattice stress and possibly the degree of residual implant damage, were also noted. SIMS P and B depth profiles did not show significant changes. Correlation among characterization results from various techniques and RTA conditions will be presented.

Wafer-to-wafer bonding is implemented in fabrication of backside illuminated (BSI) complimentary metal-oxide-semiconductor image sensor (CIS) devices in volume manufacturing. A wafer with illuminated imager and a wafer with readout and image processing electronics are fabricated separately and assembled using wafer-to-wafer bonding. Since the illuminated imager and a wafer with readout and image processing electronics are facing each other at the bonded interface, the quality of wafer-to-wafer bonding interface can affect the performance of finished devices. Room temperature photoluminescence (RTPL) technique was studied as a non-contact, in-line characterization technique for assessing bonding interface quality. Ordinary and bonded, 200 mm Si wafers, with different surface finishing conditions, were characterized by RTPL under two different excitation wavelengths (650 nm and 827 nm) to investigate the effects of surface finishing conditions. Significant variations in RTPL spectra and intensity, suggesting potential electrical property variations, were observed from bonded wafers. RTPL characterization results on ordinary and bonded wafers are introduced as a potential technique for in-line bonding interface quality monitoring. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0111604jss] All rights reserved.

We have developed a multi-wavelength, room temperature photoluminescence (RTPL) characterization technique and applied it for very low energy and low dose ion implantation process and equipment monitoring. We have tested the sensitivity and stability of the RTPL technique using 200mm p-type Si (100) wafers with 300eV F+ implantation in the dose range of 1.0 × 1011 cm−2 and 1.0 × 1012 cm−2 and found excellent correlation between RTPL intensity and F+ implant dose. We also verified that F+ implantation damage can be cured by subsequent thermal annealing. The RTPL technique is very promising as a practical means of very low energy and low dose ion implant process and equipment monitoring.

A surface heat-treatment method for semiconductor wafers using a xenon arc lamp is described. High absorption coefficients of silicon wafers in ultra violet (UV) region and short process time made selective surface heating possible. The surface melting of entire 150 mm diameter Si wafers was demonstrated in less than 2 s at a lamp power of 15 kW. By focusing UV light into a limited area on Si wafer surface, surface melting of a selectively exposed area was demonstrated at a much lower lamp power. The surface temperature ramp rate is estimated to be on the order of 1000◦C/s. Si wafers, with various implanted species (P+ ,A s + ,B + and BF2 +) and energies (1 keV‐70 keV), were annealed for implant damage recovery and electrical activation using the Xe lamp under different scanning speeds. Sheet resistance and secondary ion mass spectroscopy (SIMS) depth profiling measurement results from the scanning rapid thermal annealing (RTA) successfully demonstrated the feasibility of the technique in semiconductor RTA processing applications. Electrical activation with desired levels of dopant diffusion can be achieved by optimizing process variables such as lamp power, distance between the lamp and Si wafer, area of light exposure and scanning speed. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any

Wafer geometry and residual stress go through significant changes at different points in the semiconductor manufacturing process flow. Precise wafer geometry measurement is very important to assess process induced wafer geometry change (PIWGC) and minimize pattern overlay in lithography steps of advanced node devices and 3-D (3-dimensional) packaged devices. However, the precise wafer geometry measurement is very difficult due to gravitational wafer sag and interaction between the anisotropy of mechanical properties of Si and wafer supporting configurations. Effects of anisotropy and supporting configuration on 300 mm Si (001) wafer profile measurements were investigated for pattern overlay estimation and process optimization. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0011512ssl] All rights reserved.

Various types of stacked dielectric films are used in complimentary metal-oxide-semiconductor (CMOS) devices in gates, capacitors and device isolation structures. They are also used as insulating materials between conductors, as inter-metal dielectrics (IMD) and inter-layer dielectrics (ILD). The preparation technique, structure and properties of dielectrics strongly influence the quality of the dielectrics/Si interface. Nominally, similar dielectrics/Si structures, even prepared by the same technique, often show different electrical properties depending on subtle differences in process conditions (hidden variables). Monitoring of physical dimensions and chemical compositions of dielectrics often miss unexpected variations in electrical properties. Non-contact electrical property characterization techniques lack lateral resolution and often results in impairment of the dielectrics/Si interface due to strong external electric fields from the measurement process. Alternative dielectrics/Si interface characterization techniques, which can provide insights into electrical properties without external electric field, would be very useful as a complimentary process and material quality monitoring technique. In this study, we have investigated the effect of SiN film deposition techniques on the interface quality of the resulting SiN/SiO2/Si using spectroscopic room temperature photoluminescence (RTPL) under multiwavelength excitation. The sample preparation procedures are as follows. First, ultra thin (~2.2 nm thick), gate oxide quality, thermal oxide films were grown on 300 mm Si(100) wafers. Nominally 5.0 nm thick SiN films were grown on ~2.0 nm thick SiO2/Si wafers using conventional low pressure chemical vapor deposition (LPCVD) and atomic layer deposition (ALD) under various nitrogen source flow conditions. The film thickness was measured (after SiO2 film deposition) before and after SiN deposition using ellipsometry. Figure 1 (a) and (b) show RTPL spectra measured at the center of seven different SiN/SiO2/Si wafers under 650 nm excitation and showing maximum RTPL intensity under 650 nm and 827 nm excitation. Significantly large RTPL intensity variations were measured among the seven SiN/SiO2/Si wafers. The SiN film deposition conditions have modified the underlying SiO2/Si interface characteristics. Non-contact RTPL measurements are very sensitive to the thin film deposition techniques and conditions. It is effective as a complimentary dielectrics/Si process and interface characterization and monitoring technique. Figure 1

Slight differences between supposedly identical process chambers are a well known problem in semiconductor manufacturing. In particular, individual plasma-aided process chambers are difficult to characterize and tune to match each other because plasma is a non-equilibrium state and can leave its “footprint” in subtle ways on a wafer. This process chamber mismatching phenomena was investigated in a dual chamber, commercial, high density plasma chemical vapor deposition system by monitoring SiO2/Si interface quality using multiwavelength room temperature photoluminescence and Raman spectroscopy. Effects on the SiO2/Si interface quality, from altering the gas flow pattern in the plasma process chamber, are also studied. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0161508jss] All rights reserved.

Photoluminescence (PL) spectra from lightly boron (B) doped p − -Si(100) under 488.0 nm Ar + ion laser excitation over the temperature range of 22 K–290 K is presented. Change of PL peak height (maximum intensity), peak position, peak area (areal intensity), full-width-at-half-maximum (FWHM: peak width) were determined as a function of temperature. PL intensity was sharply decreased with temperature increase in the temperature range of 22 K – 170 K and then slowly increased again in the temperature range of 170 K–290 K. Phonon replicas of a relatively sharp band-to-band (or band edge (BE)) PL peak were clearly measured at low temperatures (≤90 K). PL spectra became broader and the phonon replicas were barely distinguishable as the temperature was increased. The envelope of the main PL peak and the broadening of peak width with the Si temperature were qualitatively in good agreement with the Maxell-Boltzmann probability distribution function. The direction of peak position shift with Si temperature change was also in good agreement with the temperature dependence of the Si bandgap. All measured PL spectra were curve fitted using combinations of modified Gaussian function(s) and standard Gaussian function(s). A simplified curve fitting method for broad PL spectra, consisting of the BE peak and band tail peak, using an exponentially modified Gaussian (EMG or ExGaussian) function and a number of standard Gaussian functions, was proposed from a practical usage point of view. Radiative recombination processes in Si and potential industrial applications of the PL characterization technique were discussed. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any

Phosphorous (P+ 1.0 MeV, 4.0 × 1013 cm−2) and boron (B+ 10 keV, 3.0 × 1014 cm−2) implanted p−-Si(100) wafers were annealed with a wide range of annealing conditions (350–800◦C, 60–150 s) in a commercially available hot wall-based, rapid thermal annealing (RTA) system. Significant variations in sheet resistance were observed in different RTA conditions. Secondary ion mass spectroscopy (SIMS) P and B depth profiles did not show significant change. Room temperature photoluminescence (RTPL) spectra were measured from all wafers under two different excitation wavelengths (650 and 785 nm). RTPL spectra showed large variations in intensity and wavelength distribution corresponding to the sheet resistance. © The Author(s) 2015. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0191512jss] All rights reserved.

Multiwavelength room temperature photoluminescence (RTPL) and Raman spectroscopy were proposed as in-line monitoring techniques for characterizing the dielectric/Si interface. As an application example, ∼7.0 nm thick ultra-thin SiO2 films on 300 mm Si wafers, prepared by various oxidation techniques and conditions, were characterized using multiwavelength RTPL and Raman spectroscopy.Specifically,overallqualityoftheultra-thinSiO2/Siinterface(includingpassivationcharacteristics)andSilatticestress beneath SiO2 films are investigated. The overall SiO2/Si interface quality was seen to be very dependent on oxidation technique and process conditions. Within wafer and wafer-to-wafer variations of SiO2/Si interface quality were successfully characterized by RTPL and Raman spectra measurements. For electrical analysis of SiO2/Si-based structures, non-contact corona charge-based, in-line (capacitance-voltage (C-V) and stress induced leakage current (SILC)) measurements were performed and compared with RTPL and Raman characterization results. Surprisingly, significant variations in RTPL intensity at and near the corona charge-based measurement sites, indicated that the corona-based electrical measurement technique, though non-contact, was indeed invasive. The effect of corona-charge based electrical measurements on SiO2/Si interface was permanent and even clearly visible from the back

Undoped and B-doped epitaxial Si1−x Ge x layers on Si(100) were characterized using a long-focal-length, polychromator-based, multiwavelength micro- Raman spectroscopy system. The peak position and full-width at half-maximum of the Si–Si signal from Si1−x Ge x correlates very strongly with Ge content and B concentration. The intensity ratio of the Si–Si peak from the epitaxial layer to the Si peak from the substrate indicates the thickness of the epitaxial Si1−x Ge x layer. Raman characterization results were confirmed by both high-resolution x-ray diffraction and secondary-ion mass spectroscopy. Multiwavelength Raman spectroscopy was used as a practical, noncontact, in-line monitoring technique for Si1−x Ge x epitaxial processes during device manufacture.

Boron-doped, single (∼54 nm) or double (∼21 + 54 nm) Si1−xGex layers were epitaxially grown on 300-mm-diameter p−-Si(100) device wafers with 20 nm technology node design features, by ultrahigh vacuum chemical vapor deposition. The Si1−xGex/Si wafers were annealed in the temperature range of 950–1050 °C for 60 s to investigate the effect of annealing on possible changes of Ge content and Si stress near the Si1−xGex/Si interface. High spectral resolution, micro-Raman spectroscopy was used as a nondestructive characterization technique with five excitation wavelengths of 363.8, 441.6, 457.9, 488.0, and 514.5 nm. Ge diffusion and generation of compressive stress at the Si1−xGex/Si interface were measured on all annealed wafers. Ge diffusion and the accumulation of compressive Si stress after annealing showed significantly different behaviors between single- and double-layer Si1−xGex/Si wafers. Raman characterization results were compared with secondary ion mass spectroscopy and high-resolution x-ray diffraction results.

Stress in Si adjacent to W-filled TSVs has been measured by multiwavelength Raman spectroscopy (probe depth ranging from 290 to 645 nm) and compared to finite element modeling. The stress in Si from the TSVs increases with TSV width and is almost constant at the different depths probed in this study. The Raman signal is mainly due to the sum of the Sx and Sy stress components, perpendicular and parallel to the TSV bars. The Sx component is tensile and the Sy component is compressive, with the Sy component dominant in between the TSVs. However, ~10 um from the edge of the TSV array, the two components are equal in magnitude so that the stress measured by Raman is zero, even though the individual Sx and Sy stresses are considerable. Hence, it is important to use finite element modeling in conjunction with Raman spectroscopy to characterize stresses in TSVs.

The process results on blanket Si and patterned Si wafers are often very different. Process variations in conventional lamp- based rapid thermal processing (RTP) systems due to pattern size, density and structure dependence under nearly identical process conditions are well known as the pattern effect , but without identifying the root cause. As device dimensions shrink, pattern-induced variability of process results increases which significantly affects the process window, device yield and manufacturability. Understanding the underlying physical causes of the pattern effect is very important to systematically improve device performance, yields and manufacturability. In this paper, the impact of device pattern size and density on process variations in RTP steps was analyzed. According to the analysis, diffraction of light from the periodicity of the nanometer scale device features can result in significant local heating near the critical depths for junctions and contacts.

Thermal behavior of 200-mm- and 300-mm-diameter Si (100) wafers during high-temperature rapid thermal processing (RTP) in a single wafer furnace (SWF) is investigated as a function of temperature, pressure, process time, wafer handling method and speed. Significant elastic wafer shape deformation was observed during wafer temperature ramp-up. Slip generation was frequently observed in wafers processed above 1050°C. Size, shape and spatial distribution of crystal defects generated during RTP were characterized using an optical microscope and X-ray topography. The wafer handling method and speed are found to be very important in reducing defect generation during RTP at the given process conditions. Highly reproducible, slip-free RTP results were achieved in 200-mm- and 300-mm-diameter Si (100) wafers processed at 1100°C by optimizing the wafer handling method and speed.

Performance variations and yield loss in advanced Si devices are closely related to the quality of the semiconductor surface and interfaces. These are very significant factors for successful development of advanced devices. In addition, proper implementation of manufacturing processes is critical as devices scale to smaller size and complexity of device structures increase. The importance of proper understanding and control of surface cleaning and passivation of silicon and dielectric/Si interface quality, is more important than ever. Characterization techniques for determining the effectiveness of Si cleaning, surface passivation and the dielectric/Si interface include Auger electron spectroscopy (AES), X-ray photoelectron spectroscopy (XPS), secondary ion mass spectroscopy (SIMS), high resolution cross-sectional transmission electron microscopy (HRXTEM), non-contact I-V, C-V and carrier lifetime measurements. Various chemical analysis techniques are also used for determining contamination sources in manufacturing. While the conventional characterization techniques have been providing useful information on the properties of the dielectric/Si interface, they cannot sufficiently provide substantive clues for many puzzling problems of Si surface cleanliness, Si surface passivation and the dielectric/Si interface. In this paper, overall quality of the Si surface and dielectric/Si interface (including cleanness, passivation and surface recombination characteristics) were characterized using room temperature photoluminescence (PL) spectroscopy. The spatial resolution of PL spectroscopy is tens of microns. To understand the depth distribution of electrically active defects/traps, at or near the Si surface and the dielectric/Si interface, different excitation wavelengths (with different probing depths) were used as the light source. Significant variations in electrically active defects, traps, and contaminants, at or near the surface, and the dielectric/Si interface were found from multiwavelength PL spectroscopic studies of Si with native oxide. Non-contact, multiwavelength PL spectroscopy was able to reveal electrically active defects and characteristics induced by the cleaning process used, which cannot be properly investigated using conventional chemical analysis and dielectric/Si interface characterization techniques.

Si lattice stress at or near the surface, and overall quality of the Si surface and interface were characterized using multi-wavelength, high resolution Raman and photoluminescence (PL) spectroscopy. Depth profiling of Si lattice stress and electrically active defects/traps, at or near the Si surface and interface, was done using ultraviolet (UV) to infrared (IR) light sources, with different probing depths. Significant variations in Si lattice stress, Si bond lengths and electrically active defects/traps were found from Si wafers undergoing various process steps. Visualization of Si surface and interface quality was done on Si wafers following various device fabrication steps.

To meet various physical property requirements of materials for advanced applications for specific devices, combinations of Si/Ge, Ge/Si, Si1-xGex/Si, are frequently introduced in the device fabrication process. Epitaxy, condensation and annealing processes are commonly used. Since a small variation in composition, strain and crystallinity can result in reduced device performance or failure, the composition, strain and crystallinity must be carefully monitored and controlled throughout the manufacturing process. We have studied the dependence of Ge and Si intermixing on annealing temperature and Raman excitation wavelength. Using multiwavelength Raman spectroscopy, we found Ge and Si intermixing in epitaxially grown Ge(100)/Si(100) after successive thermal anneals. Very strong dependence of signal-to-noise (S/N) ratio measurements on excitation wavelength and film structure was observed. Suitable excitation wavelengths must be chosen to properly characterize Si and Ge-based heteroepitaxial layers based on the thickness, stacking order and composition of epitaxial films having different optical properties at different wavelengths. © The Author(s) 2014. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited. [DOI: 10.1149/2.0041502jss] All rights reserved.

Higher failure rates have been observed for devices at or adjacent to areas that have been measured or inspected by in-line x-ray during front end of line process steps. The failures are thought to be related to SiO2/Si interface damage caused by x-ray radiation during routine in-line element, material, and process monitoring. This issue has been noted for highly advanced integrated semiconductor devices following device failure mode analysis of Si wafers, with and without x-ray in-line inspection. A multiwavelength room-temperature photoluminescence (RTPL) study was performed to identify the presence of such damage in x-ray irradiated wafers from various types of x-ray inspection steps during device fabrication processes. It was found that x-ray radiation as low as 16 keV induced damage at the SiO2/Si interface. The damage to the SiO2/Si interface was successfully observed by using multiwavelength RTPL wafer mapping.

The understanding of macro- and micro-scale wafer shape changes during device fabrication process steps is becoming very critical in developing and optimizing advanced technology node devices in which new materials such as Ni, NiPt and/or Ge are introduced. We have developed a non-contact, in-line process and/or material property monitoring method which uses various forms (reflection, diffraction, interference and scattering) of interactions between semiconductor wafers and a laser beam. Laser spike anneal (LSA) induced changes of surface profiles in TiN/NiPt/Si 1−x Ge x /Si (100) and Si 1−x Ge x /Si (100) wafers are characterized using the newly developed very high magnification optical surface profilometry (OSP-300) system. Significant global and local changes of wafer surface profiles were observed after LSA. Multi-wavelength micro-Raman studies revealed significant changes in Ge content and lattice level stress in Si 1−x Ge x /Si (100) wafers annealed under various LSA temperatures and dwell times.

The design concept of a polychromator-based multi-wavelength Raman spectroscopy system (MRS-300) which is designed to overcome the common issues with conventional Raman measurement systems is described. The system is specially designed for non-destructive, material and process characterization applications in the semiconductor industry. The performance of the MRS-300 system and non-destructive nature of the tests of lattice stress/strain and Ge content were demonstrated using mechanically stressed Si samples and epitaxially grown Si 1-x Ge x samples. The capability of very high measurement resolution (0.105cm−1/pixel or better), accuracy repeatability (0.05cm−1 or better) and repeatability (0.05cm−1 or better) of the system were demonstrated at all three excitation wavelengths (457.9nm, 488.0nm and 514.5nm). Possibility of MRS-300 applications as an in-line process monitoring system was also introduced with an example of long term measurement stability and repeatability data.

Rapid thermal scanning for activation of dopants is proposed for applications in advanced junction formation. The proposed rapid thermal scanning dopant activation technique was found to be very effective for both deep and shallow implanted junctions while providing enhanced activation parameter control capability.

Low resistivity junctions and low resistivity contacts are essential for fabricating high performance devices with advanced device modes. Significant effort has been expended to develop low resistivity junctions, industry wide. However, low resistivity contact formation has not received significant attention, other than changing the silicide of choice, depending on required minimum line width or device node. Once the candidate silicide material is chosen for the device node, relatively small improvement in resistivity has been made in recent years, despite silicidation process optimization which include modifications of process steps and integration schemes. In this study, we have investigated the effect of annealing temperature and time on the resulting resistivity of Co2Si contacts with P-doped poly-Si using a single wafer furnace-based (hot wall) rapid thermal annealing (RTA) system. The hot wall RTA resulted in significantly (>20%) lower Rs, down to 19.6 ohm/sq. from equivalent RTA process using conventional tungsten halogen lamp-based (cold wall) RTA systems over a very wide process window (RTA temperature and time). Secondary ion mass spectroscopy (SIMS) dopant (P) depth profiling results revealed that the P atoms in the CoSi2 film and at the CoSi2/P-doped poly-Si interface, redistribute very differently under different RTA conditions. The same Rs value can be realized by different P profiles resulting from different RTA conditions. To enable contact resistance reduction, P pile-up near the CoSi2/P-doped poly-Si interface for and to suppress P depletion from P-doped poly-Si layer for resistivity reduction, lower temperature RTA for longer times in the hot wall RTA system was found to be beneficial. Wafers with almost identical P depth profiles after CoSi2 formation RTA in the cold wall RTA and the hot wall RTA systems, still showed an Rs difference of ~20%. The wafers annealed in the hot wall RTA system always showed lower Rs values indicating higher P dopant activation in the P-doped poly-Si layer. The difference in wafer heating mechanisms between the cold wall (lamp-based) RTA and the hot wall (furnace-based) RTA may have played an important role in the dopant activation and Rs differences. Hot wall RTA is very promising for realizing the low resistivity contacts required in advanced high performance devices. The simple change of annealing technique may extend the life cycle of CoSi2/P-doped poly-Si contacts. The Rs response surface (as a function of RTA temperature and time) and SIMS depth profiles of P atoms will be presented at the meeting. Figure 1

Ultraviolet (UV) Raman scattering spectroscopy provides new insight into the recrystallization process versus depth in the ultra-shallow ion-implanted layer not provided by conventional characterization techniques. The recrystallization process in ultra-shallow B-implanted layers on silicon was characterized by Raman scattering spectroscopy under UV excitation. To recrystallize damaged layers after ion implantation, rapid annealing processes were carried out in both a millisecond flash annealing system and a spike annealing system. The effectiveness of this anneal is compared to Raman evaluation of non-USJ, B-implanted layers with hundred nanometer scale depth thoroughly annealed in a near isothermal hot wall chamber. By making use of the shallow penetration depth of UV light in silicon, we can distinguish Raman signals of single-crystalline, deficiently recrystallized, as well as amorphous silicon. Although, a clear, single crystalline lattice image was observed by transmission electron microscopy (TEM), the UV-Raman spectroscopy also sensitively detected deterioration of the lattice, but in nondestructive testing.

Various suicides are being used as ohmic contact materials for advanced silicon technologies. Due to the requirements for low contact resistance, no linewidth dependence and minimal thermal budget, different suicides are being adopted and modified to achieve the optimum characteristics. TiSi2 has been used to the 130 nm technology node with CoSi2 to the 100 nm node. Recently NiSi is being used to address 90 nm technologies and beyond. The formation of the various suicides was investigated using a single wafer rapid thermal furnace (SRTF) in the temperature range of 200degC to 1000degC. Utilizing an isothermal cavity process chamber, excellent temperature repeatability and uniformity can be achieved allowing investigation of the temperature sensitivity of the silicide formation. A 2-step process was used to minimize silicon consumption and control the diffusion of metal into the underlying materials, silicon, poly-Si and amorphous Si. The above mentioned suicides were investigated as used in manufacturing and the processing limits determined

Three dimensional (3D) vertical NAND (V-NAND) flash technology has been actively investigated. [1] 3D NAND architectures offer one of the best combinations of device performance, memory density, power consumption and manufacturing cost. All major memory device manufacturers are actively pursuing development of commercially viable devices. Development of bit cost scalable (BiCS) NAND technology is very important from both technology and commercialization points of view. Device scaling was achieved by vertical staking of thin film transistors (TFTs) in contrast to the conventional planar device scaling techniques relying on advances in lithography. Poly-Si is used as channel materials in 3D V-NAND flash memory devices. Control of both poly-Si grain size and grain size distribution is very important for tight control of device yield and performance variations. For poly-Si channel fabrication, amorphous Si (a-Si) film is deposited in the channel region and then converted to poly-Si by thermal annealing. To achieve desired properties of the poly-Si channel, grain size, resistivity, mobility and interface quality must be carefully monitored and controlled. One of the basic parameters of the poly-Si channel is grain size. Smaller grains lower in channel carrier mobility while larger grains increase device performance variations. The grain size and its distribution have to be optimized for the best device performance. Development of proper in-line characterization techniques for poly-Si grain size, after thermal annealing, is strongly desired. In this paper, Raman spectroscopy was used for characterizing poly-Si after thermal annealing of chemical vapor deposited (CVD) thin a-Si films on SiO2/Si wafers. The a-Si films on SiO2/Si wafers were annealed in a single wafer rapid thermal furnace (SRTF-300 system [4, 5]) in the temperature range of 600 ~ 1050oC under various ambient gases. Systematic change of Raman spectra, indicating crystallization of a-Si films and grain growth of poly-Si with annealing temperature increase was measured (Fig. 1.) using an MRS-300 system. [6] As deposited a-Si/SiO2/Si showed one sharp peak from the Si wafer at ~ 520.3cm-1 and one broad peak centered at ~ 480cm-1 corresponding to a-Si. After thermal annealing, the a-Si peak decreased in intensity and transformed into new peaks at ~ 495 and ~ 515 cm-1, corresponding to poly-Si. The poly-Si peaks increased and sharpened as the annealing temperature increased. The change of Raman spectra indicates the degree of polycrystallization and grain growth under different annealing conditions. Figures 2 and 3 showed the Raman spectra from the annealed samples and their deconvolution results. Detailed Raman characterization, as a function of annealing temperature and type of ambient gas, will be reported at the conference. References 1. G. S. Kar, G. Van den bosch, A. Arreghini, I. Debusschere, J. Van Houdt and L. Altimime, ECS Transactions, 44 (1) (2012) 431. 2. M. K. Jeong, S. M. Joe, H. J. Kang, J. H. Bae, K. R. Han, E. Choi, G. Cho, S.K. Park, B. G. Park and J. H. Lee, IEDM Tech. Dig., (2012) 207. 3.S. J. Choi, J. W. Han, S. Kim, D. I. Moon, M. Jang and Y. K. Choi, Symp. on VLSI Tech. Dig., (2010) 111. 4. W.S. Yoo, T. Fukada, H. Kuribayashi, H. Kitayama, N. Takahashi, K. Enjoji and K. Sunohara, Jpn. J. Appl. Phys., 39 (2000) 6143. 5. W.S. Yoo, T. Fukada, I. Yokoyama, K. Kang and N. Takahashi, Jpn. J. Appl. Phys., 41 (2002) 4442. 6. W. S. Yoo, K. Kang, T. Ueda and T. Ishigaki: Appl. Phys. Exp., 2 (2009) 116502.

Advanced metal-oxide-semiconductor (MOS) and metal-insulator-semiconductor (MIS) devices employ ultra thin dielectric gate layers. The physical dimensions are in the range of single digit to double digit nanometers. The effective oxide thickness (EOT) is significantly less than 10 nm. Pure SiO2 or combinations of SiO2and SiN layers are typically used as gate dielectrics. High dielectric constant materials (high-k dielectrics) and metal gates are also frequently used, depending on chip design. Physical dimensions of dielectric layer(s) are typically measured using ellipsometry and high resolution cross-section transmission microscopy (HRXTEM). Electrical characteristics are typically characterized using either contact or non-contact C-V and I-V measurements tools. Non-contact characterization techniques are generally preferred for in-line monitoring applications. However, spatial resolution of non-contact C-V and I-V measurement techniques is in the range of a few millimeters, which are 3 orders of magnitude larger than typical dimensions of actual devices. High spatial resolution, non-contact dielectric/Si interface quality characterization techniques must be developed. In this paper, ultra thin (~7 nm) SiO2/Si and ultra thin SiN/SiO2/Si wafers were prepared by low pressure thermal chemical vapor deposition (CVD) and thermal oxidation. Dielectric/Si interface quality was characterized by room temperature spectroscopic photoluminescence (PL) measurements. The PL intensity and spectra from Si were measured under different excitation wavelengths which have different probing depths. PL is an optical characterization technique which does not require any sample preparation and physical contact. Typical spatial resolution is in the range of a few microns. Small variations in dielectric/Si interface quality modulates electronic carrier behaviors significantly which results in large variations in PL intensity and spectra. Significant variations in PL intensity and spectra were measured from ultra thin (~7 nm) SiO2/Si wafers prepared by and low pressure thermal CVD and thermal oxidation. Si wafers with thermal oxide films generally showed significantly stronger PL intensity than Si wafers with thermal CVD grown oxide films (Fig. 1). Trends in PL intensity and spectra indicate the SiO2/Si interface quality of the thermally oxidized SiO2/Si is superior to that of the thermal CVD grown SiO2/Si (Fig. 2). PL characterization is found to be very sensitive to the integrity of dielectric/Si interface and thus, is promising as an in-line, non-contact interface quality monitoring technique. The excitation wavelength dependence of PL intensity and spectra of SiO2/Si and SiN/SiO2/Si will be discussed along with conventional physical and electrical characterization results.

Multiwavelength, high resolution micro-Raman spectroscopy was applied to in-line process monitoring and diagnostics of undoped and B-doped Si1-xGex epitaxy on Si(100) device wafers. This noncontact technique was used to monitor the Ge content, B concentration and thickness of single and double Si1-xGex epitaxial layers. Epitaxial process problems were diagnosed nondestructively. Raman peak positions and full-width-at-half-maximum of the Si-Si peak(s) from the Si1-xGex epitaxial layer(s) and Si substrates, in the wavenumber range of 475 ∼ 535 cm-1, were monitored under ultraviolet and visible excitation wavelengths. The Ge content, B concentration and Si1-xGex epitaxial film structures were verified by secondary ion mass spectroscopy (SIMS) depth profiling results. In-line monitoring of Si-Si and Si Raman peaks is very effective in noncontact material property characterization, epitaxial process optimization, and quality control applications.

Micro-Raman spectroscopy is a very attractive non-destructive in-line technique for characterizing stress/strain of the crystal, as well as crystallinity and Ge content in Si1-xGex. Additionally it requires no sample preparation, provides sub-micron spatial resolution, and requires relatively short measurement time. A polychromator-based, high resolution, multi-wavelength Raman spectroscopy system was evaluated from a manufacturing perspective as a candidate for in-line stress/strain monitoring equipment. Short-term and long-term measurement repeatability and system stability were extensively evaluated using five patterned Si1-xGex/Si(100) wafers with nominal Ge content in the range of 15~35 at% (in 5 at% increments). Three major spectral lines (457.9, 488.0 and 514.5 nm) from a multi-wavelength Ar ion laser were used as the excitation source. The short-term and long-term measurement repeatability was evaluated for three months. A very small range of total variation, less than 0.05cm-1, was measured under all three excitation wavelengths.

A wafer goes through global and local surface profile and strain/stress changes during various process steps. Process induced deformation and/or local strain can cause depth of focus problems in photolithography steps and can result in pattern overlay problems as well as errors in critical dimensions and tolerances in nanometer scale devices. Understanding process induced global and local deformations and stresses, at the wafer, die, micro-area, and device level, is very important in developing high performance devices for advanced technology nodes. We have developed a non-contact, in-line process and/or material property monitoring method which uses various forms of interactions (reflection, diffraction, interference, elestic scattering and inelastic scattering) between semiconductor wafers and a laser beam. The laser-based optical surface profilometry (OSP-300) system (Fig.1) has the resolution required to measure the sub-nanometer lateral distortion and sub-nanometer height variation required for advanced semiconductor device research and development. [1] This tool allows an estimation of average stress over the wafer by measuring surface deformation point by point. Multi-wavelength Raman spectroscopy (MRS-300) system was also developed as an in-line stress/strain and crystallinity monitoring tool. [2,3] The system has three thermoelectrically-cooled charge coupled device (CCD) cameras that can measure Raman peaks from three different excitation wavelengths without any disruption (i.e., without scanning the monochromator or switching the excitation laser). Three major spectral lines (457.9, 488.0 and 514.5nm) from a multi-wavelength Ar ion laser are used as the excitation source for depth profiling. This technology measures the Raman shift of lattice sites in the silicon which is well correlated to stress in the microvolume represented by the illumination spot as it penetrates into the silicon.

Three dimensional (3D) stress distributions in Si, surrounded by copper (Cu) filled through silicon vias (TSVs) with various dimensions and pitches, are non-destructively characterized and stress contour maps generated at different depths using a long focal length, polychromator-based, multi-wavelength micro-Raman spectroscopy system. It was found that stress and crystallinity in Si (in both planar and depth directions) was strongly influenced by the proximity to a TSV, as well as, the dimensions of the TSV. In addition to characterizing semiconductor materials, Multi-wavelength micro-Raman spectroscopy was extremely effective for characterizing process-induced variations in crystalline stress and quality where 3D interconnects and packaging technology is introduced.

During the steps of semiconductor processing, a wafer goes through global and local (macro and micro) surface profile and strain/stress changes due to chemical reactions and physical changes brought about by changes in the wafer's environment. In the case of Si1-xGex/Si, intentional local strain generation is introduced to enhance device performance by adding tens of atomic percents of Ge in Si. Process induced surface profile changes in TiN/NiPt/Si1-xGex/Si (100) and Si1-xGex/Si (100) wafers are characterized before and after various annealing techniques and conditions using the newly developed, very high magnification optical surface profilometry (OSP-300) system. Spike anneal steps induced significant global and local changes of wafer surface profiles in TiN/NiPt/Si1-xGex/Si (100) and Si1-xGex/Si (100) wafers, which were compared to a conventional lamp-based RTP step.

Design concepts of a newly developed multi-wavelength, micro Raman spectroscopy system for non-contact and non-destructive characterization of semiconductor materials and its performance are introduced. The system is designed to sequentially measure Raman signals under various excitation wavelengths without sample movement or calibration between switching of excitation wavelengths. Area maps of Raman shift, full-width-at-half-maximum (FWHM) and intensity from an advanced memory device were generated and stacked in the order of wavelength (or penetration depth). This unique display of Raman shift, FWHM and intensity, corresponding to crystalline stress, crystallinity and/or scattering probability provides powerful insights into the sample under characterization.

Sheet resistance and surface profiles of TiN (~10nm thick) capped, Ni films (~30nm thick) on (100) oriented p-type 300mm blanket Si wafers were measured using a conventional four point probe and WaferMasters' optical surface profilometer (OSP-300) system. Process induced surface profile changes were characterized and traced between process steps. Measurements were done after NiSi formation using WaferMasters SAO-300LP (stacked annealing oven) system and removal of the TiN capping layer and unreacted Ni layer by wet etching. Annealing of the NiSi formation was done in the temperature range of 200~425oC in N2 at 1 atmosphere for 5 min. Significant changes in wafer surface profile were observed near the phase transition (Ni/Si→Ni2Si→NiSi) temperatures as determined by the temperature sensitivity curve of sheet resistance. Wafer surface profiles became flatter after wet etching due to the release of build up between the TiN capping layer and the nickel silicide layer. The origin of the wafer distortion after annealing was found to be at the interface between the TiN capping layer and the silicide layer.