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The use of capacitive sensors in the automotive context opens new possibilities in the development of new interfaces for machine interaction with the vehicle occupants. Large smart surfaces with gesture recognition will possibly be part of such new interfaces. However, the data processing cost of such new sensors should be maintained at a minimum while increasing the complexity of their gesture recognition accuracy by using modern deep-learning approaches. In this paper, we introduce the use of Bayesian optimization with execution platform constraints to implement accurate gesture recognition sensors based on 1D capacitive sensor arrays. Various RNN-based designs are implemented and optimized for their execution on embedded automotive microcontrollers. We show that LSTM and GRU-based designs are especially adequate achieving an average recall of the gesture classes over 95% in less than 100 optimization steps.

The advent of machine learning (ML) methods for the industry has opened new possibilities in the automotive domain, especially for Advanced Driver Assistance Systems (ADAS). These methods mainly focus on specific problems ranging from traffic sign and light recognition to pedestrian detection. In most cases, the computational resources and power budget found in ADAS systems are constrained while most machine learning methods are computationally intensive. The usual solution consists in adapting the ML models to comply with the memory and real-time (RT) requirements for inference. Some models are easily adapted to resource-constrained hardware, such as Support Vector Machines, while others, like Neural Networks, need more complex processes to fit into the desired hardware. The ADAS hardware (HW platforms) are diverse, from complex MPSoC CPUs down to classical MCUs, DPSs and application-specific FPGAs and ASICs or specific GPU platforms (such as the NVIDIA families Tegra or Jetson). Therefore, there is a tradeoff between the complexity of the ML model implemented and the selected platform that impacts the performance metrics: function results, energy consumption and speed (latency and throughput). In this paper, a survey in the form of systematic review is conducted to analyze the scope of the published research works that embed ML models into resource-constrained implementations for ADAS applications and what are the achievements regarding the ML performance, energy and speed trade-off.

Gait analysis has evolved significantly during last years due to the great development of the Medical Internet of Things (MIoT) platforms that allow an easy integration of sensors (inertial, magnetic and pressure in our case) to the complex analytics required to compute, not only relevant parameters, but also meaningful indexes. In this paper, we extend a previous development based on a fully wireless pair of insoles by implementing an updated version with more reliable and user-friendly devices, smartphone app and web front-end and back-end. We also extend previous work focused on fall analysis (with the corresponding fall risk index or FRI) with the proposal of a new surgery recovery index (SRI) to account for the individual speed recovery speed that can be measured either at clinical facilities or at home in a telemedicine environment or while doing daily life activities. This new index can be personalized for different types of surgeries that affect gait such as hip, knee, etc. This paper presents the case of hip recovery and is built on top of the clinical standard SPPB test and allows obtaining quantitative parameters directly from the sensors.

Augmented reality is showing a continuous evolution due to the increasing number of smart glasses that are being used for different applications (e.g. training, marketing, industry, risk avoidance, etc.). In this paper, we present an implementation that uses augmented reality (AR) for emergency situations in smart buildings by means of indoor localization through the use of sub-GHz beacons. This also includes the mapping of emergency elements in the three-dimensional building, together with some example cases.

Pedestrian detection is one of the key problems in the emerging self-driving car industry. In addition, the Histogram of Gradients (HOG) algorithm proved to provide good accuracy for pedestrian detection. Many research works focused on accelerating HOG algorithm on FPGA (Field-Programmable Gate Array) due to its low-power and high-throughput characteristics. In this paper, we present an energy-efficient HOG-based implementation for pedestrian detection system on a low-cost FPGA system-on-chip platform. The hardware accelerator implements the HOG computation and the Support Vector Machine classifier, the rest of the algorithm is mapped to software in the embedded processor. The hardware runs at 50 Mhz (lower frequency than previous works), thus achieving the best pixels processed per clock and the lower power design.

Neural Architecture Search (NAS), which allows for automatically developing neural networks, has been mostly devoted to performance on a single metric, usually accuracy. New approaches have added more objectives, such as model size, in order to find networks suitable for resource-constrained platforms. SpArSe [1] is a multi-objective Bayesian optimization framework for automatically developing image classification convolutional neural networks (CNNs) for micro-controller units (MCUs). In this work, we first implement SpArSe and modify it to reduce search time, obtaining similar results regarding accuracy, model size, and maximum working memory but in less optimization time. Moreover, we extend the search space to include recurrent neural networks (RNNs) and add an inference latency objective for time-constrained tasks. Finally, we test our implementation in a gesture recognition task obtaining better results than previous manually tuned approaches for size and performance metrics, which validates the approach and its utility.

Capacitive sensing offers new possibilities for HMI product development. Its short range of interaction entails robustness against environmental noise and its flexibility for integration makes it a genuine technology for embedded systems. In the automotive context, capacitive sensing is explicitly devoted to driver interaction with car functionalities. However, the increasing complexity of captured signals and related interaction procedures impose severe difficulties for a classic modelling approach. Neural networks have demonstrated unbeatable performance in tasks with abundant data. Specifically, recurrent neural networks (RNNs) show excellent performance for tasks with inherent temporal structure. In this article, we develop a capacitive-sensing module that includes RNN-based dynamic gesture recognition, which has a suitable implementation size for embedded automotive applications.

In this paper we present a novel method to print paper and cardboard without ink. The method is based on the carbonization of paper by a combination of lasers working on different wavelengths. A prove of concept system is created based on combining existing commercial systems to demonstrate the viability of the method. The results show that no debris is generated and the quality of the mark is superior in terms of contrast and resolution with previously known methods.

The creation of visible changes marked onto object surfaces by laser has become an effective way of coding industrial products. Industrial applications for printing solutions drive the demand for higher speed and higher throughput for in-line digital laser marking. Currently, most laser marking equipment is based on a single laser beam with the corresponding sequential processing that culminates in a performance bottleneck which limits printing production line speed to a de facto barrier of 8 m/s. In this paper, we present a system that overcomes this barrier by using a matrix of laser beams controlled by an embedded high-performance computing platform. The industrialized solutions presented in this paper can print images of 50 to 200 dpi resolution on printing substrates widths ranging from 6 mm to 50 mm, at product line speeds of up to 16 m/s. The analysis we have performed suggests that even higher speeds could be achieved by investing in additional laser beams.

Organic electronics is one of the most promising technologies for creating flexible electronic devices using low temperature plastic compatible processes. However, contact resistances of organic transistors remain one of the most significant hurdles to achieving high performance circuits in this technology. Short channel devices (

Implementation of organic digital circuits (or printed electronic circuits) has been under an extensive investigation, facing some critical challenges such as process variability, device performance, cell design styles and circuit yield. Failure in any single Organic Thin Film Transistor (OTFT) often causes the whole circuit to fail since integration density is still low. For the same reason, the application of fault tolerant techniques is not that popular in these circuits. In this paper, we propose an approach for the direct mapping of digital functions on top of new prefabricated structures: Inkjet-Configurable Gate Arrays (IGA). This alternative has two main advantages. First, it helps to obtain high yield circuits out of mid-yield foils, and second, it allows implementing individual circuit personalization at a very low cost by using additive mask-less printing techniques thus avoiding the need for OTPROM-like (or E2PROM) devices. All along the design process of IGA cells and structures we used the scalability and technology-independent strategies provided by parameterizable cells (PCell) what helps dealing with current fast technology evolution.

In the last years there has been a growing interest in the realization of low-cost, flexible and large area electronic systems such as item-level RFID tags, flexible displays or smart labels, among others. Specifically, inkjet printing technology has been increasingly applied as advanced deposition technology in the field of printed electronics due to the high flexibility in terms of patterns (mask-less) and materials, and its low cost approach as only a small amount of materials is required in comparison to other solution-based deposition techniques. Our work focuses on the development of Organic Thin Film Transistors (OTFTs) by using organic, inorganic inks and low-cost all-inkjet purely printing process, thus centring the effort in the design, manufacturing and characterization point of view in order to fabricate all-inkjet printed organic integrated circuits. Electrical and morphological characterizations were performed in order to obtain device statistics to investigate the origins of the failures responsible for the low yields. Most of research works are based on laboratory inkjet equipment for manufacturing using single nozzle systems to fabricate small numbers of devices. The variability and mismatch of the printed devices are underrepresented in literature and are key factors towards commercialization of printed electronics.

Over the last decades, Organic Electronics has been emerging as a multidisciplinary and innovative way to generate electronic devices and systems. It is intended to provide a platform for low-cost, large-area, and low-frequency Printable Electronics on a variety of substrates, including flexible plastic substrates. Just as the first information revolution caused by integrated silicon circuits, PE is expected to cause another revolution characterized by the distribution of information systems in all aspects of life. Although the integrated circuits, based on Organic Thin Film Transistors (OTFT), are not meant to compete with the silicon-based high-end industry, their performance have already reached to a level enabling the use of organic technology to an ever-increasing number of emerging applications, such as flexible optical displays, sensors, and low-end microelectronics. Currently, most of the digital integrated circuits are yet designed by specifying the layout of each individual transistor and their interconnections. Full-custom design is extremely labor-intensive, time consuming for complex circuits and it requires advanced computer software in the design process, and several expensive mask sets in the fabrication process. Besides, taking the soft and hard faults at transistor level into account, the yield at system level is expected to be very low, since failure of one transistor causes the entire circuit to fail. This is more important for technologies based in non-crystalline materials (such as silicon) in which deposition and layer formation is more irregular. On the other side, organic electronics is more complex than Printed Circuit Boards (PCB) in the sense that these do not include active devices and do not reach high integration level. Furthermore, similar to any new-born technology, the performance of organic electronic circuits is degraded due to some limitations in technological and materials sides. That being said, the question arises as to whether circuit design techniques can be employed to compensate these bottlenecks so as to meet yield and performance requirements. The work presented in this thesis contributes to overcome the above-mentioned issues by proposing the novel concept of Inkjet-configurable Gate Array (IGA) as a designmanufacturing method for the direct mapping of digital functions on top of new prefabricated structures. IGA brings together the advantages of semi-custom gate array methodology, field-configurability, and fault-tolerance, and adopt it to Application Specific Printed Electronic Circuit (ASPEC), which is the equivalent term to Application Specific Integrated Circuit (ASIC), but for PE. This alternative has two main advantages. Firstly, it allows implementing individual circuit personalization at a very low cost through the best use of additive mask-less digital printing techniques (e.g. Inkjet, Superfine Jet, and etc.) "in the field", thus avoiding the need for One Time Programmable ROM-like (or E2PROM) devices. Secondly, fault tolerance technique allows the adoption of a failure map to use only working transistors for circuit implementation, thus, it helps to obtain high yield circuits out of mid-yield foils.

The objective of the present research is to observe to what extent the stereoscopic effect presents a solution for enhancement of user interactions in the Web context. This paper describes an experiment conducted to detect differences in perception between 2D and 3D graphical user interfaces of an e-Commerce web application. The results of the conducted user study among 39 participants indicate significantly higher performance of the 2D interface in terms of efficiency, satisfaction, and, consequently, overall usability. Therefore, for the studied sample, the stereoscopic effect had mostly negative impact on user interactions. El objetivo de la presente investigación es observar hasta qué punto el efecto estereoscópico es una solución para mejorar la interacción del usuario en el contexto Web. Se describe un experimento llevado a cabo para detectar diferencias de percepción entre las interfaces gráficas de usuario 2D y 3D de una aplicación web de comercio electrónico. Los resultados del estudio de usuarios, llevado a cabo con 39 participantes, indican un rendimiento significativamente más alto de la interfaz 2D en términos de eficiencia, satisfacción y, en consecuencia, facilidad de uso general. Por lo tanto, para la muestra estudiada, el efecto estereoscópico tuvo un impacto mayormente negativo en las interacciones del usuario.

This article describes the web application called S3Doodle. It is an initial example of the combination of a stereoscopic graphical user interface that produces stereoscopic content and is controlled by hand gestures. The web application uses core stereo 3D concepts and implements them with cutting edge technology to create a differentiated experience. We use a spatial input control as an interface that allows us to introduce depth into the created compositions. S3Doodle’s creation is documented, and the experience we had while building it is explained, shedding light on which are the technical decisions behind. We also gather user’s comments from the utilization of the web app. This application serves us as a case study for exploring gestural and stereo interactions, from which we get initial reactions upon which we can provide a better experience for future applications.

Pedestrian detection is a vital function of the emerging autonomous vehicle industry. HOG is widely used as the feature extractor for pedestrian detection thanks to its high accuracy despite the fact that it is computationally expensive. Hardware accelerators using GPUs or FPGAs are used in several proposals to address its real-time execution. There is always a trade-off between real-time processing, energy efficiency and accuracy in the existing solutions. In this paper, we present a pipelined implementation of HOG feature extraction on a low-cost Cyclone V SoC FPGA platform. The design is provides a latency of 4ms for every 640×480 input frame, which corresponds to 250fps. The whole detection system reduces the power consumption by 53.3% and 96% compared with state of the art FPGA and GPU alternatives.

In this paper we focus on the creation of a tool that alows us to put stereoscopic depth into a web page. We also explore with an experiment to what extent this stereoscopic depth may control a user's gaze pattern while performing a search task. The tool uses HTML5 to create 3D stimuli compatible with stereo displays. The stimuli created consists of a search engine result page created in a 2D and 3D side by side format. We then test the stimuli with eye tracking equipment and perform a questionnaire that gathers information about participants' opinion towards a stereoscopic 3D experience. While this experiment is a first pilot and more research is needed, it is indicative of user behavior. In this paper we describe preparations for the study, hardware and software tools used to carry out the experiment, and results analysis.

The operational stability of all-inkjet printed transistors is reported. At room temperature the threshold voltage shifts following a stretched exponential with a relaxation time τ=1x103 s. Two distinct trap sites active in different temperature ranges, one at 200-250 K and other above 310 K cause the electrical instability. Both types of traps capture holes and can be fast neutralized by photogenerated electrons. Optically induced detrapping currents confirm the differences in trap signature. It is proposed, that the traps have a common physical origin related to water.

Reconfigurable parallel computing is required to provide high-performance embedded computing, hide hardware complexity, boost software development, and manage multiple workloads when multiple applications are running simultaneously on the emerging network-on-chip (NoC)-based multiprocessor systems-on-chip (MPSoCs) platforms. In these type of systems, the overall system performance may be affected due to congestion, and therefore parallel programming stacks must be assisted by quality-of-service (QoS) support to meet application requirements and to deal with application dynamism. In this paper, we present a hardware-software QoS-driven reconfigurable parallel computing framework, i.e., the NoC services, the runtime QoS middleware API and our ocMPI library and its tracing support which has been tailored for a distributed-shared memory ARM clustered NoC-based MPSoC platform. The experimental results show the efficiency of our software stack under a broad range of parallel kernels and benchmarks, in terms of low-latency interprocess communication, good application scalability, and most important, they demonstrate the ability to enable runtime reconfiguration to manage workloads in message-passing parallel applications.

The benefits of stereoscopic vision in medical applications were appreciated and have been thoroughly studied for more than a century. The usage of the stereoscopic displays has a proven positive impact on performance in various medical tasks. At the same time the market of 3D-enabled technologies is blooming. New high resolution stereo cameras, TVs, projectors, monitors, and head mounted displays become available. This equipment, completed with a corresponding application program interface (API), could be relatively easy implemented in a system. Such complexes could open new possibilities for medical applications exploiting the stereoscopic depth. This work proposes a tool for production of interactive stereoscopic graphical user interfaces, which could represent a software layer for web-based medical systems facilitating the stereoscopic effect. Further the tool's operation mode and the results of the conducted subjective and objective performance tests will be exposed.

We present a new Placement and Routing (P&R) strategy for implementing digital Organic/Flexible/Printed Electronics (PE) circuits based on an Inkjet-configurable Gate Array (IGA) design style together with digital printing personalization.

We perform clustering over the Product Reactions Cards in order to group the terms in 8 groups and 41 subgroups. A card sorting exercise among software engineers and UX practitioners was performed in order to achieve this. We present a preliminary case study using this classification with a retailing application in order to see the difference in connotations that result introducing stereoscopic depth to the GUI.

This paper presents the development of a complete end-to-end solution for the broadcast of Multi-Stream Multi-view Real-Time Life Video Content that makes use of the new chips implementing full-spectrum receiver chips that can decode up to 16 TV channels simultaneously and pass them to the video processing chips of the Set-Top Boxes. Managing that complex video content from a user’s perspective requires adding interactive ways to increase user experience.Interactivity can either be directly managed on the main screen through the Set Top Box or on a Second Screen that is wireless connected to the Set Top Box. Several underlying technologies have been implemented that involve: the production head ends that include adding time stamps in the protocol for synchronizing streams and views; the GStreamer technology for scaling videos in real-time and the responsive design used for the 2nd screen apps management.

Learnability is a fundamental usability factor. It is included in several well known and widely used software usability evaluation models such as: IBM’s Computer Usability Satisfaction Questionnaire (CUSQ), System Usability Measurement Inventory (SUMI), System Usability Scale (SUS), and others. However, all of them assess learnability only subjectively. Taking into account the fact of presence of differences in perceived duration in interaction between human and computer, development of a new approach targeting usability, as well as learnability, in objective measures could be of great interest. This paper describes our endeavour in pursuing this task. We present our approach to the problem, introduce an instrument for calculating objective learnability out of times of completion, and reveal results of a user study among 101 participants conducted to test adequacy of the method.

Inkjet printing is a promising and challenging technique that could potentially revolutionize large area and organic electronics fabrication. Inkjet systems are designed to construct devices and circuits drop by drop, which would lead to a new paradigm in electronics fabrication. However, inkjet technology for Printed Electronics is still under development and several challenges remain. While there is significant progress being made in the development of electronic devices, such as transistors or sensors, there is a lack of work on circuit and system level design. Designing devices and circuits implies a wide knowledge of process aspects, requiring a complex interaction among concepts, tools and processes coming from different science and engineering disciplines. An explicit methodology is needed to separate design from fabrication in a similar way as in silicon design, to design devices and systems without a deep knowledge of process and materials; thus making it possible to open up inkjet technology to a larger community and undergo more rapid design implementations. In this paper we present the main aspects of such a methodology and we discuss the key topics on inkjet technology that allow us to propose these new specific steps.

Embedded multimedia devices are now a common element of our environment, such as mp3 players, handheld devices, and so on. Choosing the right main processing element is a key issue for the success of these devices, and their consumption, performance, retargetability, and development time are some of the elements that need to be analyzed and well-balanced. In this paper, we map the same multimedia application (MPEG-4 main profile) into various target platforms generally used in the embedded area. The design flow of our work starts with a single MPEG-4 encoder description which is later refined and optimized to be implemented on different platforms: an embedded platform formed by a high performance digital signal processor and an embedded processor, an application specific instruction processor, a specific hardware implemented in a field-programmable gate array for accelerating the data-flow part of the system with a soft-core for the control part, and an application specific integrated circuit. The main contribution of this paper is to illustrate a methodology that can be generalized to different data dominant applications. This paper describes a new methodology to obtain near optimal implementation from concept to silicon for all platforms and it can be extended to any hybrid HW/SW multimedia platform. We evaluate the different transformations of each platform to arrive at an optimal implementation. These higher level transformations allow achieving better results than using more precise efforts in mapping the design in the physical level. This methodology can be extended to any data dominant application.

Nowadays embedded systems are growing at an impressive rate and provide more and more sophisticated applications characterized by having a complex array index manipulation and a large number of data accesses. Those applications require high performance specific computation that general purpose processors can not deliver at a reasonable energy consumption. Very long instruction word architectures seem a good solution providing enough computational performance at low power with the required programmability to speed up the time to market. Those architectures rely on compiler effort to exploit the available instruction and data parallelism to keep the data path busy all the time. With the density of transistors doubling each 18 months, more and more sophisticated architectures with a high number of computational resources running in parallel are emerging. With this increasing parallel computation, the access to data is becoming the main bottleneck that limits the available parallelism. To alleviate this problem, in current embedded architectures, a special unit works in parallel with the main computing elements to ensure efficient feed and storage of the data: the address generator unit, which comes in many flavors. Future architectures will have to deal with enormous memory bandwidth in distributed memories and the development of address generators units will be crucial for effective next generation of embedded processors where global trade-offs between reaction-time, bandwidth, energy and area must be achieved. This paper provides a survey of methods and techniques that optimize the address generation process for embedded systems, explaining current research trends and needs for future.

While silicon based technologies are evolving towards very advanced nanometric nodes (≤ 20nm), the emerging thin-flexible-organic-large-area electronics (a.k.a. printed electronics, PE) based on flexible substrates and functional inks are starting again the history of microelectronics at technology and device levels trying to grow up to applications looking at the silicon path but far away from its costs and performances.

In this article, we present a drawing toolkit developed to create stereoscopic side-by-side 3D stimuli. The toolkit is based in the HTML5 canvas element and drawing is achieved using intermediate stereo scripting methods that correspond to the ‘2d’ context of the canvas. We include performance marks of the toolkit running on desktop and mobile browsers. Also, a discussion of how the tool is used for implementing a stereo 3D UI is specified.

Wearable electronics are gaining widespread use as enabling technologies, monitoring human physical activity and behavior as part of connected health infrastructures. Attention to human factors and comfort of these devices can greatly positively influence user experience, with a subsequently higher likelihood of user acceptance and lower levels of device rejection. Here, we employ a human factors and comfort assessment methodology grounded in the principles of human-centered design to influence and enhance the design of an instrumented insole. A use case was developed and interrogated by stakeholders, experts, and end users, capturing the context of use and user characteristics for the instrumented insole. This use case informed all stages of the design process through two full design cycles, leading to the development of an initial version 1 and a later version 2 prototype. Each version of the prototype was subjected to an expert human factors inspection and controlled comfort assessment using human volunteers. Structured feedback from the first cycle of testing was the driver of design changes implemented in the version 2 prototype. This prototype was found to have significantly improved human factors and comfort characteristics over the first version of the prototype. Expert inspection found that many of the original problems in the first prototype had been resolved in the second prototype. Furthermore, a comfort assessment of this prototype with a group of young healthy adults showed it to be indistinguishable from their normal footwear. This study demonstrates the power and effectiveness of human factors and comfort assessment methodologies in influencing and improving the design of wearable devices. This work was part funded by the EU FP7 project WIISEL (Wireless Insole for Independent and Safe Elderly Living). Project number FP7-ICT-2011-288878. peer-reviewed

Creating the layout of an application graphical user interface is an important part of any system development process. Mock-ups, usability studies, focus groups and sketching are techniques that help define this layout and ship the best UI for the required task. But with the addition of 3D depth into the GUI assortment, a gap is exposed when trying to draft the GUI due to the fact that depth cannot be easily represented using traditional 2D methods like paper or existing software. With this article we present a tool that allows designers and developers to draft graphical user interfaces that comply with stereoscopic side-by-side formats. The tool is created using the HTML5 canvas element, in conjunction with the browser’s console to live edit any sketch, and created layouts can be saved and shared in devices capable of showing compatible stereoscopic images.

This paper presents a global proposal and methodology for developing digital printed electronics (PE) prototypes, circuits and application specific printed electronics circuits (ASPECs). We start from a circuit specification using standard Hardware Description Languages (HDL) and executing its functional simulation. Then we perform logic synthesis that includes logic gate minimization by applying state-of-the-art algorithms embedded in our proposed electronic design automation (EDA) tools to minimize the number of transistors required to implement the circuit. Later technology mapping is applied, taking into account the available technology, (i.e., PMOS only technologies) and the cell design style (either Standard Cells or Inkjet Gate Array). These layout strategies are equivalent to those available in application specific integrated circuits (ASICs) flows but adapting them to Printed Electronics, which vary greatly depending on the targeted technology. Then Place & Route tools perform floorplan, placement and wiring of cells, which will be checked by the corresponding layout versus schematic (LVS). Afterwards we execute an electrical simulation including parasitic capacitances and relevant parameters. Finally, we obtain the prototypes which will be characterized and tested. The most important aspect of the proposed methodology is that it is portable to different PE processes, so that considerations and variations between different fabrication processes do not affect the validity of our approach. As final results, we present fabricated prototypes that are currently being characterized and tested.

Inkjet Technology is often mis-believed to be a deposition/patterning technology which is not meant for high fabrication throughput in the field of printed and flexible electronics. In this work, we report on the 1) printing, 2) fabrication yield and 3) characterization of exemplary simple devices e.g. capacitors, organic transistors etc. which are the basic building blocks for logical circuits. For this purpose, printing is performed first with a Proof of concept Inkjet printing system Dimatix Material Printer 2831 (DMP 2831) using 10 pL small print-heads and then with Dimatix Material Printer 3000 (DMP 3000) using 35 pL industrial print-heads (from Fujifilm Dimatix). Printing at DMP 3000 using industrial print-heads (in Sheet-to-sheet) paves the path towards industrialization which can be defined by printing in Roll-to-Roll format using industrial print-heads. This pavement can be termed as "Bridging Platform". This transfer to "Bridging Platform" from 10 pL small print-heads to 35 pL industrial print-heads help the inkjet-printed devices to evolve on the basis of functionality and also in form of up-scaled quantities. The high printed quantities and yield of inkjet-printed devices justify the deposition reliability and potential to print circuits. This reliability is very much desired when it comes to printing of circuits e.g. inverters, ring oscillator and any other planned complex logical circuits which require devices e.g. organic transistors which needs to get connected in different staged levels. Also, the up-scaled inkjet-printed devices are characterized and they reflect a domain under which they can work to their optimal status. This status is much wanted for predicting the real device functionality and integration of them into a planned circuit.

We report about the use of a printed pentafluorothiophenol layer on top of the dielectric surface as a passivation coating to improve the operational stability of all-ink-jet printed transistors. Transistors with bottom-gate structure were fabricated using cross-linked poly-4-vinylphenol (c-PVP) as dielectric layer and an ink formulation of an amorphous triarylamine polymer as semiconductor. The resulting TFTs had low turn-on voltage (Vth < |5 V|) and a mobility ≈0.1 cm2/(V s). A comparison of identically fabricated transistors shows that devices with coated dielectric have a higher operational stability than those using bare c-PVP. This conclusion is supported by a quantitative study of the threshold voltage shift with time under continuous operation. Long exposure to the ambient atmosphere causes an increase in the threshold voltage strongly dependent on the used semiconducting ink formulation. © 2015 Elsevier Ltd.

This paper presents the final results and future projection of the European projectWIISEL (Wireless Insole for Independent and Safe Elderly Living), that reached to build the first full-wirelessinsole (that include both wireless communication and wireless charging). These insoles provide a newset of non-invasive tools that can be used either at the clinical installations or at home. That solutionimproves the usability and user experience compared with traditional tools (smart carpets, wired insoles,etc.) that are oriented to clinical installations. And hence, provide a powerful tool for Ambient Intelligentfor Health, especially for elderly people, increasing their autonomy and providing means for long termmonitoring.

All inkjet printed rectifying diodes based on a metal-insulator-semiconductor (MIS) layer stack are presented. The rectifying properties were optimized by careful selection of the insulator interlayer thickness and the layout structure. The different diode architectures based on the following materials are investigated: (1) silver/ poly (methylmethacrylate-methacrylic acid)/ polytriarylamine/ silver, (2) silver/ polytriarylamine/ poly (methylmethacrylate-methacrylic acid)/ silver, and (3) silver/ poly (methylmethacrylate-methacrylic acid)/ poly-triarylamine/ poly(3,4-ethylenedioxythiophene) poly (styrenesulfonate). The MIS diodes show an averaged rectification ratio of 200 and reasonable forward current density reaching 40 mA cm -2. They are suitable for a number of applications in flexible printed organic electronics. EU [287682]

This paper presents a top-down approach for the design process of digital Application Specific Printed Electronics (PE) Circuits (ASPECs); from functionality specification at circuit level (i.e. HDL), through the optimization of combinational circuitry (represented by their logical equations), according to the PMOS-based technology that will be used to build a set of Standard Cells (SC) or use a predesign Inkjet Gate Array (IGA), down to the Place and Route to get the final circuit layout. This process will use the technology coming from the Centre for Process Innovation (CPI). This methodology maps the existing ASIC one by updating design styles and cost functions. Thus, it is portable to different Printed Electronics processes, using state-of-the-art logic synthesis EDA/software tools being the main optimization goal the transistor count. Main reason is that printed electronics technologies show low density and not such high yield compared to traditional Silicon-based microelectronics. To illustrate this methodology, we use the design and implementation of the TicTacToe game to be implemented together with flexible textile pressure sensor and lighting.

Application Specific Printed Electronics Circuit (ASPEC), a circuit designed and customized for a special application rather than intended for general-purpose use, is the equivalent term for ASIC but for printed electronics. In this paper, we extend the printed electronics to ASPEC design by developing a standard cell library for CPI (center for Process Innovation) technology which substrate is flexible PEN(50 micron thickness), laminated to glass using the PDMS bounding process. Standard cells topology allows full automation of the layout design process using automated place and route tools. In addition, Standard cells significantly help speeding the circuit development time as the blocks can be synthesized from high level descriptions (Verflog, VHDL) using the library. The cell library is generated for two different types of Top-gate bottom contact Organic Thin Film Transistors (OTFTs): l)Inter-digitated OTFT, 2)Corbino OTFT. The pseudo ratioed pMOS lodic is used for the circuitry since only p-channel transistors are available. The developed library consists of 7 gates: 5 combinational gates (Inverter, NAND2, NAND3, NAND4, and XOR2) and 2 sequential gates (D flip flop and enable D flip flop) and a FEED cell. Glade layout editor and MaskEngineer 4.8.4 and AIMSpice simulator have been used to design the cells layout and simulate the cell circuits. Automatic extraction of electrical interconnections from layout has been done in order to enable layout versus schematic (LVS). Finally, Tic-Tac-Toe game using combinational circuit has been designed, fabricated and will be characterized to demonstrate the standard cell library.

This paper presents an investigation about the ideal composition of cell libraries to be used for digital Application Specific Printed Electronics Circuits (ASPECs). Printed/organic/flexible electronics is becoming more and more important over the last years, and it seems that the industry will continue growing as new possible applications arise, and the existing ones are being improved due to better designs and fabrication processes, even moving towards integrating logic circuitry together with sensors and actuators. This paper presents considerations for developing (ASPECs), trying to keep a similar approach to the typical ASIC procedures. The work presented herein adopted a cell-based design methodology addressed to printed electronics (PE) designs. Such methodology allows us to propose a design flow for PE similar to the VLSI design flow, comprising logic synthesis, mapping, placement, and routing. In order to evaluate different library compositions, a set of benchmark has been mapped with six different combinations of mapping tools and associated libraries. The obtained results show that a simple library composed of just three cells - either NAND2, NOR2 and inverters or NAND, NAND3 and inverters - performs very well in terms of transistor count. NAND gates are usually preferred options for ratioed PMOS-only design styles. Using a more complex cell library can produce reductions of around 25% in terms of transistor count, but produce increases of around 23% as well.

The fabrication of pH-sensitive ISFET devices in an unmodified two-metal commercial CMOS technology (1.0 um from Atmel-ES2) is reported. The ISFET devices have a gate structure compatible with the CMOS process, with an electrically floating electrode consisting on polysilicon plus the two metals. The passivation oxynitride layer acts as the pH-sensitive material in contact with the liquid solution. The devices have shown good operating characteristics, with a 47 mV/pH response. The use of a commercial CMOS process allows the straightforward integration of signal-processing circuitry. An ISFET amplifier circuit has been integrated with the ISFET sensors.

Pressure sensors and aceelerometer structures have been fabricated in a commercial CMOS foundry technology (1.0 µm from Atmel-ES2) using a post-processing for back-side wafer micromachining. The overall technology (CMOS plus post-processing) can be used for integrated sensor system design through a specific design kit in the standard foundry design environment. Fabrication is then performed so that postprocessing is transparent to the user.

Inkjet printed electronics using thermo-curable liquid inks exhibit particular geometrical characteristics in terms of regularity. This article presents a morphological analysis for inkjet printed multi line intersections that are critical structures for building circuits. We studied thin-film structures of silver conductive ink and printed by inkjet technology. Instability of the ink during printing causes the thickness irregularity of vertex, normally with peaks at these areas. We propose the usage of specific patterns for intersections as thickness regularity compensations. The results show that some patterns help to reduce this instability and improve the thickness regularity of intersections morphology.

This paper reports on usage of Greek cross test structure to characterize geometry of inkjet printed electronics circuits. Geometric characteristics extracted from optical characterization can be correlated with electric measurements for square resistance in order to speed up the characterization processes. Design of inkjet printed Greek cross test structure should consider the ink coalescence and coffee ring effects.

In this paper we present 3DSjQ, a tool used to implement stereoscopic 3D in web pages. It provides HTML developers the possibility to create static and dynamic content that interacts with depth. We uncover the algorithm used for the tool, describe the method of operation and discuss future work including further development and implementations.

With this paper we document an experiment that is defined to test to what extent stereoscopic depth may control a user’s gaze pattern while performing a search task. The experiment consisted in displaying a search engine result page created in a 2D and 3D side by side format, and a questionnaire that gathers information about participants’ opinion towards a stereoscopic 3D experience. While this experiment is a first pilot and more research is needed, it is indicative of user behavior. In this paper we describe preparations for the study, hardware and software tools used to carry out the experiment, and results analysis.

This paper presents the design of a multi-processor system to control a Laser Marking machine. The use of multiple soft-core processors allows to independently control multiple heads that share a single laser beam. We show that with several design decisions we can increase the laser beam utilization factor up to 92%. Besides, we present a multi-soft-core architecture, a particular programming model, and how the system is extended to enable performance analysis.

The emergence of wearable intelligent textile systems with sensors and actuators nodes are integrated into user clothes. Emergency units can benefit from new technologies to improve their performance and security conditions when working exposed to risk situations. In firefighters case is a the system Bluetooth Low Energy (BLE) at 2.4GHz with a watch to show the thermal stress and, in case of exceed healthy level will trigger an alarm to warn the user. In this scenario the design and study of the working conditions of an antenna is a crucial issue for ensuring the communication capabilities of the the whole system. In this work paper we present the design, development and test of a miniature flexible antenna prepared to integrate in the uniforms maintaining the radiation properties although bend or warming. We will see how to minimize the size of the antenna with a antenna PIFA on a Polyethylene Terephtalate (PET) substrate.

CONTENT EXTRACTION Local Spatiotemporal Features for Robust Content-Based Video Copy Detection Geert Willems, Tinne Tuytelaars, and Luc Van Gool Cross-Domain Learning for Semantic Concept Detection Wei Jiang, Alexander Loui, And Shih-Fu Chang TV Content Analysis and Annotation for Parental Control Thanassis Perperis and Sofia Tsekeridou Robust, Hardware-Oriented Overlaid Graphics Detection for TV Applications Ahmet Ekin Commercial and Trademark Recognition Lamberto Ballan, Marco Bertini, Alberto Del Bimbo, Walter Nunziati, and Giuseppe Serra CONTENT STRUCTURING TV Program Structuring Techniques Alina Elma Abduraman, Sid Ahmed Berrani, and Bernard Merialdo About TV StreamMacro-Segmentation Zein Al Abidin Ibrahim and Patrick Gros Large-Scale Analysis for Interactive Media Consumption David Gibbon, Andrea Basso, Lee Begeja, Zhu Liu, Bernard Renger, Behzad Shahraray, and Eric Zavesky 9 High-Level TV Talk Show Structuring Centered on Speakers' Interventions Felicien Vallet, Slim Essid, Jean Carrive, and Gael Richard CONTENT RECOMMENDATION Recommender Systems for Interactive TV Riccardo Bambini, Paolo Cremonesi, and Roberto Turrin Capturing Long-Term User Interests in Online Television News Programs Frank Hopfgartner Personalized Content Access in Interactive TV-Based Cross Media Environments Alcina Prata, Teresa Chambel, and Nuno Guimaraes CONTENT QUALITY Algorithmic Evaluation of Visual Appeal Anush Krishna Moorthy and Alan Conrad Bovik Mobile TV Content Design Rules Shelley Buchinger, Julia Wippersberg, Klaus Lojka, Karin Macher, Werner Robitza, Matej Nezveda, Patrik Hummelbrunner, and Helmut Hlavacs WEB AND SOCIAL TV Hierarchical Semantic Content Analysis and Its Applications in Multimedia Summarization and Browsing Junyong You, Andrew Perkis, Moncef Gabbouj, and Touradj Ebrahimi Elaborating the Convergence of TV and Web (2.0) Content Sabine Bachmayer and Pauliina Tuomi Enhancing Social TV through Social Media Mining Ovidiu Dan, Junlan Feng, and Bernard Renger CONTENT PRODUCTION A Survey of Advanced Content Management Tools for TV Postproduction Werner Bailer, Klaus Schoeffmann, and Frank Hopfgartner Enriching the Viewing Experience of TV Programs Using Virtual Content Insertion Yu-Tzu Lin, Chia-Hu Chang, and Ja-Ling Wu Analysis of the TV Interactive Content Convergence and Cross-Platform Adaptation Aitor Rodriguez-Alsina and Jordi Carrabina Glossary Index

Ambient Intelligence is a new paradigm in which environments are sensitive and responsive to the presence of people. This is having an increasing importance in multimedia applications, which frequently rely on sensors to provide useful information to the user. In this context, multimedia applications must adapt and personalize both content and interfaces in order to reach acceptable levels of context-specific quality of service for the user, and enable the content to be available anywhere and at any time. The next step is to make content available to everybody in order to overcome the existing access barriers to content for users with specific needs, or else to adapt to different platforms, hence making content fully usable and accessible. Appropriate access to video content, for instance, is not always possible due to the technical limitations of traditional video packaging, transmission and presentation. This restricts the flexibility of subtitles and audio-descriptions to be adapted to different devices, contexts and users. New Web standards built around HTML5 enable more featured applications with better adaptation and personalization facilities, and thus would seem more suitable for accessible AmI environments. This work presents a video subtitling system that enables the customization, adaptation and synchronization of subtitles across different devices and multiple screens. The benefits of HTML5 applications for building the solution are analyzed along with their current platform support. Moreover, examples of the use of the application in three different cases are presented. Finally, the user experience of the solution is evaluated.

Altres ajuts: MINETUR/TSI-020400-2010-82 Altres ajuts: MINETUR/TSI-020100-2010-1036 Multi-soft-core systems are a viable and interesting solution for embedded systems that need a particular tradeoff between performance, flexibility and development speed. As the growing capacity allows it, many-soft-cores are also expected to have relevance to future embedded systems. As a consequence, parallel programming methods and tools will be necessarily embraced as a part of the full system development process. Performance analysis is an important part of the development process for parallel applications. It is usually mandatory when you want to get a desired performance or to verify that the system is meeting some real-time constraints. One of the usual techniques used by the HPC community is the postmortem analysis of application traces. However, this is not easily transported to the embedded systems based on FPGA due to the resource limitations of the platforms. We propose several techniques and some hardware architectural support to be able to generate traces on multiprocessor systems based on FPGAs and use them to optimize the performance of the running applications.