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Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

Piezoelectric energy harvesters (PEHs) are widely deployed in many self-sustaining systems, and proper rectifier circuits can significantly improve the energy conversion efficiency and, thus, increase the harvested energy. Various active rectifiers have been proposed in the past decade, such as synchronized switch harvesting on inductor (SSHI) and synchronous electric charge extraction (SECE). This article presents a sense-and-set (SaS) rectifier that achieves maximum-power-point-tracking (MPPT) of PEHs and maintains optimal energy extraction for different input excitation levels and output voltages. The proposed circuit is fabricated in the 0.18- $\mu \text{m}$ CMOS process with a 0.47-mm2 core area, a 230-nW active power, and a 7-nW leakage power. Measured with a commercial PEH device (Mide PPA-1022) at 85- and 60-Hz vibration frequency, the proposed circuit shows 512% and 541% power extraction improvement [figure of merit (FoM)] compared with an ideal full-bridge rectifier (FBR) for ON-resonance and OFF-resonance vibrations, respectively, while maintaining high efficiency across different input levels and PEH parameters.

Arrays of floating neural sensors with high channel count that cover an area of square centimeters and larger would be transformative for neural engineering and brain-machine interfaces. Meeting the power and wireless data communications requirements within the size constraints for each neural sensor has been elusive due to the need to incorporate sensing, computing, communications, and power functionality in a package of approximately 100 micrometers on a side. In this work, we demonstrate a near infrared optical power and data communication link for a neural recording system that satisfies size requirements to achieve dense arrays and power requirements to prevent tissue heating. The optical link is demonstrated using an integrated optoelectronic device consisting of a tandem photovoltaic cell and microscale light emitting diode. End-to-end functionality of a wireless neural link within system constraints is demonstrated using a pre-recorded neural signal between a self-powered CMOS integrated circuit and single photon avalanche photodiode.

A key challenge for near-infrared (NIR) powered neural recording ICs is to maintain robust operation in the presence of parasitic short circuit current from junction diodes when exposed to light. This is especially so when intentional currents are kept small to reduce power consumption. We present a neural recording IC that is tolerant up to 300 μW/mm(2) light exposure (above tissue limit) and consumes 0.57 μW at 38°C, making it lowest power among standalone motes while incorporating on-chip feature extraction and individual gain control.

1T1MTJ spin-transfer-torque (STT)-MRAM is a promising candidate for next-generation high-density embedded non-volatile memory. This paper presents a 1-Mb 28-nm 1T1MTJ STT-MRAM with improved sensing margin and reduced power consumption. An offset-cancelled sense amplifier is proposed, using only a single capacitor, to improve sensing margin and accelerate read speed. To save write power, an in situ write-self-termination method is proposed where the sense amplifier is reconfigured without area overhead to continuously monitor the write operation and shutoff the write drivers as soon as the magnetic transition occurs in the bitcell. A prototype chip achieves 2.8- and 3.6-ns read access time at 25 °C and 120 °C, respectively. The in situ write-self-termination scheme reduces write power by 47% and 60% with 20-ns write access time at 25 °C and 120 °C, respectively.

Dual-junction GaAs photovoltaic (PV) cells and modules at sub millimeter scale are demonstrated for efficient wireless power transfer for Internet of Things (IoT) and bio-implantable applications under low-flux illumination. The dual-junction approach meets demanding requirements for these applications by increasing the output voltage per cell with reduced area losses from isolation and interconnects. A single PV cell (150 μm × 150 μm) based on the dual-junction design demonstrates power conversion efficiency above 22% with greater than 1.2 V output voltage under low-flux 850 nm near-infrared LED illumination at 6.62 μW/mm(2), which is sufficient for batteryless operation of miniaturized CMOS IC chips. The output voltage of dual-junction PV modules with 4 series-connected cells demonstrates greater than 5 V for direct battery charging while maintaining a module power conversion efficiency of more than 23%.

Brain machine interfaces using neural recording systems [1]–[4] can enable motor prediction [5]–[6] for accurate arm and hand control in paralyzed or severely injured individuals. However, implantable systems have historically used wires for data communication and power, increasing risks of tissue damage, infection, and cerebrospinal fluid leakage, rendering these devices unsuitable for long-term implantation (Fig. 26.9.1, top). Recently, several wireless and miniaturized neural recording implants with various power and data transmission methods were proposed. References [7], [8] propose an electrocorticography (ECoG) recording system with near-field RF power transfer and bilateral communication, but the 0.5W Tx exceeds maximum exposure limits by 10x [8]. Ultrasonic telemetry can safely send more power than RF; however it requires mm-scale dimensions (0.8mm3 in [9]) due to bulky ultrasound transducers. On the other hand, near infrared (NIR) light can provide power transfer and data downlink via a photovoltaic cell (PV), and a data uplink via a light-emitting diode (LED). Dimensions can be scaled to 100s of microns [10], with [11] demonstrating a 0.0297mm2 neural recording system using a 50mW/mm2 light source $( of safety limit for the brain). However, this system is limited to a single channel, and since it only has a surface electrode, it can record only surface potentials (face-down, potentially blocking the light channel) or must itself be injected into brain tissue, creating significant tissue damage and danger of bleeding. In this paper, we propose $0.74\mu \mathrm{W}, 0.19\times 0.17\mathrm{mm}^{2}1\mathrm{C}$ designed for a wireless neural recording probe. It computes so-called spiking band power (SBP) [5], [12] on-chip to save 920x power while maintaining accurate finger position and velocity decoding.

Wireless sensors for IoT applications have become a prominent computing class and are typically severely power constrained. IoT devices are deployed in a wide range of environments and low power consumption must be guaranteed across a wide temperature range. The combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB) can achieve minimum total energy per cycle, where dynamic and leakage energy are at an optimal trade-off point [1]. However, due to the dependence of leakage on temperature and workload fluctuations over time, this optimal operating point requires runtime adjustment. Traditional approaches to track an optimal operating point involve repeated measurement of processor power inside a body-bias and supply voltage search loop. However, determining processor power consumption adds significant complexity and/or power overhead since it requires separate measurement of supply voltage and current followed by their multiplication.

Acoustic sensing is one of the most widely used sensing modalities to intelligently assess the environment. In particular, ultra-low power (ULP) always-on voice activity detection (VAD) is gaining attention as an enabling technology for IoT platforms. In many practical applications, acoustic events-of-interest occur infrequently. Therefore, the system power consumption is typically dominated by the always-on acoustic wakeup detector, while the remainder of the system is power-gated the vast majority of the time. A previous acoustic wakeup detector [1] consumed just 12nW but could not process voice signals (up to 4kHz bandwidth) or handle non-stationary events, which are essential qualities for a VAD. Prior VAD ICs [2], [3] demonstrated reliable performance but consumed significant power $(\gt 20 \mu \mathrm {W})$ and lacked an analog frontend (AFE), which further increases power. Recent analog-domain feature extraction-based VADs [4], [5] also reported $\mu \mathrm {W}-$ level power consumption, and their simple decision tree [4] or fixed neural network-based approach [5] limited broader use for various acoustic event targets. In summary, no sub $-\mu \mathrm {W}$ VAD has been reported to date, preventing the use of VADs in unobtrusive mm-scale sensor nodes.

A key challenge in the design of on-chip wake-up timers for compact wireless sensor nodes is to achieve high timing accuracy over temperature and supply voltage variation within an ultra-low power budget. We propose a gate-leakage-based frequency-locked timer with first- and second-order cancellation achieving 260 ppm/°C from −5 to 95°C. The timer consumes 224 pW at 90 Hz output frequency with 0.93%/V supply voltage dependence in the 1.1-3.3 V range.

1T1R spin-transfer-torque (STT) MRAM is a promising candidate for next-generation high-density embedded non-volatile memory [1-2]. However, 1T1R STT-MRAM suffers from limited sensing margin and high write power. As shown in Fig. 30.2.1(a), sense amplifier design is challenging due to the small difference (only 2x) between the high-resistance state (R AP ) and the low-resistance state (R P ), as well as R AP degradation with increasing temperature. Moreover, R P and R AP resistance distributions shift with process variation, requiring a read reference (V ref ) that tracks process. To improve the sensing margin, several offset-cancellation methods have been reported to reduce sense amplifier mismatch [3]. However, these methods use multiple capacitors and hence incur significant area overheads. To address this issue, we propose an offset-cancelled sense amplifier that uses only a single capacitor to significantly improve the sensing margin by more than 60%. A second design challenge for STT-MRAM stems from the high current needed to flip a cell during a write operation. For non-volatile memory applications with a 10-year retention time requirement, the write current can be as high as several hundred μA. However, as shown in Fig. 30.2.1(b), the required write time varies with the state change required (0→1 or 1→0), process variation, and temperature. As a result, a fixed write time that ensures successful write for all conditions wastes a significant energy for typical or average conditions. We propose an in situ write-self-termination method to reduce write energy in most scenarios. The sense amplifier is reconfigured to continuously monitor the write operation and automatically shuts off the write drivers when the state transition is detected, without an area or timing penalty. In addition, dual dummy columns are added in each array to provide read V ref tracking of row-wise PVT variation. A 1Mb STT-MRAM was fabricated in 28nm technology, and achieves a 2.8ns read-access time at 25°C and 3.6ns at 120°C, respectively. With in-situ self-write-termination the write power is reduced by 47% with a 20ns write-access time at 25°C and by 60% at 120°C.

This article introduces a 32-kHz crystal oscillator (XO) with high energy-to-noise-ratio pulse injection at subharmonic frequency. A T/4-delay clock slicer is proposed to convert the sinusoidal crystal waveform into an output clock of 32 kHz and to introduce a delay of T/4, providing proper timing for energy injections. The output clock feeds frequency dividers and generates pulses to activate the proposed all-NMOS differential driver at 4 kHz. It enables two injections in eight periods at the peak and valley of the crystal oscillation, with the crystal running freely between injections. This configuration achieves a 2-ppb Allan deviation floor. The less frequent injections reduce the injection overhead, enabling the lowest reported power consumption of published nW XOs (0.51 nW). At 0.45 V, the proposed XO operates across a temperature range of −25∘C to 125 °C, the widest reported range for nW XOs. This design is fabricated in the 40-nm CMOS and occupies 0.02 mm 2 .