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To attribute authorship (author identification) means to identify the true author of a sample of work among many candidates. Author identification is an important research field in natural language. Machine learning approaches are widely used in natural language analysis, and previous research has shown that similar techniques can be applied in the analysis of computer programming (artificial) languages. This paper focuses on the use of machine learning techniques in the identification of authors of computer programs. We focus on identifying which features capture the writing style of authors in the classification of a computer program according to the author's identity. We then propose a novel approach for computer program author identification. In this method, features from source code of the programs are combined with authors' sociological features (gender and region) to develop the classification model. Several experiments were conducted on two datasets composed of computer programs written in C++. Our models are able to predict an author's identity with a 75% accuracy rate.

Ternary reversible logic functions are generally represented as ternary Galois field sum of products (TGFSOP) expressions and the TGFSOP expressions are mapped to reversible circuits using cascades of Feynman and Toffoli gates. Although a ternary logic function with a large number of variables can be minimized as a TGFSOP expression, the process is computationally expensive and the resulting reversible circuit tends to have a high quantum cost and ancilla in puts. To overcome these limitations, in this work we propose a new method of representing ternary reversible logic functions as Max of Min-terms (Max-Min) expressions, which can be mapped to a reversible circuit using multiple-controlled unary gates requiring lower quantum cost and fewer ancilla inputs. We propose a map-based minimization method for Max-Min expressions of up to four variables focusing on restrictions of the reversible circuit mapping technique.

An overview of the diagnostics installed on the Alcator C-Mod tokamak is presented. Approximately 25 diagnostic systems are being operated on C-Mod. The compact design of the machine and the cryostat enclosing the vacuum vessel and magnetic field coils make access challenging. Diagnostics are used to study four focus areas: transport, plasma boundary, waves, and macrostability. There is significant overlap between these topics, and they all contribute toward the burning plasma and advanced tokamak thrusts. Several advanced and novel diagnostics contribute to the investigation of C-Mod plasmas, e.g., electron cyclotron emission, phase-contrast imaging, gas puff imaging, probe measurements, and active magnetohydrodynamic antennas.

This paper focuses on the use of machine learning techniques for the analysis of computer programs in order to acquire information about an author's gender. There are few existing studies that address the relationship between linguistics and programming; however, in many areas where language is analyzed it is possible to mine important information about the users of that language associated with set of attribute or coding style. In this work we use open source implementations of machine learning algorithms, specifically, nearest neighbor (K*), decision tree (J48), and Bayes classifier (Naive Bayes). These algorithms were applied to C++ programs which were associated with sociolinguistic information about the program authors. Our goal was to classify the programs according to the gender of the author. As indicated by our initial results we have been able to achieve precision of 72.3%, recall of 72%, and f-measure of 71.9% which demonstrates that we can predict the gender of the authors of C++ programs.

In this paper we propose an approach for the design of online testable reversible circuits. A reversible circuit composed of Toffoli gates can be made online testable by adding two sets of CNOT gates and a single parity line. The performance of the proposed approach for detecting a single bit fault, a cross point fault and the family of missing gate faults has been observed. Discussion around the correctness of our approach and the overhead is also provided.

Previous work presented a simple technique for converting an ESOP-based Boolean reversible circuit into an online testable circuit. This paper builds on the previous work by extending its application to circuits consisting of cascades of ternary Toffoli gates. The technique is applied to an existing cascade of ternary Toffoli gates, and requires that a single additional line be added to facilitate the propagation of any faults that are identified, as well as modification and/or addition of some gates. The modified circuit can detect online any single-bit errors that occur within the circuit. Experimental results compare very favourably to the only other known approach.

Mobile technology has already had a major impact on the financial industry. With the growing acceptance of mobile transactions, security issues require more attention. The proposed secured architecture for 2-party mobile payments (SA2pMP) was designed to satisfy the four properties of confidentiality, authentication, integrity and non-repudiation that are demanded by any secure system. As an extension following [1] and [2], a PC-based simulation is conducted to evaluate the feasibility of the proposed architecture. This paper introduces the computer based simulation and the feasibility evaluation process. In terms of criteria based on the time delay and the code size, SA2pMP is demonstrated feasible for implementation in Java ME enabled CLDC-1.1 mobile devices.

The evolution of wireless networks and mobile devices has resulted in increased concerns about performance and security of mobile payment systems. In this paper we propose a new secured architecture for two-party mobile payments, e.g. mobile banking. The proposed architecture employs a lightweight cryptography system that combines public key and symmetric key cryptography systems (ECDSA and AES), as well as a multi-factor authentication mechanism. These are coupled with a transaction log strategy to satisfy the properties of confidentiality, authentication, integrity and non-repudiation. Compared to some existing mobile payment platforms the proposed architecture is a lightweight secured mechanism that is more suitable for two-party banking transactions over resource-limited mobile devices.

The evolution of wireless networks and mobile devices has resulted in increased concerns about performance and security of mobile payment systems. In this paper we propose SA2pMP, a lightweight secured architecture for two-party mobile payments. SA2pMP employs a lightweightcryptography scheme that combines public key and symmetric key cryptography systems (ECDSA and AES), as well as a multi-factor authentication mechanism. These are coupled with a transaction log strategy to satisfy the properties of confidentiality, authentication, integrity and nonrepudiation. We simulate SA2pMP in a context of money transfer banking transaction, on three different emulators:Sun Java Wireless Toolkit 2.5.2 for CLDC emulator, Sony Ericsson SDK 2.5.0.3 Z800 emulator, and Nokia S60 3rd Edition emulator. We also compare SA2pMP to some existing mobile payment platforms. The result of simulation and comparison proves that SA2pMP is a lightweight secured mechanism that is feasible and suitable for two-party mobile payment transactions, e.g. mobile banking, over Java ME enabled, resource-limited mobile devices.

Recent work has begun to investigate the advantages of using reversible logic for the design of circuits. The majority of work, however, has limited itself to combinational logic. Researchers are just now beginning to suggest possibilities for sequential implementations. This paper performs a closer analysis of three latch designs proposed in previous work and suggests advantages and disadvantages of each

An implementation of an algorithm for string matching, commonly used in DNA string analysis, using configurable technology is proposed. The design of the circuit allows for pipelining to provide a performance increase. The proposal is unique in that we suggest a design that is specific to certain parameters of the problem, but may be reused for any particular instance of the problem that matches these parameters. The use of a field programmable gate array allows the implementation to be instance specific, thus ensuring maximal usage of the hardware. Analysis and preliminary results based on a prototype implementation are presented.

Four operations on switching functions are used to define a classification technique based on the autocorrelation function. The relationship between these classes and the well-known spectral classes is investigated, and a canonical representative for each class is proposed. It is thought that these classes will be of use in logic synthesis employing decision diagram representations for intermediate steps.

The Microgravity Acceleration Measurement System (MAMS) is a high resolution and wide dynamic range dual sensor-based accelerometry instrumentation system to be installed within the International Space Station's (ISS) US Laboratory Module. The MAMS instrument will provide highly accurate acceleration measurement data over the nano-g to milli-g range characterizing the Lab Module environment in the frequency spectrum from 10/sup -4/ Hz to 100 Hz. MAMS covers the quasi-steady acceleration frequency range by utilizing the Orbital Acceleration Measurement Experiment (OARE) and the vibratory microgravity disturbance range by using the High Resolution Accelerometer Package (HIRAP). These instruments are being repackaged to fit into an EXPRESS Double Mid-Deck Locker with appropriate command and data interfaces to the ISS. This paper will describe the MAMS and its performance verification.

Reconfigurable hardware has recently shown itself to be an appropriate solution to speeding up problems that are highly dependent on a particular complex or repetitive sub-algorithm. In most cases, these types of solutions lend themselves well to parallel solutions. The optimal design on field programmable gate arrays (FPGAs) for problems with algorithms or sub-algorithms that can be highly parallelised is investigated. In addition, a classification system is introduced, which categorises FPGA-based solutions into 'instance-specific' and 'parameter-specific'.