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Patients with Sjögren syndrome (SS) experience difficulties in wearing conventional dentures. After removal of all teeth, the oral rehabilitation is challenging and time consuming using conventional treatment protocols. Although implant-retained overdentures are beneficial for this specific patient group, the average total oral rehabilitation time (TORT) usually takes at least 9 months and needs to be reduced to increase patients' quality of life (QoL). In this paper, we report on a new treatment concept for immediate implant-based oral rehabilitation in a 77-year-old patient with partial edentulous SS. Because of persistent pain, discomfort, and retention problems with the conventional prosthetic devices, full clearance of the remaining mandibular dentition and immediate oral rehabilitation with an implant-retained overdenture were suggested. The treatment protocol included virtual surgical planning (VSP), combining a guided bone reduction of the mandibular alveolar process, immediate dental implant placement, and restoration using a prefabricated bar and placement of the overdenture. This method demands the use of ionizing 3D imaging optionally combined with an optical dental scan or a conventional impression. Furthermore, one needs to gain experience using VSP software. This novel treatment concept for immediate implant-based oral rehabilitation using VSP proved to be feasible and safe in a patient with SS, resulting in a significantly reduced TORT and improved QoL. Further research is needed to what extent this treatment concept could be beneficial to other patient groups, such as patients with head and neck cancer.

We demonstrate a novel process for building a Resistive RAM (ReRAM) stack which reduces the forming voltage ( $\text{V}_{\textit {form}}$ ) and increases the switching resistance, both characteristics that are important ingredients for the use of ReRAM in scalable analog compute for AI. Utilizing this process, we explore analog switching characteristics above 100k $\Omega $ and demonstrate 4-bit programming at Rmax $=1\text{M}\Omega $ . Utilizing the same writing characteristics, CIFAR-10 inference simulation shows 90% accuracy, comparable to the full precision model accuracy.

Recently, multilevel Resistive RAM (ReRAM) stacks have been demonstrated to have promising applications related to inference and learning in artificial intelligence. However, extensive studies on energy efficiency, repeatability, and retention during multilevel operations have not been undertaken previously. It is, therefore, required to investigate the device characteristics such as compliance current (CC) dependence, forming voltage, memory window, symmetry, and switching energy. Furthermore, understanding the impact of dielectric composition and/or electrode materials is necessary to optimize the device performance, such as switching characteristics, endurance, and energy efficiency. In this work, we have investigated a two-terminal ReRAM device, 10nm Ti/50nm TiN/7nm HfO2/1nm Al2O3/PVD Ti/TiN (Fig. 1), with bilayer switching dielectrics of HfO2 and Al2O3. In this case, the embedded Al2O3 layer was placed between the HfO2 layer and the top electrode (TE). We have evaluated the gradual resistance change capability with varying CC. The I-V characteristics of the ReRAM device, measured by a dc double sweep, is shown in Fig. 2. The device switched at a compliance current of 50nA with a forming voltage of 1.85 volts to set to low resistance state (LRS) from the high resistance state (HRS). The subsequent reset from LRS to HRS was obtained during the negative voltage ramp showing a bipolar switching operation (Fig. 2). With the variation of compliance current (50 nA to 70 nA), the LRS was gradually changed indicating multilevel LRS. It is known that by increasing the compliance current with a gradual set process, multiple conducting filaments (CFs) or thicker CFs can form setting the different LRS values and the annihilation of the CFs during the reset process can also moderately vary the HRS values. The resistance ratio between the HRS and LRS was observed to be more than 1000. The devices were subjected to 100 cycles of SET and RESET operations at different CCs without any failures. When the embedded Al2O3 layer was placed between the bottom electrode (BE) and the HfO2 layer, the switching compliance current was increased to 10 mA with a reduced forming voltage of 1.6V. Multilevel LRS states were observed for this device when the CC was varied from 10 mA to 12 mA for 100 cycles at each CCs. To further understand the behavior, TEM depth profile measurements were carried out, and it was observed that Al2O3 diffused from the peak at the as-deposited location into the HfO2 layer in both cases. While this improved the uniformity in switching behavior, the low switching energy consumption in the case of an embedded Al2O3 layer in between the HfO2 layer and the TE layer remains to be investigated. Replacing the PVD Ti layer (Fig. 1) with ALD Ti in the TE when an Al2O3 layer was between the bottom electrode (BE) and the HfO2 layer reduced the switching compliance current from 10 mA to 100 nA. This suggests that the metal quality of the TE can impact the switching behavior of the multilevel ReRAMs. Figure 1

Supplemental Digital Content is available in the text., IMPORTANCE: A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 is hypothesized to play a role in the pathogenesis of invasive infection, but studies in sepsis are lacking. OBJECTIVES: To study A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 protein level in pediatric sepsis and to study the association with outcome. DESIGN: Data from two prospective cohort studies. SETTING AND PARTICIPANTS: Cohort 1 is from a single-center study involving children admitted to PICU with meningococcal sepsis (samples obtained at three time points). Cohort 2 includes patients from a multicenter study involving children admitted to the hospital with invasive bacterial infections of differing etiologies (samples obtained within 48 hr after hospital admission). MAIN OUTCOMES AND MEASURES: Primary outcome measure was mortality. Secondary outcome measures were PICU-free days at day 28 and hospital length of stay. RESULTS: In cohort 1 (n = 59), nonsurvivors more frequently had A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 levels above the detection limit than survivors at admission to PICU (8/11 [73%] and 6/23 [26%], respectively; p = 0.02) and at t = 24 hours (2/3 [67%] and 3/37 [8%], respectively; p = 0.04). In cohort 2 (n = 240), A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 levels in patients within 48 hours after hospital admission were more frequently above the detection limit than in healthy controls (110/240 [46%] and 14/64 [22%], respectively; p = 0.001). Nonsurvivors more often had detectable A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 levels than survivors (16/21 [76%] and 94/219 [43%], respectively; p = 0.003), which was mostly attributable to patients with Neisseria meningitidis. CONCLUSIONS AND RELEVANCE: In children with bacterial infection, detection of A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 within 48 hours after hospital admission is associated with death, particularly in meningococcal sepsis. Future studies should confirm the prognostic value of A Disintegrin and Metalloproteinase with Thrombospondin Motifs-1 and should study pathophysiologic mechanisms.

Copyright © 2020 The Author(s). Published by Wolters Kluwer Health, Inc.PURPOSE OF REVIEW: Oral rehabilitation with dental implants in head and neck cancer (HNC) patients is challenging. After tooth removal prior to radiotherapy, immediate placement of dental implants during panendoscopy or surgery is thought to reduce the oral rehabilitation time improving patients' quality of life. RECENT FINDINGS: There is lack of consensus on the timing of dental implant placement and loading protocols. The aim of this study was to perform a systematic review of the literature regarding the performance and survival rate of immediately inserted dental implants placed prior to radiotherapy. Of 1003 articles, 10 were finally included comparing immediate vs. delayed placement of implants and comparing the effect of radiotherapy on immediately placed implants. Meta-analysis demonstrated a slightly higher survival of immediately placed implants compared with postponed placed implants [risk ratio: 0.92, 95% confidence interval (95% CI): 0.48-1.78, P = 0.81, I2 = 0%]. The other meta-analysis comparing radiotherapy vs. nonradiotherapy showed a clearly better survival of immediately placed implants not having received radiotherapy (risk ratio: 5.02, 95% CI: 0.92-27.38, P = 0.10, I2 = 56%). SUMMARY: Guidelines are recommended for immediate dental implant placement in the edentulous mandible in HNC patients prior to radiotherapy to allow homogeneity regarding the treatment protocols and thus comparison of treatment outcomes.

Metal-insulator-metal (MIM) stacks, though simple in design, are the backbone device for resistive random access memories (ReRAM) and, as such, play a vital role in emerging memory technologies. In this work, we characterize the impact of Ar, Ar/N2, and BCl3/Cl2 plasma processes on the physical properties of the TiN bottom electrode (BE) surface. The BCl3/Cl2 process increases roughness by 40%. Ar and Ar/N2 processes both decrease PVD TiN roughness by 50%. This reduction propagates through the entire MIM stack. X-ray photoelectron spectroscopy (XPS) indicates that both plasma processes alter the Ti-ON concentration on the TiN surface. The impact of BE surface roughness and composition on MIM electrical properties is currently under investigation.

Direct, atomic-scale visualization of polarization switching in a functional, polycrystalline, binary oxide via insitu high-resolution transmission electron microscopy (HRTEM) biasing is reported for the first time. Antiferroelectric (AFE) ZrO 2 was used as the model system, which is important for commercial DRAMs and as emerging NVMs (through work-function engineering). We observed (1) clear shifting and coalescing of domains within a single grain, and (2) dramatic changes of the atomic arrangements and crystalline phases-both at voltages above the critical voltage measured for AFE switching. Similar synergistic in-situ structural-electrical characterization can pave the way to understand and engineer microscopic mechanisms for retention, fatigue, variability, sub-coercive switching and analog states in ferroelectric and AFE-based memory devices.

In this work, we presented the Hf-Zr system as a case study of materials that were evaluated in the past and are now receiving renewed interest due to its potential use in artificial intelligence (AI). A historical overview of Hf-Zr research and its promising new applications for emerging memories will be shared.

This paper investigates the p-Ge/Al2O3/ZrO2/TiN gate stacks that were subjected to different slot plane antenna oxidation (SPAO) conditions: 1) prior to any high-k atomic layer deposition (ALD); 2) in between Al2O3 and ZrO2ALD layers; and 3) after the ALD of high- ${k}$ layers. The carrier transport mechanisms as a function of temperature on these samples were observed to be different. The SPAO treatment effectively removes the trap centers in ZrO2 and Al2O3 layers depending on the SPAO treatments. Fowler-Nordheim tunneling seems to be the dominant transport mechanism at high field range when SPAO was performed after the high- ${k}$ layers were deposited. On the other hand, Poole-Frenkel emission and hopping conduction mechanism are dominant for other two samples in both gate electron injection and substrate electron injection (SEI) modes. The trap center ( $ {\phi }_{\text{t1}} = {0.13}$ eV) remains in the ZrO2 when ZrO2 is not subjected to the SPAO. Trap energy level $ {\phi }_{\text{t1}}$ (0.13 eV) was removed and $ {\phi }_{\text{t2}}$ (0.27 eV) still exists when only Al2O3 oxide layer was exposed to SPAO. Hopping distance, ${a}$ (about 0.3 nm) is extracted by hopping conduction model. After time dependent dielectric breakdown measurement, it was found that if GeO2 exists at the interface then it can be degraded easily by SEI stress. On the other hand, if SPAO was processed in between the high- ${k}$ layers the formation of a GeOx layer enhances the interface quality and provides better immunity to degradation under stress.

Neuromorphic computing represents a potential paradigm shift from conventional von Neumann computing architecture and shows promise for achieving massive parallelism and power efficiency for such data-centric tasks as image recognition and language processing. Based on the concept of synaptic plasticity, human-like machine learning can be potentially realized by use of arrays of electronic synapses that function in an analogous manner to biological neurons. One of the key features of this type of computing is the ability to control synaptic weights in an analog-like fashion for use in both inference and training applications. A number of existing device technologies in non-volatile memory systems exhibit attractive characteristics for such synaptic devices.[1,2] In particular, resistive switching devices (resistive random-access memory or ReRAM) can change and store their conductance value (G) in response to electrical stimuli making them potentially enabling for deep learning applications involving synaptic weights. For ReRAM devices, HfO2-based thin films can be utilized for filamentary oxide ReRAM and are an attractive option due to their fab-friendly processing and current implementation in high-volume manufacturing. In this study, we evaluated atomic layer deposition (ALD) for the growth of HfO2 for integration in both front-end-of-line (FEOL) and back-end-of-line (BEOL) compatible test structures on 300 mm wafers in order to optimize electrical performance for use as synaptic device elements in neuromorphic architectures. The effect of oxidant in the ALD process was evaluated and it was shown that H2O outperformed O3 in terms of better uniformity and lower forming voltage. By utilizing a hydrogen-based plasma either after the deposition or inserted as an intermediate step during deposition we were able to further decrease forming voltage for a fixed dielectric thickness. Reducing deposition temperature to 200°C in conjunction with the hydrogen-based plasma treatment offered an additional tuning knob to further reduce forming voltage. Stable high-resistance switching (> 100 kΩ) with analog behavior in scaled BEOL devices was also obtained using this optimized HfO2-based ReRAM. Additionally, a tight distribution of forming voltage was obtained ensuring that 99.9999% devices in a 14 nm ReRAM module can be formed below the targeted voltage. References Kuzum et al., Nanotechnology, 24, 382001 (2013) W. Burr et al., Advanced in Physics:X, 2, 89 (2016)

One of the key challenges for Ge gate stack is to achieve an improved interface quality between Ge and the high-K dielectric. In order to overcome this limitation, various interface treatments like ozone pre-gate treatment and ozone ambient annealing (1), nitridation of Ge surface (2),formation of a GeO2 layer between Ge and high-K dielectric using ECR plasma technique (3) and formation of an ultra-thin SiO2/GeO2bilayer have been tried. It has recently been reported that slot plane antenna(SPA) microwave plasma treatment helps to improve the EOT and enhances the oxide quality by reducing impurities and leakage current when the dielectric is exposed during or after deposition (4). Moreover SPA oxidation possesses the unique property of having low electron temperature, which makes it a very low damage process compared to other techniques,either inductively coupled plasma(ICP) and electron cyclotron resonance(ECR) plasma (5). In this study we investigated the impact of SPA plasma oxidation (SPAO) treatment in improving the interface quality when MOS capacitors were fabricated on 300mm p-type Ge substrates. SPAO plasma treatments were performed at different steps in the high-k deposition process. The substrate was initially subjected to a dry chemical oxide removal (COR) process. Subsequently, three different sets of samples were prepared with the exposure of SPAO plasma at following locations (Fig.1): CASE-1: SPAO plasma treatment after Al2O3(1nm)/ZrO2(3.5nm) deposition; CASE-2: SPAO plasma treatment was carried out in between Al2O3(1nm) and ZrO2(3.5nm) deposition; CASE-3: the Ge substrate was exposed to SPAO plasma treatment after COR and prior to Al2O3(1nm)/ ZrO2(3.5nm) layer deposition. Al2O3(1nm) and ZrO2(3.5nm) layers were deposited by atomic layer deposition. Capacitance-voltage at multi-frequencies,current-voltage and conductance measurements were performed at room temperature. Parameters like flatband voltage (Vfb), equivalent oxide thickness(EOT), interface state density(Dit),and leakage current were estimated accurately after quantum mechanical corrections and eliminating the series resistance effect. As shown in Fig. 2 lowest fast interface state density is achieved when SPAO plasma treatment was performed after Al2O3 and prior to ZrO2 deposition (CASE-2). A comparable Dit is also observed when plasma exposure was done after the entire gate stack deposition (CASE-1) (Fig.2). From different experimental results significant degradation to both the dielectric quality and interface was observed when SPAO is performed just after COR (CASE-3). References: 1) Zhao Mei et al, Journal of Semiconductors, Volume 34, No. 3, 2013. 2) A. Dimoulas et al, Appl. Phys. Lett., volume 86, no. 3, 2005. 3) Yukio Fukuda et al, IEEE transaction on electron devices, volume 57, No. 1, 2010. 4) M.N. Bhuyian et al, ECS Journal of Solid State Sci and Techn, vol. 3(5), N83, 2014. 5) C. Tian et al, J. Vac. Sci. Technol. A 24, 1421, 2006. Figure 1

Miniaturization in Integrated Circuit fabrication has scaled to atomic dimensions in recent times. With critical device dimensions moving into the range of ~10nm, atomic layer processing control is becoming essential. Atomic Layer Deposition (ALD) uses separated film components at (or near) self-limiting conditions for atomic level uniformity and thickness control. The unique nature of ALD processing has opened the opportunity for a deposition technique that presents deposition components in a spatially separated method compared to sequential component exposure of traditional systems. Spatial ALD has differentiating characteristics that can benefit IC Fabrication at current fabrication dimensions. Historically, deposition systems for IC fabrication use batch furnace or single wafer configurations. The economic benefit of batch furnace processing has been challenged by the enhanced capabilities of single wafer processing as IC scaling emphasized critical film properties and uniformity. ALD processing has rejuvenated batch furnace benefits since separate exposures of deposition components provides excellent uniformity from self-limiting deposition layers, and lower particle defectivity since the components don’t mix. However, the sequential processing of individual components has strained the efficiencies of batch furnace and single wafer ALD processing. Spatial ALD moves substrates (wafers) through each deposition component separately in space, compared to the time sequential processing of batch furnaces and single wafer processing. There are several advantages to Spatial ALD processing, and several unique capabilities that can apply to IC fabrication. By depositing through movement, the deposition components can be maintained through a steady state, which is advantageous for plasma processing and for limiting peripheral equipment film accumulation. By its nature, the deposition rate of Spatial ALD is controlled by the speed of substrates passing through the deposition zones, which can provide unique controls for deposition. Deposition chemistry and process conditions can be designed to take advantage of Spatial ALD properties for unique benefits in IC fabrication. The presentation will explore some fundamental aspects of Spatial ALD processing, the dependency and opportunities of relevant chemistries, and potential applications for the unique capabilities of Spatial ALD, including unsaturated process conditions.

Even through Ge/high-k interface has been extensively studied the high leakage current associated with these gate stacks continues to introduce frequency dispersion and hysteresis in capacitance-voltage (CV) and conductance-voltage (GV) characteristics. These dispersions severely limit the understanding the interface and accurate estimation of interface state density, Dit and equivalent oxide thickness (EOT). Since several parameters like EOT, flatband voltage, bulk doping, surface potential as a function of gate voltage are important and bulk defect and interface defect concentration affect the CV and GV characteristics several corrections to the characteristics are required to obtain accurate values. We have measured the CV and GV characteristics of Ge/ALD 1nm-Al2O3/ALD 3.5nm-ZrO2/ALD TiN MOS capacitors with three different interface treatments by HP4284 LCR meter using different frequencies. The interface treatments are (i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) followed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR&SPAOx); and (iii) COR followed by vapor O3 treatment (COR&O3). The plots were corrected by three different methods. Firstly, we removed the effect of sheet resistance, RS . The second approach uses data (capacitance and conductance) measured at two different frequencies to solve two unknown variables (capacitance and conductance) (1). The solved CV plot is closer to the corrected CV plot at 1 MHz rather than that at 100 KHz. This allows us to use 1MHz corrected data to obtain the EOT information. Additionally, this approach helps to verify that 1MHz data is robust assuming that defects do not respond to the other frequencies used here. The third approach is to modify the measurement circuits (2) to enhance CV and GV characteristics. Fig. 1 shows the CV characteristics after the corrections by three different approaches for three different samples. COR&SPAOx samples show excellent CV characteristics. The details of all the correction methods and the advantages of these methods to correct CV and GV will be discussed. We will demonstrate that the correction methods are suitable for accurately measure the interface characteristics. The Dit calculated by two method (conductance and capacitance spectroscopy) (Fig. 2) are compared and discrepancy of the results between different samples and different methods will be explained. References Y. Ding and D. Misra, J. Vac. Sci. Technol. B, 33, 021203, 2015. K.J. Yang and C. Hu, IEEE Trans on Electron Dev, 46(7), 1500, 1999. K.S.K Kwa, S. Chattopadhyay, N.D. Jankovic, S.H. Olsen, L.S. Driscoll, and A.G. O'Neill, Semicond. Sci. Technol., 18(2), 82, 2003. Figure 1

We report on Atomic Layer Deposition Titanium (ALD Ti) for FinFET source/drain contact applications. On planar test structures, we accurately benchmark contact resistivity (ρc) of ALD Ti, ∼1.4×10–9 Ω·cm2 on Si:P and ∼2.0×10–9 Ω·cm2 on SiGe:B, among to lowest reported values in literature. Ultralow ρc is resulting from enhanced Ti/Si(Ge) reactivity originating in the ALD process. We also demonstrate capability of this process to significantly lower Rc on FinFETs by allowing a lateral contact into the S/D area effectively maximizing the contacting area.

As Si metal oxide semiconducting field effect transistors have continued to scale, SiO2-based gate dielectrics and polySi gates have beensuccessfullyreplacedbyHfO2-basedhigh-kdielectricsandmetal gates at the 45nm technology node and beyond. In order to continue scaling, improvements of key film properties of the high-k dielectric, such as k-value, equivalent oxide thickness (EOT) and leakage current, are needed. A reduction in EOT can be achieved by reducing the thickness of the gate dielectric with the associated drawback of increased gate leakage, or by increasing its effective dielectric constant (k-value). In this regard, the electrical properties of HfO2-based dielectrics may be enhanced by structural modifications, since the kvalue has been shown to be dependent on the crystalline phase (monoclinick =16,tetragonalk =70andcubic =29). 1 HfO2 filmstypically crystallize into the monoclinic phase, which is its most thermodynamically stable phase. 2,3 One method of stabilizing the metastable cubic

SEMATECH evaluated the impact of various process options on the overall manufacturing cost of a TSV module, from TSV lithography and etch through post-plate CMP. The purpose of this work was to understand the cost differences of these options in order to identify opportunities to significantly reduce cost. Included in this study were multiple process and materials options for TSV etch, liner, and barrier/seed (B/S). For each of these options, recipes were adjusted for post-etch clean, ECD Cu fill and CMP overburden, and the resulting cost impacts were evaluated. The TSV dimensions used in this study are 5x50 μm and 2x40 μm. These cost comparisons included a sensitivity analysis, highlighting the main factors responsible for the differences. Cost of materials, tool cost, and throughput were the primary factors affecting cost differences, especially in barrier/seed deposition. In some cases the contributions from both these sources were comparable. We explain the assumptions used and some of the uncertainties inherent in this work. For example, where materials costs were significant, we extrapolated the cost of new materials from research quantities to those needed to support high volume manufacturing. We had to estimate throughputs and materials costs using our best engineering judgment, because the recipes have not yet been optimized. We also considered that the tools used on some non-critical steps might be fully depreciated, or a lower cost tool such as is used in wafer level packaging. Despite these uncertainties and assumptions, we were able to extract some fairly clear conclusions. The process options include the following B/S variations: For 5x50 μm TSVs, the B/S film structure is TaN/Ta/Ru/Cu, and the options are with and without the Ru and/or Cu layers. For 2x40 μm TSVs, the B/S structure is TaN/Ru/Cu, with different thicknesses of Ru, and the Cu is an optional seed layer for the field. We also discuss the impact of scaling the TSV dimensions on manufacturing costs. This work is continuing to look at different process options and to apply this methodology to MEOL modules such as temporary bond and debond, wafer thinning, and TSV reveal.

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.

CMOS device scaling below the 22 nm technology node requires gate dielectric materials with superior properties to those of conventional high-k materials. It was found that, Al incorporation into HfO2 results in an increase in the transition temperature from amorphous to polycrystalline state (1-2). Improved thermal stability (2) and enhanced permittivity (3) by Al doping into ALD HfO2 was also reported. As a result of the improvement in film properties, improved equivalent oxide thickness (EOT) values, reduced gate leakage current, lower hysteresis and improved interface quality were also observed for Al doped HfO2 (4-6). However, intermixing of HfO2 and Al2O3 depends significantly on the stack structure, which results in variations in the stoichiometry in the film (7). The relative position of HfO2 and Al2O3 in HfO2/Al2O3bi-layer has a significant influence on positive charge formation in the dielectrics and also on the quality of the interfacial layer (IL) (8-10). In this work, we deposited and studied the reliability of 40 cycles ALD HfO2 doped with Al in the deposition process. The ALD thin film composition was measured by X-ray photoelectron spectroscopy (XPS). Thin films with Al/(Al+Hf)% composition ranging 0% to 8% were deposited and annealed at 800oC in N2 ambient. MOS capacitors were then fabricated with ALD TiN as the metal gate. The electrical measurements show that, devices with ~2% Al/(Hf+Al)% have an optimized performance with 17% lower EOT than undoped HfO2. The amount of positive charge and gate leakage current density were also evaluated for all devices. The reliability of these devices was monitored by subjecting them to a constant field stress at E= 27.5 MV/cm in the gate injection mode, where the applied voltage to the gate was modified according to the EOT to have equal field across all the dielectrics. Stress-induced trap generation in the dielectrics was observed due to bulk and interface defects. Trap formation followed a power law function with stress time. Observed stress induced flat-band voltage shift (Fig. 1) shows that devices with Al/(Hf+Al)% =2% have 36% reduction in the rate of trap generation as compared to HfO2, whereas degraded flat-band voltage shift was observed for devices with Al/(Hf+Al)% =7%. It can be inferred that an optimized Al concentration in HfO2can lead to an improvement of the device performance. In order to further understand the reliability characteristics we plan to evaluate the change in interface state density with stress and their time dependent dielectric breakdown (TDDB) characteristics. References M.-Y. Ho et al., Appl. Phys. Lett., 81, 4218 (2002). H. Y. Yu et al., Appl. Phys. Lett., 81, 3618(2002). P. K. Park et al., Appl. Phys. Lett., 89, 192905(2006). W. J. Zhu et al., IEEE Electron. Dev. Lett., 23(11), 649(2002). V. Mikhelasvili et al., Appl. Phys. Lett., 85, 5950(2004). Y.-K. Chiou et al., J. Electrochem. Soc., 154 (4) G99(2007). M. H. Cho et al., Appl. Phys. Lett., 81, 1071(2002). B. H. Lee et al., Appl. Phys. Lett., 76, 1926 (2000). L. G. Gosset et al., J. Non-Cryst. Solids, 303, 17(2002). W. Wang et al., J. Appl. Phys., 105, 064108 (2009).

Resistive random-access memory (RRAM) device has attracted wide attention for next-generation nonvolatile memory (NVM) application due to simple structure, high cycling endurance, good retention, low power consumption and fast switching time (1, 2). In recent years, RRAM devices are extensively researched for multi-level data storage (3, 4). RRAM devices can be driven to various resistance states by applying suitable compliance current values during the switching operation. In this work, multilevel resistive switching behaviors of RRAM devices with three different dielectric materials like HfO2, HfAlO2 and HfZrO2 are investigated with fixed top/bottom electrodes. To control the resistance state, a thin Al2O3 layer (1 nm) was inserted between the bottom electrode and switching dielectric (Ti/TiN/Al2O3/HfAlO2 or HfZrO2 or HfO2/Ti/TiN). The fabrication details of these devices are presented elasewhere (5). Fig. 1 shows DC endurance cycling on the LRS/HRS resistances of the three RRAM structures, (a) HfAlO2, (b) HfZrO2 and (c) HfO2 for different increasing compliance currents. The endurance cycling is performed with 20 cycles per compliance level. As can be seen from the figure, different low resistance states (LRS) and high resistance states (HRS) are well resolved after dc endurance cycling for HfAlO2 and HfZrO2 based RRAM devices. Devices with HfO2, on the other hand, does not show any multilevel LRS or HRS behavior for increase in compliance current. The reason is possibly due to the lack of oxygen vacancies available in the HfO2-RRAM structure. When HfZrO2 was subjected to a post deposition annealing (PDA) in nitrogen environment, the resistance distribution of LRS and HRS was improved, possibly due to improvement of dielectric quality while the oxygen vacancy concentration remained the same. To further improve the resistance window an additional 2 nm thick TiN layer was added before the Ti layer on top electrode of HfZrO2 based RRAM. The cycle to cycle distribution of HRS/LRS resistance of HfZrO2 based RRAM was significantly improved while the compliance current for switching was increased. In summary, process optimization and electrode selection with HfZrO2 as the switching layer can provide significant multilevel storage in RRAM devices. References: E. Ambrosi, A. Bricalli, M. Laudato and D. Ielmini, Faraday discussions DOI: 10.1039/c8fd00106e (2018). A. Prakash and H. Hwang. Physical Sciences Reviews, vol. 1(6), (2016) Chen, et al., Semiconductor Science and Technology7 (2015): 075002. J. Jang and V. Subramanian. Thin Solid Films 625 (2017): 87-92. D. Misra, S. Sultana, B. Jain, N. Bhat, K. Tapily, R.D. Clark, S. Consiglio, C.S. Wajda, and G.J. Leusink, ECS Trans., vol. 86(2), 77, 2018. Figure 1

We have integrated ALD barrier and Ru liner for novel interconnect integration and have evaluated electrical properties and time dependent dielectric breakdown (TDDB). RC and via resistance were reduced by the ALD barrier, and particularly it was confirmed that TDDB performance can be improved by using ALD TaAlN with an ultrathin film. Accordingly, ALD TaAlN barrier and CVD Ru liner are attractive barrier/liner combination for next generation interconnect integration schemes.

Next generation CMOS devices use a high-κ dielectric layer (HfO 2 , HfSiO, HfSiON and La 2 O 3 ) grown on thin interfacial silicon dioxide as the gate dielectric. The higher dielectric constant of the Hf oxide based film stack allows a decrease in equivalent oxide thickness (EOT). Because the high-κ film stack has a greater physical thickness than an electrically equivalent SiO 2 film, the tunneling current decreases. It is a critical metrology requirement to measure the thickness of silicon dioxide and high-κ film stacks. Spectroscopic ellipsometry (SE) in the far UV wavelength region can be used to differentiate the high-κ films from silicon dioxide. This is due to the non-zero nature of the imaginary part of the dielectric function (beyond 6 eV) in the far UV region for high-κ films. There has been some conjecture that optical studies should be extended beyond 150 nm further into the VUV. This study addresses these concerns through determination of the dielectric function down to 130 nm. We show the fitted dielectric function of hafnium silicates and lanthanum oxide down to 130 nm. X-ray reflectivity (XRR) measurements were also performed on the high-κ films to complement the thickness measurements performed with SE.

We have previously shown that by varying the position of threshold voltage adjustment cap layers within the gate stack, as well as the oxidant used during processing, it is possible to tune the threshold voltage of n-FET devices, and to concurrently realize a scaling benefit by incorporating group IIA and group IIIB elements into gate dielectrics deposited by metalorganic atomic layer deposition. In this report we have focused on lanthanum oxide cap layers that provide band edge nFET work functions. We compare our previously reported results with ozone oxidation with newly developed processes using oxygen and water as oxidants that result in highly scaled devices with band edge work functions and acceptable leakage characteristics.

Non-volatile resistive random-access memory (RRAM) devices are currently being investigated as a low power, high density and high-speed alternative DRAM (1). A transition metal oxide dielectric layer is typically used as an insulating layer in a metal-insulator-metal (MIM) structure. To reduce the large variability of switching parameters and high operation current in these RRAM devices, bilayer dielectric structures are being explored. In this work we have used several different bilayer structures using different dielectrics. In each device the bottom electrode (BE) was 10nm Ti/50nmTiN followed by 1nm Al2O3. The second dielectric layer or the switching layer was a 7-nm HfO2 (R3), HfZrO2 (R4 with Hf:Zr%=50%) or HfAlO2 (R1 with Hf:Al%= 3%) followed by the top electrode (TE) constituting of 8nm Ti/6nm ALD TiN+50nm PVD TiN. In some cases, the top electrode was varied to 2nm ALD TiN/8nm Ti/6nm ALD TiN+50nm PVD TiN (R5) by adding a 2nm ALD TiN layer prior to 8nm Ti. Some devices with HfZrO2 (R2) were subjected to a post deposition anneal (PDA) at 700oC for 60 s. In all cases, to enhance the switching characteristics on the top electrode 8 nm Ti was used as the cap layer material except in the case of R5 where 2nm of ALD TiN was deposited prior to 8 nm of Ti. The use of thin dielectric layer of 1nm Al2O3 was to suppress the sneak-path problem (3) in the low resistance state (RON). Comparing the variation of switching layer, it was observed that the device with 1nm Al2O3/7nm HfAlO2 (R1) provided the superior average Roff/Ron values and both set and reset power compared to HfO2 (R3), and HfZrO2 (R4) devices. When the HfZrO2 (R4) devices were compared with the identical device with PDA (R2) Ron increased and Roff decreased for the PDA device, reducing the Roff/Ron value. Variation of cap layer to TiN instead of Ti also showed similar Roff/Ronbehavior. D. Ielmini, Semicond. Sci. Technol. Vol. 31, 063002, 2016. Xiaorong Chen and Jie Feng, Appl. Phys. A, vol. 120, 67 2015 U. Chand, K-C. Huang, C-Y. Huang, and T-Y. Tseng, IEEE Trans. on Electron Devices, vol. 62(11), 3665, 2015

The continued scaling of MOSFET devices necessitates the scaling of the gate dielectric in terms of equivalent oxide thickness (EOT) and associated k-value. As a replacement for SiO2 based gate dielectrics, which have reached their fundamental scaling limit, Hf-based dielectrics including HfO2, Hf silicate and nitrided Hf silicate have been chosen as viable materials.[1] Though the HfO2-based materials have generally been preferred, recent studies have shown that HfO2 with an admixture of ZrO2, which are both fully miscible, has the potential to provide a higher dielectric constant by means of stabilization of higher-k phases.[2,3] Moreover, the mixed oxide HfxZr1-xO2 has been shown to exhibit improved device performance and reliability compared to HfO2.[4] For the deposition of ultra-thin high-k gate dielectric films on planar structures, chemical vapor deposition may offer advantages in terms of wafer throughput, manufacturability, cost of ownership, and process flexibility compared to the alternately pursued atomic layer deposition based approaches. In this study we investigated the process characteristics and film properties of HfZrO4 (HfO2:ZrO2=1) thin films deposited using metallorganic chemical vapor deposition on a 300 mm production-worthy deposition chamber. The mixed oxide films were deposited using a mixture of Hf-t-butoxide and Zr-t-butoxide (1:1 molar ratio) at a wafer temperature of either 380°C or 480°C using O2 as a co-reactant. The Si wafers had a thin (~8A) layer of chemically grown SiO2. The physical properties of the films were analyzed using various characterization techniques including spectroscopic ellipsometry, corona-oxide-semiconductor (Quantox) leakage measurements, XRR, angle-resolved XPS, RBS, ICP-AES, and TEM. MOS capacitor structures featuring HfZrO4 dielectric were fabricated and tested using C-V and I-V measurements. Key electrical parameters (EOT, leakage current density, VFB) were compared with structures featuring HfO2 deposited using the same deposition system and process conditions used for the HfZrO4 process. The HfZrO4 growth rate (Fig.1) was observed to be the same for both deposition temperatures, thus indicating a mass transport limited growth rate regime. Density was observed to increase with deposition temperature in line with reported values for ALD-deposited HfZrO4 from metal chloride sources.[3] The increase in film density (and possibly decrease in film impurities) is also corroborated by improved Quantox measured leakage (Fig.2) as well as increase in metal coverage rates (Fig.3). Improvements in Jg vs EOT trends were observed when comparing HfZrO4 with HfO2 in MOS capacitor structures. Additionally, no measurable difference in CV hysteresis was observed for HfZrO4 compared to HfO2. In our deposition system an excellent wafer-to-wafer repeatability (0.86%) was observed for a mean thickness of 19 A over a 50 wafer run. These results indicate that MOCVD HfZrO4 is a promising material for advanced high-k applications. Figure 1. XRR measured thickness values and densities for HfZrO4 films deposited at 380°C and 480°C and associated growth rates determined from linear fits.

Material interactions in advanced high-κ / metal gate stacks can have a significant effect of the performance of completed devices. The effect of these interactions was investigated using planar MOS capacitor stacks that might be used for the gate of a MOS transistor. Gate electrode materials included TaN, TaSiN, and W, and HfSiO and HfSiON were used as the gate dielectric materials with an ultra-thin SiO2 interface between the silicon substrate and the dielectric. Deposition methods included CVD and ALD.

Cu-fill extendability is demonstrated with a novel integration scheme using clustered ALD barrier, CVD Ru liner and PVD Cu dry-fill processes.

Over the past decade traditional scaling by simple linear shrinking has effectively ceased as IC makers have adopted new 3-dimensional device structures, complex integration schemes and new processes and materials for an expanding number of applications in order to overcome fundamental physical limits. This trend will accelerate as devices are scaled to a level approaching atomic dimensions. Dielectric materials with tailored properties are required to meet future device needs. And deposition processes that are self-limited (e.g. Atomic Layer Deposition (ALD)), or self-directed (e.g. selective deposition) will enable those materials to be used in scaled 3D devices. Highly tailored ALD processes are being investigated to fabricate functional material layers. Interspersed treatments and doping to make ternary materials may be used to modify the physical and electrical properties of ALD films further in order to optimize the resulting physical or electrical properties. To improve device contacts, ultra-thin dielectrics and metal layers may be deposited inside of high aspect ratio contact structures in order to provide lower contact resistivity- or may be used to provide solutions for integration of new contact structures. Selective deposition processes can be used to deposit functional materials only where they are needed, thus reducing the patterning burden during IC manufacturing. Future use of new transistor channel materials, such as III-V and Ge, will require the use of ALD gate dielectrics with compatible treatment schemes in order to passivate defects and provide EOT scaling inside of ultra-high ratio replacement gate structures. Examples of these and similar processes will be described and discussed with the goal of discerning a path beyond 10nm devices.

We demonstrate statistically significant data for specific contact resistivity (ρ c ) of sub-10−8Ω-cm2 and sub-2×10−8Ω-cm2 for N-type and P-type Si respectively on 300mm wafer by introducing ultra-thin ALD high-k dielectric layer(s) between the metal and Si. A 6-terminal Cross-Bridge Kelvin (6T-CBK) structure was used for the extraction to achieve excellent resolution in this small ρ c range. With the help of measurements from multiple dielectric stacks and Non-Equilibrium Green's Function (NEGF) based quantum transport calculations, we clearly show that the suppression of evanescent metal induced gap states (MIGS) and formation of interface dipole play significant role to reduce the ρ c as long as the tunneling resistance of the dielectric stack is small. Finally, transient response, break down mechanism and technology benchmarking are discussed which show promise for sub-14nm node applications.

A method for the in situ measurement of mechanical stress in thin films deposited in a vacuum system is presented. The bending of the substrate, a measure for mechanical stress in the deposited layer, is detected by reflecting two parallel laser beams off the surface of the substrate and measuring the angle between the two reflected beams. A hollow mirror in the path of the reflected beams acts as an ‘‘optical cantilever’’ and increases the sensitivity of this method. In the present setup it is possible to detect the difference between a flat substrate and a substrate with a radius of curvature of 6.5 km.

Rutherford backscattering spectroscopy (RBS) has been an important analytical method for determination of the depth distribution of elemental concentrations in materials. The depth resolution of RBS is typically limited by the energy resolution of ion detectors. In this work we demonstrate the use of a compact magnetic spectrometer as the ion energy detector for high resolution RBS analysis. The magnetic spectrometer offers several advantages: (1) a high energy resolution ΔE/E∼1/2000; (2) a large bending power for MeV ions; and (3) a particular configuration allowing for true 180° RBS analysis. By combining this magnetic spectrometer with the grazing angle geometry, we have achieved a depth resolution better than 5 A for RBS analysis of concentration distributions in elemental (e.g., Ta) and compound (e.g. HfO 2 ) thin films using 2 MeV helium ions. These experimental results suggest that high‐resolution characterization of nanoscale thin films can be realized using MeV ions in conjunction with such magnetic spectrometers.

The continuous scaling of Cu interconnects for sub-10nm technology nodes calls for development of ultrathin and conformal Cu diffusion barriers. Due to its ability to conformally deposit films with nanoscale thickness control, atomic layer deposition (ALD) is an attractive method for depositing refractory metal nitride diffusion barrier layers, as opposed to a line-of-sight technique such as physical vapor deposition (PVD).[1] In this regard we have previously demonstrated extendability of Cu fill (with Ru seed layer) below 25 nm linewidth (200 nm height) when PVD TaN is replaced with ALD TaN.[2] In 40 nm Cu dual damascene structures with 3 nm barrier layers, ALD TaN has also been shown to reduce via resistance by ~28% compared to PVD TaN in spite of 20x lower blanket resistivity for PVD TaN.[3] In order to further improve ALD grown TaN and minimize Cu-diffusion through these ultrathin barrier films, it is desirable to avoid forming polycrystalline films with inherent grain boundary diffusion pathways. Accordingly, alloying refractory transition metal nitrides with a third element (as for example Al) may offer a promising method for maintaining metastable amorphous films by interrupting the typical polycrystalline phase formation.[4,5] In this study, ultrathin TaN and ternary Ta1-xAlxNy films (denoted TaAlN) were deposited by ALD using metallorganic precursors and were evaluated for their effectiveness in Cu diffusion barrier applications compared to a PVD grown TaN control. TaN was deposited using tert-butylimido tris(ethylmethylamido)tantalum (TBTEMT, Ta(NCMe3)(NEtMe)3) and NH3 at 350 °C with a growth per cycle (GPC) of ~ 0.7 Å/cycle. ALD TaAlN ternary alloy films were deposited by addition of trimethylaluminum/NH3 cycles to the TBTEMT/NH3cycles using Ta:Al cycle ratios in the range 16:1 to 2:1, resulting in Al/(Al+Ta)% in the range of 21% to 88%. The effectiveness of the barrier layers against Cu-diffusion in advanced interconnects were investigated using in-situ ramp anneal synchrotron x-ray diffraction (XRD) [6,7] to study the effect of annealing on Cu diffusion with the presence of these ultrathin (~1.8 nm) barrier layers interposed between 50 nm PVD grown Cu and the Si substrate. The barrier failure temperature (Tc) was determined based on the onset of Cu3Si XRD peaks during the in-situ ramp anneal. The kinetics of Cu3Si formation was assessed by XRD using multiple ramp anneal rates and performing a Kissinger-like analysis [6] to determine the effective activation energy (Ea) for silicidation in presence of the Cu diffusion barrier layers. Compared to the film stack with PVD TaN barrier, the stacks with ALD TaN and TaAlN (Ta:Al = 8:1) exhibit a slightly higher Tc for Cu silicidation. The effective activation energy of Cu3Si formation for stacks with ALD TaN (Ea ~ 1.5 eV) and TaAlN (Ea ~ 1.3 eV) are close to the reported value for grain boundary diffusion of Cu (1.3 eV) [8], whereas the Cu3Si effective activation energy for the stack with PVD TaN (Ea ~ 2.3 eV) is closer to the reported value for lattice diffusion (2.7 eV).[8] Although the temperature of Cu3Si crystallization and corresponding barrier failure temperature is higher for these ALD barrier films compared to the PVD barrier TaN film, the failure mechanism for the ALD barriers is most likely dominated by grain boundary diffusion whereas the initial failure mechanism for the PVD barrier may be dominated by lattice diffusion. References [1] H. Kim, S-H. Kim, and H.-B.-R. Lee, Atomic Layer Deposition for Semiconductors, C. S. Hwang. Ed.; Springer, New York, 2014; pp. 209-210. [2] K. Yu, T. Hasegawa, M. Oie, F. Amano, S. Consiglio, C. Wajda, K. Maekawa, and G. Leusink, Proceedings of 2014 IEEE International Interconnect Technology Conference/Advanced Metallization Conference (IITC/AMC), 117 (2014). [3] O. van der Straten, X. Zhang, K. Motoyama, C. Penny, J. Maniscalco, and S. Knupp, ECS Trans., 64(9), 117 (2014). [4] M.-A. Nicolet, Appl. Surf. Sci., 91, 269 (1995). [5] M.-A. Nicolet and P.H. Giauque, Micro. Eng., 55, 357 (2001). [6] W. Knaepen, C. Detavernier, R.L. Van Meirhaeghe, J. Jordan Sweet, and C. Lavoie, Thin Solid Films, 516, 4946 (2008). [7] G. Rampelberg, K. Devloo-Casier, D. Deduytsche, M. Schaekers, N. Blasco, and C. Detavernier, App. Phys. Lett., 102, 111910 (2013). [8] T. Oku, E. Kawakami, M. Uekubo, K. Takahiro, S. Yamaguchi, and M. Murakami, Appl. Surf. Sci., 99, 265 (1996). Figure 1

As Si Metal Oxide Semiconducting Field Effect Transistors (MOSFETs) have continued to scale Short Channel Effects (SCE) have become exacerbated by the inability to continue scaling the Equivalent Oxide Thickness (EOT) of the device significantly beyond what was realized with the introduction of High K Metal Gate (HKMG) MOSFETs at the 45nm technology node. Since EOT scaling has not kept pace with the gate length (Lg) scaling needed to continually increase the transistor drive current, device makers have instead elected to introduce FinFET and Tri-Gate transistors with inherently better electrostatic control in order to realize reasonable SCE in the device. High mobility channel materials, such as Ge, are attracting increasing interest due to the possibility of realizing increased performance even without scaling the Lg of the device (1). Ge is particularly attractive for use as a channel material for P-type MOSFETs (PMOSFETs) due to its high hole mobility and Si processing compatibility. In fact, we have demonstrated experimental PMOSFET devices with hole mobilities significantly higher than what can be obtained on Si, Fig. 1. However, a significant remaining challenge to incorporating Ge into VLSI production is obtaining a stable and well-passivated dielectric/semiconductor interface using tooling and substrates compatible with current 300mm Si VLSI High Volume Manufacturing (HVM) in order to achieve reasonable device performance at sub 1nm EOTs (2). In this paper we will report progress on surface passivation and functionalization of Ge channel surfaces, as well as High K dielectric layer growth by Atomic Layer Deposition (ALD) and the resulting electrical properties measured by fabricated MOSFETs and Metal Oxide Semiconducting Capacitors (MOSCAPs). The Ge channel devices were formed on 300 mm Si wafers using Ge grown by an epitaxial process including a graded SiGe buffer layer. We have utilized a TEL CertasTMChemical Oxide Removal (COR) process (3), which uses dry HF and ammonia, rather than traditional wet cleaning, to remove Ge native oxides without damaging or roughening the fragile Ge surface. We have also studied Ge oxide interface layer formation by plasma oxidation using a Slot Plane Array (SPA) antenna (4) utilizing in-line X-ray Photoelectron Spectroscopy (XPS) to measure Ge and high K oxide thickness on monitor wafers fashioned by the same Ge epitaxial process used to make the electrical devices and compared it to the equivalent Si oxidation process, Fig. 2. Various other passivation and interface schemes were investigated and will be discussed, contrasted and compared including ozone oxidation, Al oxide passivation/interface layers, SPA plasma nitridation, and thin amorphous Si passivation layers. We have utilized Hf oxide grown by a previously reported ALD process (5) as the High K dielectric for our devices, and TiN as the metal gate. Our results show that Ge channel devices can be fabricated on 300mm Si substrates using Si VLSI-compatible toolsets and infrastructure and resulting in reasonable device characteristics, Fig. 3. Thus, Ge channel MOSFETs are found to be a promising technology for use in HVM at future VLSI technology nodes. References 1. S. Swaminathan, Y. Oshima, M. Kelly, P.C. McIntyre, Appl. Phys. Lett., 95, 032907 (2009). 2. L. Zhang, M. Gunji, S. Thombare, P.C. McIntyre, IEEE Electr. Device. L., 34, 736 (2013). 3. T. Hamelin, J. Wallace, and A. LaFlamme, U.S. Patent No. 7029536. 4. T. Sugawara, S. Matsuyama, M. Sasaki, T. Nakanishi, S. Murakawa, J. Katsuki, S. Ozaki, Y. Tada, T. Ohta, N. Yamamoto, Jpn. J. Appl. Phys., 44, 1232 (2005). 5. R.D. Clark, S. Consiglio, C. Wajda, G. Leusink, T. Sugawara, H. Nakabayashi, H. Jagannathan, L.F. Edge, P. Jamison, V. Paruchuri, R. Iijima, M. Takayanagi, B. Linder, J. Bruley, M. Copel, V. Narayanan, ECS Trans. 16, 4, 291 (2008)

We have recently reported electrical performance improvements in atomic layer deposited (ALD) HfO2 films grown by use of a cyclical deposition and annealing scheme (termed DADA) compared to a single deposition followed by a post-deposition anneal (PDA). We previously proposed a model for bottom-up crystallization in DADA films in contrast to random crystallization for PDA films. To elucidate the mechanisms for this structural modification, in this study we utilized grazing incidence in-plane X-ray diffraction and pole figure measurements using synchrotron radiation as well as transmission electron microscopy. Structural differences were investigated from different annealing conditions as well as from different thickness of films. We observed significant differences in structural properties of DADA films compared to films receiving PDA. We also report on the evolution of monoclinic HfO2 with a (-111) preferred orientation (fiber texture) for DADA films whereas PDA treatment resulted in a random grain alignment and mixed phase structure.

With the replacement of SiO2 by high-k Hf-based dielectrics in complementary metal–oxide–semiconductor technology, the measurement of the high-k oxide bandgap is a high priority. Spectroscopic ellipsometry (SE) is one of the methods to measure the bandgap, but it is prone to ambiguity because there are several methods that can be used to extract a bandgap value. This paper describes seven methods of determining the bandgap of HfO2 using SE. Five of these methods are based on direct data inversion (point-by-point fitting) combined with a linear extrapolation, while two of the methods involve a dispersion model-based bandgap extraction. The authors performed all of these methods on a single set of data from a 40 A HfO2 film, as well as on data from 20 and 30 A HfO2 films. It was observed that the bandgap values for the 40 A film vary by 0.69 eV. In comparing these methods, the reasons for this variation are discussed. The authors also observed that, for each of these methods, there was a trend of increasing...

In this work we present physical and electrical characterization of HfO2 films deposited using the Dep-Anneal-Dep-Anneal (DADA) deposition scheme. Electrical results from MOSCAP devices fabricated using a low temperature (Gate Last-like) integration flow are presented. In addition we report detailed physical analyses of the films and changes in the films versus as-deposited ALD HfO2 and films undergoing a single post-deposition anneal and show the correlation between observed physical changes in the film and electrical results. Observed physical changes using HR-RBS, HR-TEM, SIMS, XPS and XRR include crystallization, densification, Si intermixing, reduction of in-film carbon and improved etch resistance leading to improved leakage vs. EOT and electrical non-uniformity. Dependence of these changes on the underlying interface layer (e.g. SiO2 vs SiON) is also described.

This paper presents the optimization of HfO2 high-κ gate dielectrics by utilizing cyclic depositions and anneals during atomic layer deposition (ALD). An order of magnitude reduction in gate leakage is obtained by tuning the anneal temperature, duration and sequence in the ALD. The films are also seen to have three to four times reduction in carbon content. These optimized films are moreover observed to be densified without compromising equivalent oxide thickness (EOT), carrier mobility and threshold voltage. Further electrical characterization supports that there is a suppression of trap assisted tunneling with the optimized ALD process by revealing a stronger temperature dependence on the annealed samples as opposed to the conventional ALD process.

In this work, we present a study of the growth and electrical characteristics of metalorganic atomic layer deposited (MO-ALD) HfO2 films deposited using a 300 mm Counter-Flow ALD platform. HfO2 films were deposited over a large range of process temperatures, and flow rates in order to fully characterize the MOALD process window. The HfO2 films were characterized using AFM, HRTEM, MEIS, and SIMS. Saturation curves were generated for precursor and ozone oxidant over a 150 ºC process temperature window, using two different flow rates of Hf precursor. The use of water versus ozone as an oxidant was also investigated. Since all depositions take place above the decomposition temperature of the precursor, it is critical to understand and control the rate of thermal decomposition or parasitic CVD in the process in order to realize good uniformity in a traveling wave-type system. Thus, we have measured the rate of thermal CVD over the full range of temperatures. The thermal CVD rate shows a concave Arrhenius behavior as the process rises in temperature and transitions from an ALD dominated growth mechanism to a CVD dominated mechanism. We propose a possible explanation for this behavior. In addition to the growth characteristics, we have investigated the electrical properties of the as-deposited films using in-line Quantox measurements, and gate stack structures using integrated devices. The relationship between process and electrical characteristics will be discussed.

Because of the disadvantages of the Dubowitz score in very ill preterms, an alternative score based on 7 morphological items was designed, and the results are compared to those of the Dubowitz score in 229 newborns. This scoring system proved to be reliable and easy to perform; standard deviation was +/- 10.2 days versus 9.7 days for the Dubowitz score.