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In recent years, DPDK (Data Plane Development Kit, a data plane development tool set provided by Intel, focusing on high-performance processing of data packets in network applications), one of the high-performance packet I/O frameworks, is widely used to improve the efficiency of data transmission in the cluster. But, the busy polling used in DPDK will not only waste a lot of CPU cycles and cause certain power consumption, but also the high CPU usage will have a great impact on the performance of other applications in the host. Although some technologies, such as DVFS (dynamic voltage and frequency scaling, which is to dynamically adjust the operating frequency and voltage of the chip according to the different needs of the computing power of the application running on the chip, so as to achieve the purpose of energy saving) and LPI (low power idle, a technology that saves power by turning off the power of certain supporting circuits when the CPU core is idle), can reduce power consumption by adjusting CPU voltage and frequency, they can also cause performance degradation in other applications. Using thread sleep technology is a promising method to reduce the CPU usage and power consumption. However, it is challenging because the appropriate thread sleep duration cannot be obtained accurately. In this paper, we propose a model that finds the optimal thread sleep duration to solve the above challenges. From the model, we can balance the thread CPU usage and transmission efficiency to obtain the optimal sleep duration called the transmission performance threshold. Experiments show that the proposed models can significantly reduce the thread CPU usage. Generally, while the communication performance is slightly reduced, the CPU utilization is reduced by about 80%.

Recently, high performance packet I/O frameworks continue to flourish for their ability to process packets from high-speed links. To achieve high throughput and low latency, high performance packet I/O frameworks usually employ busy polling. As busy polling will burn all CPU cycles even if there's no packet to process, these frameworks are quite power inefficient. However, exploiting power management techniques such as DVFS and LPI in the frameworks is challenging, because neither the OS nor the frameworks can provide information (e.g., actual CPU utilization, available idle period, or the target frequency) required by these techniques. In this article, we establish a model that can formulate the packet processing flow of high performance packet I/O to help and address the above challenges. From the model, we can deduce the information needed for power management techniques, and gain the insights to balance the power and latency. After suggesting to use pause instruction to reduce CPU power within short idle period, we propose two approaches to conduct power conservation for high performance packet I/O: one with the aid of traffic information and the other without. Experiments with Intel DPDK show that both approaches can achieve significant power reduction with little latency increase.

Performance interference between QoS and best-effort applications is getting more aggravated as data-intensive applications are rapidly and widely spreading in recently emerging computing systems. While the completely fair scheduler (CFS) of the Linux kernel has been extensively used to support performance isolation in a multitasking environment, it falls short of addressing memory-related interference due to memory access contention and insufficient cache coverage. Though quite a few memory-aware performance isolation mechanisms have been proposed in the literature, many of them rely on hardware-based solutions, inflexible resource management or ineffective execution throttling, which makes it difficult for them to be used in widely deployed operating systems like Linux running on a COTS SoC platform. We propose a memory-aware fair-share scheduling algorithm that can make QoS applications less susceptible to memory-related interference from other co-running applications. Our algorithm carefully separates the genuine memory-related stall from a running task’s CPU cycles and compensates the task for the memory-related interference so that the task gets the desired share of CPU before it is too late. The proposed approach is adaptive, effective and efficient in the sense that it does not rely on any static allocation or partitioning of memory hardware resources and improves the performance of QoS applications with only a negligible runtime overhead. Moreover, it is a software-only solution that can be easily integrated into the kernel scheduler with only minimal modification to the kernel. We implement our algorithm into the CFS of Linux and name the end result mCFS. We show the utility and effectiveness of the approach via extensive experiments.

Software-defined networking (SDN) is an emerging trend where the control plane and the data plane are separated from each other, culminating in effective bandwidth utilization. This separation also allows multi-vendor interoperability. Link failure is a major problem in networking and must be detected as soon as possible because when a link fails the path becomes congested and packet loss occurs, delaying the delivery of packets to the destination. Backup paths must be configured immediately when a failure is detected in the network to speed up packet delivery, avoid congestion and packet loss and provide faster convergence. Various SDN segment protection algorithms that efficiently reduce CPU cycles and flow table entries exist, but each has drawbacks. An independent transient plane technique can be used to reduce packet loss but is not as efficient when multiple flows try to share the same link. The proposed work focuses on reducing congestion, providing faster convergence with minimal packet loss and effectively utilizing link bandwidth using bandwidth-sharing techniques. An analysis and related studies show that this method performs better and offers a more reliable network without loss, while simultaneously ensuring the swift delivery of data packets toward the destination without congestion, compared to the other existing schemes.

Improvements in semiconductor technology enabled smaller feature sizes, better clock speeds, and high performance. Improvements in computer architectures were enabled by RISC architectures and efficient high-level language compilers. Together, we have enabled customized computer architectures from system-on-hips to powerful GPUs and high-performance processors. Users need that the CPU should be able to access unlimited amounts of memory with low latency. The cost of fast memory is multi-fold compared to lower speed memory. Another characteristic of CPU memory access is principle of spatial and temporal locality. The solution is to organize the memory into hierarchy by caching data at different levels. Section 12.3 covers cache basics in detail. All the memory addressable by CPU need not be in physical memory due to space and cost. It can reside in disk. The address range is mapped by virtual memory manager. Virtual address constitutes the page number and the offset within the page. This page is placed in the physical memory in the free page slot available. This is indexed in the page table. Thus, virtual memory is mapped into physical memory. Section 12.4 details the virtual memory management in detail. RISC stands for Reduced Instruction Set Computer. The clock per instruction (CPI) is one in RISC. This architecture uses optimized set of instructions executed in one cycle. This allows pipelining by which multiple instructions can be executed simultaneously in different stages. RISC has several registers; instruction decoding is simple and simple addressing modes. Section 12.5 explains RISC architectures in detail. An efficient implementation of instruction execution is to overlap the instruction executions by which each hardware unit is busy all the time. Section 12.6 explains in detail this concept of pipelining and hazards are controlled in the architecture. Several advances in pipelining architecture have been developed. But the performance improvements get saturated with new constraints and issues in implementation. When a single instruction operates on multiple data elements in a single instruction cycle, the instructions are called Single Instruction Multiple Data (SIMD) instructions. Section 12.7 introduces data-level parallelism with vector processing. Section 12.9 introduces Single instruction Multi-threading (SIMT) in GPUs. We can exploit certain type of programs where they are inherently parallel and have very little dependence. We call them as threads of execution. Thread-Level Parallelism (TLP) is explained in detail in Sect. 12.10. FPGA-based technology has made system-on-chip designs a cake’s walk. Systems with high-performance requirements are possible with hardware configured to such requirements. Temporal re-configuration in FPGAs mimicking DLLs in software has made re-use of same FPGA fabric for just-in-time “use and throw” hardware blocks. Section 12.11 covers reconfigurable computing in detail. After reading this chapter, readers will be able to understand internal architecture of any processor which helps in selecting a processor for individual requirement.

A Bloatware is software that offers limited functionality at the expense of RAM and CPU cycles. The proliferation of bloatware in Android devices depletes not only hardware resources but also makes them more vulnerable to security and privacy threats. A consumer pays in terms of battery, wasted space, privacy and security compromises. These applications have also been known to be used for computer control and data collection. This, however, has some disadvantages. These bloatwares are often mounted in the device partition, making it difficult to remove them without root access. Each app that has been uninstalled can be reinstalled using the same program. The existing methods of rooting the device is complex and may render the device inoperable if not done cautiously. The proposed “Android Debloater and Optimizer” uninstall such bloatware without the risk of rooting your device.

This paper presents FALTCON that enhances the control path for repeated TCP connections. First, we measure and find that the control path of TCP stack consumes as many CPU cycles as that of the data path, which brings up the importance of optimizing the control path. Yet, to the best of our knowledge, there has been little research effort on investigating the control path. Also, we observe that a significant portion of TCP traffic (e.g., HTTP) is not only short-lived but also repeated for a server and client pair. We design FALTCON to take advantage of the property of being repeated. Specifically, FALTCON re-designs the control path to remove the duplicate allocation of the structures and redundant operations over them. FALTCON is implemented in Linux 5.1 that has the latest and highly efficient networking stack. Furthermore, we optimize FALTCON to be lockless entirely and to work per-core. The experiment results show that FALTCON achieves a higher number of connections than Linux, up to 19%, and with much less CPU cycles up to 31%.

The sixth generation wireless communication networks (6G) are anticipated to bring a disruptive innovation on multiple scenarios, where deep edge networks (DENs) turn into a vital network structure on vertical industrial paradigms, including the combination of communication, computing and caching (3C). In this paper, we present the DENs scene to facilitate the deep convergence of computing and communication resources. More specifically, we formulate the optimization problem in terms of energy consumption and latency in order to minimize the total agents overhead. At the same time, for the sake of executing tasks and alleviating interference among different edge networks and high-dynamic network environments, we propose a CPU cycle frequency aided multi-agent deep deterministic policy gradient (C-MADDPG) algorithm framework to optimize the task scheduling, transmission power, CPU cycle frequency and mutual interference from multiple channels to obtain the optimal overhead. Finally, extensive simulation and experimental results demonstrate that our proposed C-MADDPG algorithm has better performance gain in term of execution overhead for different network parameters.

In many control domains (plant control, air traffic control, military command and control) humans are assisted by computer systems during their assessment of the situation and their subsequent decision making. As computer power increases and novel algorithms are being developed, machines move slowly towards capabilities similar to humans, leading in turn to an increased level of control being delegated to them. This technological push has led to innovative but at the same time complex systems enabling humans to work more efficiently and/or effectively. However, in these complex and information-rich environments, task demands can still exceed the cognitive resources of humans, leading to a state of overload due to fluctuations in tasks and the environment. Such a state is characterized by excessive demands on human cognitive capabilities resulting in lowered efficiency, effectiveness, and/or satisfaction. More specifically, we focus on the human-machine adaptive process that attempts to cope with varying task and environmental demands. In the research field of adaptive control an adaptive controller is a controller with adjustable parameters and a mechanism for adjusting the parameters (Astrom & Wittenmark, 1994, p. 1) as the parameters of the system being controlled are slowly time-varying or uncertain. The classic example concerns an airplane where the mass decreases slowly during flight as fuel is being consumed. More specifically, the controller being adjusted is the process that regulates the fuel intake resulting in thrust as output. The parameters of this process are adjusted as the airplane mass decreases resulting in less fuel being injected to yield the same speed. In a similar fashion a human-machine ensemble can be considered an adaptive controller. In this case, human cognition is a slowly time-varying parameter, the adjustable parameters are the task sets that can be varied between human and machine, and the control mechanism is an algorithm that ‘has insight’ in the workload of the human operator (i.e., an algoritm that monitors human workload). Human performance is reasonably optimal when the human has a workload that falls within certain margins; severe performance reductions result from a workload that is either too high or (maybe surprisingly) too low. Consider a situation where the human-machine ensemble works in cooperation in order to control a process or situation. Both the human and the machine cycle through an information processing loop, collecting data, interpreting the situation, deciding on actions to achieve one or more stated goals and acting on the decisions (see for example Coram, 2002

CPUs routinely offload to NICs network-related processing tasks like packet segmentation and checksum. NIC offloads are advantageous because they free valuable CPU cycles. But their applicability is typically limited to layer≤4 protocols (TCP and lower), and they are inapplicable to layer-5 protocols (L5Ps) that are built on top of TCP. This limitation is caused by a misfeature we call ”offload dependence,” which dictates that L5P offloading additionally requires offloading the underlying layer≤4 protocols and related functionality: TCP, IP, firewall, etc. The dependence of L5P offloading hinders innovation, because it implies hard-wiring the complicated, ever-changing implementation of the lower-level protocols. We propose ”autonomous NIC offloads,” which eliminate offload dependence. Autonomous offloads provide a lightweight software-device architecture that accelerates L5Ps without having to migrate the entire layer≤4 TCP/IP stack into the NIC. A main challenge that autonomous offloads address is coping with out-of-sequence packets. We implement autonomous offloads for two L5Ps: (i) NVMe-over-TCP zero-copy and CRC computation, and (ii) https authentication, encryption, and decryption. Our autonomous offloads increase throughput by up to 3.3x, and they deliver CPU consumption and latency that are as low as 0.4x and 0.7x, respectively. Their implementation is already upstreamed in the Linux kernel, and they will be supported in the next-generation of Mellanox NICs.

Internet of Things (IoT) has become a part of our daily life; these provide information like sensory data which could help us in driving a vehicle with ease, electricity management in homes, health care, and many more. In all the scenarios, the information is generally in the form of log data used to measure certain parameters to figure out the solutions matching to the applications. As this information is very sensitive, there are chances of capturing the device and tampering the data causing sever performance degradation of the network. The possibility of attacks on these devices is mainly of two types one is of physical attack which could occur due to accidents and intentional damage to the device and the second type of possible attack is cyber-attack like tampering the information, denial-of-service, and compromising the device. In this paper, we propose a Power Trust mechanism to assign trust value for each node of the network based on the energy auditing. This energy auditing is done with reference to CPU cycles, data received, data processed, data sent network performance, and power consumption. Using the energy auditing model, we calculate trust values of every node present in the network dynamically and predict the physical attacks and cyber-attacks. With the method introduced, IoT devices would be better monitored and secured.

Wearable Internet of Things (IoT) devices are getting ubiquitous for continuous physiological data acquisition and health monitoring. This paper investigates an electrocardiogram (ECG) based biometric user authentication technique for IoT edge devices. A convolutional neural network (CNN) based deep learning technique for user authentication is proposed. The proposed technique achieves an authentication accuracy of 99.63% when tested with 290 subjects from Physionet PTB ECG database. To limit the complexity of the technique for IoT edge nodes, we applied optimisation techniques such as binarisation and approximation of the CNN weights. Accuracy-vs-time-complexity trade-off analysis is performed and results are presented for different optimisations. Our evaluations shows that the complexity-optimised method achieves 98.88% authentication accuracy with acceptable CPU cycles consumed.

To curb redundant power consumption in portable embedded and real-time applications, processors are equipped with various Dynamic Voltage and Frequency Scaling (DVFS) techniques. The accuracy of the prediction of the operating frequency of any such technique determines how power-efficient it makes a processor for a variety of programs and users. But, in the recent techniques, the focus has been too much on saving power, thus, ignoring the user-satisfaction metric, i.e. performance. The DVFS technique used to save power, in turn, introduces unwanted latency due to the high complexity of the algorithm. Also, many of the modern DVFS techniques provide feedback manually triggered by the user to change the frequency to conserve energy efficiently, thus, further increasing the reaction time. In this paper, we imple- ment a novel Artificial Neural Networks-driven frequency scaling methodology, which makes it possible to save power and boost performance at the same time, implicitly i.e. without any feedback from the user. Also, to make the system more inclusive concerning the kinds of processes run on it, we trained the ANN not only for CPU-intensive programs but also on the ones that are more memory-bound, i.e. which have frequent memory accesses during its average CPU cycle. The proposed technique has been evaluated on Intel i7-4720HQ Haswell processor and has shown performance boost by up to 20%, SoC power savings up to 16%, and Performance per Watt improvement by up to 30%, as compared to the existing DVFS technique. An open-source memory-intensive benchmark kit called Mibench was used to verify the utility of the suggested technique.

Optimizing the size and location of storage buffer between machines is critical issues in designing efficient production automation line. The objective of the study is to propose the optimal design of the initial buffer size as well as the suitable machine cycle time to increase the efficiency of the automation line. In this study, the production system consists of three machines with two buffers are placed between them is considered. There is a regular downtime for maintenance at the second machine, which results in lower production efficiency. The production simulation on cloud is used for modelling and demonstrating the concept. The experimental results revealed the proposed optimal initial buffer and the proposed cycle time of maintenance station could yield the maximum production line efficiency.

With the introduction of ultra-low latency SSDs, which complete I/O operations in a few microseconds, the use of polling is becoming an attractive solution for alleviating the overheads in interrupt-driven I/O completion. However, careful use of polling is essential because of its inherent CPU overhead. Hybrid polling, in which a timer-based sleep is inserted in the middle of polling, has recently been proposed to relieve the CPU overhead. However, there is still substantial headroom for further optimization to save CPU cycles. In this paper, we propose efficient hybrid polling scheme that minimizes the CPU cycles for polling without sacrificing the I/O latency. By considering I/O time characteristics of idle and busy storage devices, our scheme makes an appropriate sleep time decision that maximizes the I/O performance and minimizes the CPU cycles for polling. The proposed scheme is implemented in the Linux kernel and evaluated with various I/O workloads. The evaluation results show that whenever an SSD is heavily or lightly loaded, our scheme achieves I/O latency identical to that of classical polling while maintaining a low CPU utilization. Compared to the original hybrid polling, our scheme reduces CPU utilization by 5%–40% and provides faster I/O latency by up to 10%.

In times of cloud services and IoT, network protocol processing is a big part of the CPU utilization today. Foong et al. proposed the rule of thumb for TCP, that a single-core CPU needs about 1 Hz clock frequency to produce 1 bit/s worth of TCP data packets. Unfortunately, CPU speed has stagnated around 5 GHz in recent years resulting in a upper limit of 5 GBit/s throughput with single-threaded network processing. Further, CPUs featuring such high clock rates (e.g., Intel Core i7-8086K) have rated TDP around 95 W, resulting in very high power consumption for high throughput situations. Meanwhile, industry offers some hardware acceleration for TCP as part of their server network cards, to relief the server CPUs and increase the energy efficiency. However this is just a small support as state and management still needs the CPU of the host system. In this paper, we present an approach based on field pro- grammable gate arrays (FPGA) to not only free up CPU cycles but provide a scaleable and energy efficient concept to fully utilize high-speed network interfaces, while maintaining the flexibility of software solutions. For our evaluation, we utilized the NetFPGA Sume, proofing to achieve the linerate of connected SFP+ ports while power consumption stays below 6 W. By leveraging network protocol virtualization, the hardware acceleration approach is not only deployable but stays flexible enough to adapt new networking paradigms quickly.

We propose a server-based approach to manage a general-purpose graphics processing unit (GPU) in a predictable and efficient manner. Our proposed approach introduces a GPU server that is a dedicated task to handle GPU requests from other tasks on their behalf. The GPU server ensures bounded time to access the GPU, and allows other tasks to suspend during their GPU computation to save CPU cycles. By doing so, we address the two major limitations of the existing real-time synchronization-based GPU management approach: busy waiting within critical sections and long priority inversion. We have implemented a prototype of the server-based approach on a real embedded platform. This case study demonstrates the practicality and effectiveness of the server-based approach. Experimental results indicate that the server-based approach yields significant improvements in task schedulability over the existing synchronization-based approach in most practical settings. Although we focus on a GPU in this paper, the server-based approach can also be used for other types of computational accelerators.

Many modern embedded CPUs adopt Non-Coherent DMA (NC-DMA) over Coherent DMA (C-DMA) because of simplicity. An NC-DMA design, however, requires a CPU device driver to explicitly invalidate or flush a wide range of cache space. When an I/O DMA device writes data to a main memory region, the CPU needs to invalidate the cache space corresponding to the same memory region twice: (1) to prevent dirty cache lines from overwriting the DMA data and (2) to remove any cache lines prefetched before the DMA is done. In this work, we first show that such explicit invalidations consume 31 percent of CPU cycles, limiting the data transfer throughput of a high-speed network interface card (NIC) when receiving network packets. Second, we propose a Semi-Coherent DMA (SC-DMA) architecture for improving the efficiency of NC-DMA with a slight modification to the hardware. Specifically, our SC-DMA records the DMA region and prohibits any data that is prefetched from the region from entering the cache, reducing nearly 50 percent of the unnecessary invalidations. Lastly, we identify several software optimizations that can substantially reduce excessive cache invalidations prevalent in NIC drivers. Our evaluation with NVIDIA Jetson TX2 shows that our proposed SC-DMA design with the NIC driver optimizations can improve the NIC data transfer throughput by up to 53.3 percent.

The explosive growth of data brings new challenges to the data storage and management in cloud environment. These data usually have to be processed in a timely fashion in the cloud. Thus, any increased latency may cause a massive loss to the enterprises. Similarity detection plays a very important role in data management. Many typical algorithms such as Shingle, Simhash, Traits and Traditional Sampling Algorithm (TSA) are extensively used. The Shingle, Simhash and Traits algorithms read entire source file to calculate the corresponding similarity characteristic value, thus requiring lots of CPU cycles and memory space and incurring tremendous disk accesses. In addition, the overhead increases with the growth of data set volume and results in a long delay. Instead of reading entire file, TSA samples some data blocks to calculate the fingerprints as similarity characteristics value. The overhead of TSA is fixed and negligible. However, a slight modification of source files will trigger the bit positions of file content shifting. Therefore, a failure of similarity identification is inevitable due to the slight modifications. This paper proposes an Enhanced Position-Aware Sampling algorithm (EPAS) to identify file similarity for the cloud by modulo file length. EPAS concurrently samples data blocks from the head and the tail of the modulated file to avoid the position shift incurred by the modifications. Meanwhile, an improved metric is proposed to measure the similarity between different files and make the possible detection probability close to the actual probability. Furthermore, this paper describes a query algorithm to reduce the time overhead of similarity detection. Our experimental results demonstrate that the EPAS significantly outperforms the existing well known algorithms in terms of time overhead, CPU and memory occupation. Moreover, EPAS makes a more preferable tradeoff between precision and recall than that of other similarity detection algorithms. Therefore, it is an effective approach of similarity identification for the cloud.

Cloud computing can leverage over-provisioned resources that are wasted in traditional data centers hosting production applications by consolidating tasks with lower QoS and SLA requirements. However, the dramatic fluctuation of workloads with lower QoS and SLA requirements may impact the performance of production applications. Frequent task eviction, killing and rescheduling operations also waste CPU cycles and create overhead. This paper aims to schedule hybrid workloads in the cloud data center to reduce task failures and increase resource utilization. The multi-prediction model, including the ARMA model and the feedback based online AR model, is used to predict the current and the future resource availability. Decision to accept or reject a new task is based on the available resources and task properties. Evaluations show that the scheduler can reduce the host overload and failed tasks by nearly 70%, and increase effective resource utilization by more than 65%. The task delay performance degradation is also acceptable.

In many cases industrial companies’ efficiency is limited by bad man-machine collaboration. In the time of intelligent manufacturing, more data can be collected and help companies to improve their efficiency. Therefore, a production line optimization method based on Man-Machine collaboration with the help of big data tools and sensors is introduced. At first, the production line will be analyzed and main data as machine cycle time, personnel operation time, task distribution etc. will be collected. Then based on these data, a simulation model will be made in plant simulation. After that, the performance of the production line will be evaluated considering the man-machine collaboration, work task distribution etc. and the optimization will be made. Afterwords, the machine cycle time, operator motion track and labor operation time in real production situation will be collected to compare and validate the optimization model.

In this work, an experimental and theoretical investigation of a frozen and hot water production unit with direct gas absorption is developed. Water/ammonia couple is used. A particular interest is given to the system performances evaluation such as exergetic efficiency and total exergy loss. Parameters analyzed are coefficients of performance, irreversibility and exergetic efficiency. Results show that the machine can reach a COP up to 65% and exergetic efficiency up to 18% for a working temperature and a condensation temperature of 120 °C and 18 °C, respectively. These performances decrease for a condensation temperature of 37 °C and 47 °C. Indeed, the engine is less efficient and presents more irreversibility, which is major in the pre-absorber and the absorber. An improvement of the machine cycle is proposed, in order to adapt it to low grade heat sources, using a compressor upstream of the pre-absorber. Performances of the new hybrid cycle are better than those of the real cycle.

For modern switches operating with terabit-scale bandwidth it is important to achieve guarantees of highperformance as early as possible in the design and development process. P4 is the state-of-art programming language for defining the control flow of SDN network switches. The most computationally intensive part of the program flow are the lookup tables. Unfortunately, the execution semantics of P4 lookup tables is highly implementation dependent.Continuing our previous work on P4 parsers, we propose, classify, and evaluate implementation-level cost models for P4 programs composed of parser and lookup constructs, enabling developers to estimate program execution costs (with CPU cycle precision) before actually deploying the solution to hardware.

Security, reliability, and efficiency are crucial traits of the microprocessors used for safety and mission critical applications. Conventional microprocessors are typically not suitable for these applications, mainly because these processors do not support architectural-level protection including thread isolation, which in turn could lead to security vulnerabilities in embedded systems. In this case, a single erroneous thread could cause catastrophic failure of the whole system. Also, with conventional microprocessors, no specific defense mechanisms are provided to prevent foreign invaders such as viruses from attacking the system. This could become a significant problem especially for safety and mission critical applications that are typically real-time systems. In this paper, we introduce novel and unique pipeline barrel processor (PBP) architecture for safety and mission critical applications for real-time operating systems. Our PBP microprocessor is designed in such a way to alleviate the aforementioned issues, by comprising following features: fine-grained multi-tasking using single pipeline assembly, dynamic allocation of CPU cycles, memory partitioning at the architectural level, execution code regions at the hardware level, and global variables and stack protections. Experiments are performed to evaluate our PBP microprocessor, and to verify the correctness and functionality of the microprocessor design.

International audience; In hybrid systems on chip (SoC) the algorithms must share limited resources classified as hardware (FPGA logic, memory and DSP blocks) and software (CPU cycle budget). Embedded applications are implemented with concurrent processes, which have to coexist. Therefore, the algorithm performance or precision is often downgraded to fit on a FPGA or to meet timing constraints. One of the solutions to relax these constraints is to reconfigure the SoC according to application requirements observed at runtime. Hardware (HW) reconfiguration can be performed by means of dynamic partial reconfiguration (DPR). Beyond the intrinsic DPR complexity, the most critical aspect is the implementation of the reconfiguration decision. Academic adaptive architectures are usually based on power / performance rules. Nevertheless such solutions are usually application agnostic and so cannot fully exploit the possible adaptation to the environment. So real-life systems require solutions to capture the knowledge of algorithm experts that can be leveraged at runtime to drive the reconfiguration decision according to application scenarios. In this paper we propose a methodology to design a reconfiguration controller based on quality of service (QoS) indicators to be specified by experts. This controller monitors the reconfigurable partitions (RP) and can make DPR decisions to optimize the global QoS. We illustrate our methodology in the Radar domain with a tracking system based on Kalman filters implemented on a Zynq Ultrascale+. This study highlights expected gains and obstacles, it presents the different strategies to cope with the issues and draws perspectives.

Network Function Virtualization (NFV) promises to reduce the capital and operational expenditure for network operators by moving packet processing from purpose-built hardware to software running on commodity servers. However, the state-of-the-art in NFV is merely replacing monolithic hardware with monolithic Virtual Network Functions (VNFs), i.e., software that realizes different network functions. This is a good first step towards deploying NFV, however, common functionality is repeatedly implemented in monolithic VNFs. Repeated execution of such redundant functionality is particularly common when VNFs are chained to realize Service Function Chains (SFCs) and results in wasted infrastructure resources. This stresses the need for re-architecting the NFV ecosystem, through modular VNF design and flexible service composition. From this perspective, we propose MicroNF ( $\mu \mathbf{NF}$ in short), a disaggregated packet processing architecture facilitating the deployment of VNFs and SFCs using reusable and independently deployable components. Experimental results show that compared to monolithic VNF based SFCs, $\mu \mathbf{NF}$ -based ones achieve the same throughput by using less CPU cycles per packet on average.

Service Function Chaining (SFC) is used to steer the traffic to a specific set of Network Functions (NFs) (such as load balancer, proxy, firewall, etc.) based on the type of traffic and operator policy. Handling the massive amount of user traffic envisioned in the next generation networks using traditional techniques is costly and tedious. By leveraging advanced technologies such as Network Functions Virtualization (NFV) and Software Defined Networking (SDN), NFs can be deployed as software instances on Virtual Machines (VMs) (also called as Virtual Network Function (VNF)). Network operators widely place different types of VNFs at different locations to meet the user traffic demands. Multiple VNF instances on the same physical server compete for common resources such as network I/O bandwidth, CPU cycles, cache memory, and main memory which can lead to severe performance interference, which is ignored in existing NF selection mechanisms. However, increasing the SFC acceptance rate of SFC requests with an effective selection of required VNFs under the constraint of end-to-end latency is still an open problem. Since this problem is NP-Hard, we propose a heuristic algorithm based on dynamic programming which efficiently selects the required VNFs and steers the traffic by considering the interference effect. Results show that the proposed algorithm improves the average SFC acceptance rate by 29% as compared with existing methods.

Cryptography is the art of converting readable data into indecipherable format using keys and vice versa. Strength of the algorithm is mainly measured by the complexity and CPU cycles required for cryptanalysis in the algorithm. But in an energy constrained environment like IoT, CPU intense complex algorithms will degrade the efficiency. Light-weight or cut down versions of symmetric and asymmetric cryptographies are found best suited for constrained environments. So accordingly, we in this paper have surveyed a lot of Hardware and software based Light-weight cryptographic algorithms in a quest to find the best suited cryptographic algorithm for signing and hashing blockchain in a constrained environment.

One of the issues with spinlock protocols is excessive spinning which results in a waste of CPU cycles. Some protocols use the hybrid, spin-then-block approach to avoid this problem. In this case, the contending thread may prefer relinquishing the CPU instead of spinning, and resumes execution once notified. This paper presents a machine learning framework for intelligent sleeping and spinning as an alternative to the spin-then-block strategy. This framework can be used to address one of the challenges faced by this strategy: the delay in the critical path. The work suggests a reinforcement learning based approach for queue-based locks that aims at having threads learn to spin or sleep. The challenges of the suggested technique and future work are also discussed.

In recent years, big data applications with scheduling algorithms have evolved lot due to the advancement of new technologies and techniques. We are living in digital data world where the data size is in terms of Exabyte or Pico Byte. This large volume of data is referred as big data. In today’s business environment, the performance of applications largely depends on the efficient retrieval of relevant data on time; the data analysis and retrieval of relevant data need to be done at faster rate. The traditional scheduling algorithms will not be efficient to handle such huge volume of data, considering the above facts managing big data applications and scheduling of big data on distributed architecture has become a challenging research area in the last three–four years. To process such huge volume of data, efficient scheduling algorithms need to be adopted to achieve better performance. The existing MapReduce implementation on Hadoop framework on single node cluster limits themselves to implement all the jobs on single node cluster. In this paper, we will discuss different scheduling techniques and their performance effects on a multimode clusters. The parameters considered for performance evaluation are CPU time, physical memory, and virtual memory. The main aim is to provide survey of different scheduling algorithms that can be used across distributed architecture to achieve better performance in analysis of big data considering YouTube dataset. The results interpret that capacity-based scheduling algorithm is more efficient as compared to FIFO and FAIR in terms of CPU cycles, physical and virtual memory utilization.

Volunteer computing is a distributed computing model in which individuals in possession of computing resources volunteer to provide them to a project. Owing to the availability of billions of computing devices all over the world, volunteer computing can help solve problems that are larger in scale even for supercomputers. However, volunteer computing projects are difficult to launch and deploy. These platforms also force volunteers to trust the authenticity of the project owner and to blindly accept credits allotted to their contribution by the project owner. As a result, very few high-profile trusted projects are able to sustain in this system. In this paper, we present an incentivized web-based volunteer computing platform that functions as a market place to buy and sell computing power. Launching a project on the system and contributing to an existing project happens over the browser without the need for a specialized software or hardware. We introduce the application of blockchain to remove the need to trust any other party in the system. We also present a prototype implementation and solve NP-Problems as examples using the proposed prototype.

We are working in the era of cloud computing, where all of the required resources are available online at pay-par-basis. It made all the IT industry easily accessible to all types of users. It provides the services in software, hardware and in storage terms. We are dealing the model of IAAS which provides on demand secured storage services. A number of researchers has designed and proposed a number of techniques and algorithms for assurance of storage services provided by cloud service providers. Our paper presents a modified approach of integrity verification in multiparty communication in decentralized cloud computing environment. We enhanced the basic model of AES with AES Poly Library 1305 and also redesigned the variant of secret sharing scheme for handling a secured group communication. Our factors for evaluation are the hardness and randomness of key i.e. entropy of the proposed technique and other measurable units which gives the efficiency of communication overhead and security.

Obtaining CPU cycles on an HPC cluster is nowadays relatively simple and sometimes even cheap for academic institutions. However, in most of the cases providers of HPC services would not allow changes on the configuration, implementation of special features or a lower-level control on the computing infrastructure, for example for testing experimental configurations. The variety of use cases proposed by several departments of the University of Torino, including ones from solid-state chemistry, computational biology, genomics and many others, called for different and sometimes conflicting configurations; furthermore, several R&D activities in the field of scientific computing, with topics ranging from GPU acceleration to Cloud Computing technologies, needed a platform to be carried out on. The Open Computing Cluster for Advanced data Manipulation (OCCAM) is a multi-purpose flexible HPC cluster designed and operated by a collaboration between the University of Torino and the Torino branch of the Istituto Nazionale di Fisica Nucleare. It is aimed at providing a flexible and reconfigurable infrastructure to cater to a wide range of different scientific computing needs, as well as a platform for R&D activities on computational technologies themselves. We describe some of the use cases that prompted the design and construction of the system, its architecture and a first characterisation of its performance by some synthetic benchmark tools and a few realistic use-case tests.

In fast-growing computing era, many consumers and small-scale organizations are starving for large computing power to run their applications. Rapidly growing technology and limited time usage, restrict users to invest in possessing their own computing power. Whenever there is a need for executing large applications users are looking for an approach where resources are pooled dynamically and execute the application. Majority of existing resource allocation frameworks are concentrating on resource allocation based on CPU cycles, storage, and memory. It is observed that these resource allocation methods can perform even better when network bandwidth is considered depending on the size of the task and efficient sharing of bandwidth among peer users. In this article, we have proposed a novel approach called Network Attentive Payload Allocation [NAPA] for resource scheduling based on the size of the task and available network bandwidth, considering all the users gets essential network bandwidth. Task are allocated to virtual machines using the payload distribution model. By using this model, we have evaluated the performance of the NAPA in cloud sim by editing the broker datacenter package. Experimental results were compared, and it is observed that after applying NAPA the performance of the model is increased fairly.

Classifying traffic signs is an indispensable part of Advanced Driver Assistant Systems. This strictly requires that the traffic sign classification model accurately classifies the images and consumes as few CPU cycles as possible to immediately release the CPU for other tasks. In this paper, we first propose a new ConvNet architecture. Then, we propose a new method for creating an optimal ensemble of ConvNets with highest possible accuracy and lowest number of ConvNets. Our experiments show that the ensemble of our proposed ConvNets (the ensemble is also constructed using our method) reduces the number of arithmetic operations 88 and $$73\,\%$$73% compared with two state-of-art ensemble of ConvNets. In addition, our ensemble is $$0.1\,\%$$0.1% more accurate than one of the state-of-art ensembles and it is only $$0.04\,\%$$0.04% less accurate than the other state-of-art ensemble when tested on the same dataset. Moreover, ensemble of our compact ConvNets reduces the number of the multiplications 95 and $$88\,\%$$88%, yet, the classification accuracy drops only 0.2 and $$0.4\,\%$$0.4% compared with these two ensembles. Besides, we also evaluate the cross-dataset performance of our ConvNet and analyze its transferability power in different layers. We show that our network is easily scalable to new datasets with much more number of traffic sign classes and it only needs to fine-tune the weights starting from the last convolution layer. We also assess our ConvNet through different visualization techniques. Besides, we propose a new method for finding the minimum additive noise which causes the network to incorrectly classify the image by minimum difference compared with the highest score in the loss vector.

The high number of occupational accidents occurring every year in the industrial sector is still one of the main social policy action areas of governments worldwide. Both technical and human failures are often addressed as the main causes for accidents at work. However, the lack of full hazard prevention effectiveness from currently available Safeguarding Devices is another factor that should be considered, at least, from an engineering viewpoint. This paper presents a recently patented Access Detection and Machine Cycle Tracking System (ADMCTS) for industrial machinery with active safety purposes. Active safety paradigm has greatly succeeded in the automotive sector in the last years, dramatically improving road traffic accident prevention by means of active devices with real-time capabilities. Based on a dedicated Computer Vision System (CVS) for real-time video analysis of a monitored safety zone, the ADMCTS performs three main functions: access and presence detection of objects entering and/or remaining within the monitored zone, machine cycle tracking, and warning and alarm signal handling to ensure that machine functions are only allowed when workplace conditions are safe. Machine cycle tracking provides the ADMCTS with an adaptive risk assessment capability for optimal prevention. In order to provide a thoughtful description of its functionality, a state machine model of the ADMCTS is introduced, and a visual walk-through of this model, as applied on a generic cutting machine, is also discussed.

In virtualized data centers, live virtual machine (VM) migration can increase energy efficiency by consolidating VMs on fewer servers. This problem is usually considered a Bin Packing Problem with server capacity constraints, such as CPU, memory and network bandwidth. In order to minimize the communication traffic within the data center network, existing research works used correlation-based strategy to consolidate VMs onto servers, which means that VMs with inter-traffic are consolidated as closely as possible, e.g. within a server or a rack. However, this strategy increases the traffic load of virtual switches on servers, and it causes a certain number of CPU cycles of servers to move traffic through virtual switches. A lack of consideration for the virtual switching overhead may increase the risk that VMs are not allocated enough resources, and consequently reduce VMs' performance. In this work, we conduct experiments to estimate the virtual switching overhead on server CPU resource, and based on the experiment results, we propose a virtual-switching-aware VM consolidation algorithm to address this problem. Experiments on representative data center workloads show that the overhead can occupy 10-30% of server's CPU resources. Additionally, our algorithm shows a much lower server capacity violation probability as compared with the baseline algorithm. HighlightsWe quantitatively study the virtual switching overhead.The virtual switching overhead occupies 10-30% of server's CPU resources.Simple linear regression can be used to model the virtual switching overhead.The overhead are similar both in the interserver cases and the intra-server cases.We propose a new algorithm to reduce the server capacity violation probability.

This paper validates the on-board applicability of lunar landing Generalized Model Predictive Static Programming (GMPSP) guidance algorithm using processor-in-loop (PIL) simulations. PIL simulations have been extensively used to verify the real time applicability of algorithms by obtaining run-time information and memory consumption. In this paper, two segmented approach is proposed for the powered descent phase of lunar landing to minimize fuel consumption. The GMPSP guidance algorithm is used for both segments of the powered descent phase to generate the admissible guidance law. The on-board applicability and computational efficiency of GMPSP guidance algorithm are demonstrated through PIL simulation results. In PIL simulations, the GMPSP algorithm is coded in C and validated by using the target TMS320C6748 Digital Signal Processor. The results obtained from the target processor gives an insight into the behavior of the algorithm during the actual mission. The convergence time of the GMPSP algorithm is determined from CPU cycles required by the processor for convergence of the algorithm.

The main focus of this paper is a generic approach to enable both single persons and worldwide distributed teams to analyse and enhance manufacturing plants. This paper describes the state of the art, current challenges, our approach to tackle this task, a first implementation of our solution (FADAT) and the test results from at a real industrial plant. The novelties are the combination and synchronisation of different data sources for analysing plans and the implementation of a collaborative working mode without the need for a steady online connection.

Development of fast methods to conduct in silico experiments using computational models of cellular signaling is a promising approach toward advances in personalized medicine. However, software-based cellular network simulation has run-times plagued by wasted CPU cycles and unnecessary processes. Hardware-based simulation affords substantial speedup, but prior attempts at hardware-based biological simulation have been limited in scope and have suffered from inaccuracies due to poor random number generation. In this work, we propose several hardware-based simulation schemes utilizing novel random update index generation techniques for step-based and round-based stochastic simulations of cellular networks. Our results show improved runtimes while maintaining simulation accuracy compared to software implementations.

Recently, high performance packet I/O frameworks are expected an extensive application for their ability to process packets from 10Gbps or higher speed links. To achieve high throughput and low latency, high performance packet I/O frameworks usually employ busy polling technique. As busy polling will burn all CPU cycles even if there's no packet to process, these frameworks are quite power inefficient. Meanwhile, exploiting power management techniques such as DVFS and LPI in high performance packet I/O frameworks is challenging, because neither the OS nor the frameworks can provide information (e.g., the actual CPU utilization, available idle period, or the target frequency) required by power management techniques. In this paper, we establish an analytical model that can formulate the packet processing flow of high performance packet I/O to help address the above challenges. From the analytical model, we can deduce the actual CPU utilization and average idle period in different traffic load, and gain the insight to choose CPU frequency that can appropriately balance the power consumption and packet latency. Then, we propose two simple but effective approaches to conduct power conservation for high performance packet I/O: one with the aid of traffic information and the other without. Experiments with Intel DPDK show that both approaches can achieve significant power reduction (35.90% and 34.43% on average respectively) while incurring

In current NFV ecosystem, most software NFs delivered by NF vendors tend to be monolithic with multiple features. In runtime, an NF is configured with a subset of its features turned on/off. By our code analysis and primary test, we find that some of the (runtime) unused features are executed silently, which wastes CPU cycles and memory. We propose to use program analysis techniques to eliminate runtime redundant logic in NF code so that the NF performance can be accelerated. We prototype our idea and test it on Snort to show the feasibility.

Software-Defined Networking (SDN) has attracted great attention from both academia and industry. However, the deployment of SDN has faced some critical security issues, such as Denial-of-Service (DoS) attacks on the SDN infrastructure. One such DoS attack is the data-to-control plane saturation attack, where an attacker floods a large number of packets to trigger massive table-misses and packet-in messages in the data plane. This attack can exhaust resources of different components of the SDN infrastructure, including TCAM and buffer memory in the data plane, bandwidth of the control channel, and CPU cycles of the controller. In this paper, we analyze the vulnerability of SDN against the data-to-control plane saturation attack extensively and design FloodShield, a comprehensive, deployable and lightweight SDN defense framework to mitigate this dedicated DoS attack. FloodShield combines the following two techniques: 1) source address validation which filters forged packets directly in the data plane, and 2) stateful packet supervision which monitors traffic states of real addresses and performs dynamic countermeasures based on evaluation scores and network resource usages. Implementations and experiments demonstrate that, compared with previous defense frameworks, FloodShield provides effective protection for all three components of the SDN infrastructure – data plane, control channel and control plane – with less resource consumption.

We see an increasing trend in the processing power and storage capacities of mobile phones. Combined with their large numbers and ubiquitous nature, they present new possibilities in the field of public resource computing, also called volunteer computing. An effective volunteer computing solution can be achieved by utilizing the idle CPU cycles and free storage space of these mobile phones. Existing solutions like BOINC cater mainly to large organizations and have complex procedures for submitting datasets and code for computation. Here we propose a novel distributed computing platform which enables the user to harness the public computing power with ease. The user needs to upload a dataset, the Java code that needs to be run on it, and the merge code that combines the results. We have come up with a distribution and scheduling algorithm which leverages the computational heterogeneity of the devices, the complexity of the task involved and the size of the dataset uploaded.The platform also provides a decentralized public storage, using which users can upload any file securely. It uses threshold cryptography on the uploaded files to create encrypted shares. This approach reduces the redundancy required to maintain availability. We have run a DNA sequence similarity algorithm on our system, utilizing a number of Android phones of different makes. Our results show that this approach is a viable, cost-efficient alternative to traditional distributed computing resources for performing non-time bound computations on large datasets.

Redundant array of inexpensive disks (RAID) based storage systems performance is limited to the sequential nature of the central processing unit (CPU), and they consume high amounts of energy because they need erasure coding for striping data and parity into storage devices. This paper proposed an energy-aware GPU based scheduling. The proposed scheduler differs from existing RAID in that it can reduce the number of CPU cycles and coding time. The proposed system generates parity by using a GPU, stripes parity at the initiator server and stripes data at the target server. We also apply an energy-aware scheduling scheme based on solid state disk-based data storage and hard disk drive-based parity storage. Experimental results show that the energy consumption by GPU-RAID is 45% less than Linux-RAID.

CPU cache misses and branch mispredictions waste CPU cycles and affect program performance. Such software inefficiencies could be neither eliminated by existing compilers nor avoided by developers. In this paper, we propose a novel approach, named PERDICE, to automatically discover such performance bugs by leveraging concolic execution. PERDICE adopts a new path exploration algorithm to discover such software inefficiencies. In particular, we measure performance losses in the granularity of program locations (e.g., instructions, source code lines) instead of paths to avoid getting stuck into the code without software inefficiencies. Moreover, when scoring test inputs, our new approach prefers the test inputs incurring increments in performance losses. This strategy allows PERDICE to avoid getting stuck into the software inefficiencies that have been found. We have implemented PERDICE for both PC (X86 instructions) and Android smartphones (ARM instructions). The experimental results with real-world desktop software and Android native code show that PERDICE outperforms the other four popular algorithms and PROFs (a multi-path performance profiler) in terms of the speed to discover software inefficiencies and the severity (i.e, amount of wasted CPU cycles) of inefficiencies.

The number of deployed Internet of Things (IoT) devices has been increasing rapidly, and security has become significantly important in IoT environments. However, security issues remain challenging due to constraints of IoT devices. One critical security issue is that attacks tamper the firmware of IoT devices. Once the firmware is tampered, it is difficult to notice and recover the tampered firmware. For the integrity of firmware, this paper proposes a new blockchain-based firmware verification system, called Chain Veri. We overcome vulnerabilities of previous studies such as fudging firmware verification. Furthermore, unlike previous studies that presented only the concepts and ideas, we implement Chain Veri from scratch and carry out performance evaluation on storage consumption and CPU cycles to run Chain Veri on IoT device. Our results show that only 1.2MB of storage is used to verify 2,845 devices. Also, 1,692 CPU cycles are to generate a palette in ChainVeri.

Embedded devices are gaining popularity day by day due to the expanded use of Internet of Things applications. However, these embedded devices have limited capabilities concerning power and memory. Thus, the applications need to be tailored in such a way to perform the specified tasks within the constrained resources with the same accuracy. In Real-Time task scheduling, one of the challenging factors is the intelligent modelling of input tasks in such a way that it produces not only logically correct output within the deadline but also consumes minimum CPU power. Algorithms like Rate Monotonic and Earliest Deadline First compute hyper-period of input tasks for periodic repetition of the same set of tasks on CPU. However, at times when the tasks are not adequately modelled, they lead to an enormously high value of hyper-period which result in more CPU cycles and power consumption. Many state-of-the-art solutions are presented in this regard, but the main problem is that they limit tasks from having all possible period values, however, with the vision of Industry 4.0, where most of the tasks will be doing some critical manufacturing activities, it is highly discouraged to prevent them of a certain period. In this paper, we present a resource-aware approach to minimise the hyper-period of input tasks based on device profiles and allows tasks of every possible period value to admit. The proposed work is compared with similar existing techniques, and results indicate significant improvements regarding power consumptions.

This paper proposes the implementation of a multi-objective genetic algorithm (MOGA) on a low-end microcontroller, applying benchmark functions to evaluate its performance. A general-purpose microprocessor implementation of the same algorithm was used to compare CPU cycles spent for each generation on both platforms. The results show that although the microcontroller is slower than the microprocessor, it is fast enough to be used for solving optimization problems, and has lower cost and lower power consumption than the microprocessor platform.

We applied machine learning to detect changes in state of key registers in digital devices from their analog RF emissions. As digital devices operate, they emit information via analog side channels. We collected the RF side channel with a 500-MHz shielded loop probe from Riscure, placed in the nearfield (