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Code-domain signal processing techniques implemented at radio frequencies (RFs) enable simultaneous transmit and receive (STAR) applications. With direct sequence spread spectrum (DSSS) techniques and RF correlators, transmit (TX) self-interference (SI) is separated from the receive (RX) signal at the antenna interface for STAR. The processing gain inherent in the code-domain approach increases the TX SI rejection in the RF domain to relax filtering and linearity requirements of the RX. A code-domain RX demonstrates 52 dB of TX SI rejection with TX code-notch and RX code-pass filters operating at the same center frequency. The RX is tunable from 0.25 to 1.25 GHz and has a gain of 39 dB at 1 GHz while consuming 90 mW of which 40 mW are consumed in the front-end filters. The RX is implemented in a 45-nm CMOS SOI process and full-duplex operation is verified through an over-the-air demonstration.

A code-domain transceiver front end that incorporates a transmit modulator and a receive (RX) RF signal correlator is presented. An integrate-and-dump $N$ -path filter improves rejection by 8 dB. We propose an RF chopper switch with 12.1-/23.1-dBm P1dB/IIP3 for both RF correlation and filtering that rejects TX self-interference by 49.5 dB. Walsh and Barker codes are generated with fine and coarse tuning for synchronization. The RX power consumption is 18 mW, including dynamic power (1-V supply) and four analog amplifiers (1.5 V) at the operating frequency of 1 GHz and the code rate of 200 megachip-per-second (Mc/s). The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Mc/s. Over the air testing demonstrates synchronization with Barker codes.

This article demonstrates a signal processing technique for receiving non-contiguous RF channels by concurrently mixing several RF bands to adjacent IF channels. Consequently, channel selection does not require local oscillator tuning and the proposed receiver (RX) can switch channels in less than 25 ns. The RX chip operates over a frequency range of 100 MHz–1.4 GHz and demonstrates an out-of-band rejection of 49 dB and a measured RX sensitivity of −86 dBm, which is the lowest measured for $N$ -path-based RXs. The chip was fabricated in a 45-nm RF silicon-on-insulator (SOI) CMOS process and occupies an active area of 0.55 mm2 with the power consumption of 23.1 mW when operating at 1 GHz. The chip performance is verified with over-the-air measurement of two transmitted signals 80 MHz apart that are received simultaneously with a 10-MHz analog-to-digital converter (ADC) at an error vector magnitude (EVM) around −20 dB. The measured dynamic range for EVM less than −20 dB is better than 86 dB for a QPSK constellation.

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch.

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ( $\lambda /4$ ) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes.

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance.

This paper demonstrates a code-domain transceiver that incorporates a transmit (TX) modulator and receive (RX) RF signal correlator. We propose a transmission gate switch with 12.1-dBm/23.1-dBm P1dB/IIP3 for both RF correlation and filtering and rejects TX self-interference by 49.5 dB. An integrate-and-dump N-path filter improves rejection by 8 dB. The RX power consumption is 18 mW at 1 GHz. The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Megachip-per-second (Mc/s). Over the air testing demonstrates synchronization with Barker codes.

This work reports a high-power modulator implemented in 45-nm CMOS SOI for signal processing after the power amplifier. Two stacked switch variations, a 12 stack and 8 stack, were designed in 45-nm SOI CMOS and tested for trade-offs in insertion loss and power handling. These switches use a novel tapering technique to significantly improve switch linearity. The modulators have P 1dB values between 34 dBm and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1 GHz carrier. The IIP3 is between 46 dBm and 61 dBm.

This paper reports a Watt-level power handling modulator using a stacked-FET switch for signal processing at the antenna. Two design approaches are compared in this paper: a resistive gate termination and an inductive gate termination. The stacked switches are implemented in 45-nm CMOS SOI. Measured performance of these stacked switches shows the benefit of an inductive termination: power handling capabilities of $> 30\ \mathbf{dBm}$ with modulation speeds of up to 300 MHz. The IIP3 is demonstrated to exceed 45 dBm.