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In this paper, we propose an Interleave-Division Multiple Access (IDMA) based uplink multi-user system fornext generation WLAN. By minimizing the latency throughaccurate detection per iteration, we were able to design a receiver architecture that meets the latency demands of current IEEE802.11 WLAN. To do this, the proposed system utilizes a novel algorithm for simplified LLR calculation of the soft input soft output demapper needed in the IDMA first stage detection.The proposed system has a maximum of 34.8 bits/s/Hz spectral efficiency for a single spatial stream and can support up to 8 users in a single 20MHz channel. We compare the proposed system to a reference OFDMA system and show its advantages in terms of diversity, flexibility and BER performance. Keywords: 802.11ax; IDMA; uplink multi-user access

With increased awareness among consumers regarding food safety and security, food allergen control has become an indispensable requirement in the food industry. Although several methods for detecting allergens in food products are available, highly sensitive techniques are required. In this study, we developed a technique named as peptide array-based inhibition enzyme-linked immunosorbent assay (ELISA), Pep-iEIA, for evaluating antigenicity and detecting cow's milk antigen in infant formula products, using a peptide array consisting of a series of overlapping peptides found in allergenic milk proteins. Pep-iEIA was used to examine five cow's milk-based infant formulas with different degrees of hydrolyzation, and the assay offered both more sensitive detection and detailed analysis of remaining antigenic peptides in allergen compared to conventional ELISA. The antigenicity level of the allergenic peptides identified using Pep-iEIA was confirmed by surface plasmon resonance assay. We believe that Pep-iEIA will be highly useful for antigenicity evaluation of dairy products consumed by infants and patients with cow's milk allergy.

The demand for high-resolution wireless video transmission technology is expected to increase greatly as the video resolution increases, and as the Wi-Fi devices spread. Wireless transmission of high-resolution video requires high throughput, therefore it is necessary to use a multiple-input multiple-output (MIMO) system. In this paper, we propose an evaluation platform for video transmission method based on joint source-channel coding (JSCC) that suppresses the degradation of received video by combining source coding and precoding, and efficient hardware software co-design for implementing it on hardware such as field-programmable gate array (FPGA) board. As a result of simulation, beamforming based on eigenbeam-space division multiplexing (E-SDM), one of the precoding method, is performed and the effectiveness of the proposed method has been confirmed.

With the spread of mobile devices, image and video transmission is in great demand. The use of multiuser multiple-input multiple-output (MU-MIMO) systems, where multiple data can be sent to multiple users, is highly expected. This paper proposes a novel power allocation scheme for MU-MIMO systems, which minimizes the variance of channel capacities of each spatial stream of all users to achieve user fairness in terms of video quality. In addition to the user fairness, we make the spatial streams which convey visually more important information be high-quality for achieving high video quality. Simulation results show that the proposed power allocation enables to equalize video quality even if the distances between a transmitter and users are different.

Non-orthogonal multiple access (NOMA) is a promising candidate for the future fifth generation systems because of its ability to provide greater spectral efficiency. Interleave division multiple access (IDMA) is one of the NOMA techniques that can support multiple access for a large number of users in the same bandwidth. One of the problems in the hardware implementation of IDMA is its high latency due to iterative processing. In this paper, we propose a novel architecture for the IDMA receiver with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially handles deinterleaving, despreading, spreading, and interleaving for multi-user detection. The proposed architecture which we call interleaved domain multi-user detection can perform multi-user detection directly without deinterleaving the received frame in the interference canceller iteration resulting in the decrease of latency by almost half. We also describe the memory design which is able to implement the proposed architecture. The results show that due to the reduction of the latency by half, the throughput can be increased by twice compared with the conventional architecture. VLSI implementation results show that the proposed architecture has reduced circuit area and power consumption by 53% and 58%, respectively, compared with the conventional architecture with the same throughput condition.

Glioblastoma multiforme (GBM) is the most common primary intracranial neoplasm. Although maternal mortality in Japan is among the lowest in the world, the main cause of maternal mortality is pregnancy-related intracranial hemorrhage. This case reports a 30-year-old female pregnant patient who suddenly died at 30 weeks of gestation. She had complained of headache from early stages during pregnancy and reported a headache and stiff neck starting two weeks before her death. Postmortem computed tomography revealed an intracerebral hematoma. The autopsy of the brain revealed severe swelling. The left frontal lobe contained a cavity filled with clear fluid, and a hematoma weighing 24 g. There was also widespread cerebral edema. The histological findings after evaluation of the cavity wall material were indicative of malignancy, and positive immunostaining for alpha thalassemia/mental retardation syndrome X-linked (ATRX), p53 and isocitrate dehydrogenase (IDH-1), was consistent with a diagnosis of GBM. There are studies that indicate pregnancy can promote the clinical and radiological advancement of glioma. The acceleration of tumor growth during pregnancy has been found to depend on several factors (e.g., hormonal factors, growth factors, and hemodynamic changes). Increased cardiac output and blood volume have been shown to promote the size of vascular tumors during pregnancy. Although headaches and neck stiffness are often considered pregnancy-related, this case highlights the importance of its prompt diagnosis, which can also save the fetus’ life. It also emphasizes the need for forensic pathologists to further evaluate intracerebral hematomas identified during investigations of maternal deaths during pregnancy.

In this paper, we propose a design of asynchronous communication for an industrial wireless LAN system. In our design, MAC is synchronous multi-user round-robin transmission protocol. Low overhead Packet Division Multiple Access scheme is utilized for Multi-user Downlink transmission up to 80 MHz, while Frequency Division Multiple Access is employed for the uplink transmission. The designed of PHY system is developed based on a fast and deterministic communication featuring the synchronous multi-user system. In this paper, the industrial robots are not only controlled by synchronous communication but also by asynchronous communication via our industrial WLAN (iWLAN) system. This paper presents the hardware and software cooperative design. In the verification, up to 10 motors can be controlled by our iWLAN system by asynchronous communication, and the delay of each robot measured is 188 μs on average. Besides, the time synchronization captured by oscilloscope is from 40 to 100 ns as in our target.

Currently, Global Positioning System (GPS) is widely used as a representative position estimation system. However, GPS suffers from poor position estimation accuracy in an indoor environment. Moreover, time synchronization between devices needs to be performed for position estimation which is a resource intensive process. In previous studies, an asynchronous protocol (i.e., no synchronization requirement) called Grid Search was proposed to handle this problem. However, this method also has high complexity and takes a lot of search time to estimate the position. In this paper, we propose a method to narrow the search range using intersecting chord under the condition that generated circles intersect with each other. The proposed position estimation method has low complexity but can achieve accuracy comparable to Grid Search, i.e., a maximum estimation error less than 2 meters with 80% of the trials are within 1 meter. In addition, the calculation time can be reduced up to 6 times compared to the Grid Search when the search range extends to 5 times.

We demonstrate a precision time protocol (PTP) used to synchronize clocks in industrial wireless local area network (iWLAN) communication systems. The implementation of the system on FPGA boards for accurate verification and to test the feasibility of the system in a real environment. The result has been confirmed that time synchronization is high accuracy from 40 to 100 ns., IEEE International Symposium on Circuits and Systems (ISCAS 2019), May 26-29, 2019, Sapporo Japan

In this paper, we propose an industrial Wireless Local Area Network (iWLAN) system compatible with asynchronous communication for industrial robots (iRBs) control in factory automation (FA) environments. The design of our media access control layer is synchronous multi-user round-robin transmission protocol. Low overhead Packet Division Multiple Access (PDMA) scheme is utilized for Multi-user Downlink transmission up to 80 MHz, while Frequency Division Multiple Access (FDMA) is employed for the uplink transmission. The system is developed based on a fast and deterministic communication featuring the synchronous multi-user system. In general, the iRBs are not only controlled by synchronous communication but also by asynchronous communication via this iWLAN system. In this paper, we present the Field-programmable gate array (FPGA) implementation are carried out to confirm that our iWLAN system by asynchronous communication can control up to four motors. Based on the result of FPGA implementation, the time synchronization of the proposed system in high accuracy from 40 to 100 ns is also captured by an oscilloscope.

In this research, we propose an industrial Wireless Local Area Network (iWLAN) system compatible with asynchronous communication for industrial robots (iRBs) control in factory automation (FA) environments. In FA, iRBs are not only controlled by synchronous communication but also by asynchronous communication. As our conventional system is not compatible with asynchronous communication, it causes delay when iRBs are controlled by asynchronous communication. In order to target iRBs using asynchronous communication, we propose the utilization of specific memory writing technique. The register transfer level (RTL) simulation results show that our proposals can communicate with iRBs in faster throughput, better than the conventional system. Furthermore, the field-programmable gate array (FPGA) implementation are carried out to confirm that motors can be controlled by our iWLAN system compatible with asynchronous communication.

In this paper, a proposed hardware architecture implementation of more accuracy Precision Time Protocol (PTP) is presented. This approached design can be integrated into the wireless communication system for factory automation (FA) devices. In order to increase the closeness of the PTP harmony, we propose two approaches to improve the accurate synchronization to the nanosecond level by reducing the effects of asymmetric path delays of transmissions between master (MS) and slave (SL). The first one is the PTP protocol implementation at PHY layer to remove the random transmission jitters caused by higher layers. The second one is the full hardware implementation to remove the imbalanced timing made by the uneven hardware designs between MS and SL. Besides, a low overhead 3-frames exchange PTP approach to increase throughput of the transmission system is presented. We also implement successfully the PTP hardware design architecture and the SoPC of PHY-MAC and PTP integration system.

Highway is designed to be a traffic-jam-free road. However, the traffics are often jammed these days, especially during rush hour, causing fuel waste and air pollution. One of the reasons is the payment system which consumes time. Electronic Toll Collection system has been implemented in Indonesia to resolve this problem, but the traffic jam is still a common view in highways. It happens because the customers need to tap the electronic card to its reader until the payment transaction is verified and the bar is opened. This sequence of processes requires every vehicle to stop for a while. The accumulation of delay time is the main cause of queuing and traffic jam in highways. Further, the receipt for every transaction is still printed on a piece of paper which is eventually wasted and harm the environment. This article presents a prototype design of Queuing Free Smart Toll Gate system based on wireless technology. It can detect vehicles up to 40 km/h of speed within 3 meters radius. Service rate is less than 1 second per vehicle. Instead of using paper and ink and SMS, the payment notification is sent to the customer via the Internet. It is successfully received by customer's smartphone Telegram Messenger in less than 23 seconds after detection. This system can be an alternative solution to resolve traffic jam in highways, efficient and environmentally friendly. No more vehicles need to stop in toll gate, no more fuel wasting, no more air pollution, and no more paper trash at the toll gates.

It is my great pleasure to welcome you to the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2018), and Ishigaki island, Japan. The ISPACS is an annual important conference of the IEEE Co-sponsor and represents large number of gatherings of researchers and industry professionals in the corresponding fields in the world. This year's conference brings together more than 150 delegates from around the globe to discuss the latest advances in this vibrant and constantly evolving field.

A design of wireless communication system, particularly Media Access Control (MAC) and Physical layer system (PHY) for Factory Automation (FA) system based on Wireless Local Area Network (WLAN) communication system, is proposed in this paper. The designed of MAC is synchronous multi-user round-robin transmission protocol. Low overhead Packet Division Multiple Access (PDMA) scheme is utilized for Multi-user Downlink transmission up to 80 MHz, while Frequency Division Multiple Access (FDMA) is employed for the uplink transmission. The designed of PHY system is developed based on a fast and deterministic communication featuring the synchronous multi-user system. For efficient of multi-user transmission in the proposed protocol, the transmission time of the proposed iWLAN with 40 MHz bandwidth can achieve 500% better than PROFINET wireless standard. Furthermore, the implementation results of MAC and PHY layer of the proposed system show that FPGA logic utilization can fit with the target FPGA which is promising for a full implementation and evaluation combining with radio frequency.

In this paper, a new architecture of a multi-mode Fast Fourier Transform hardware for IEEE 802.11ax WLAN standard is presented. The proposed architecture is based on Radix-2 Multipath Delay Commutator (MDC), Radix-22 and Radix 24 Single-path Delay Feedback(SDF) stages. To optimize the throughput and area of the FFT hardware, we applied two design techniques such as compression of redundant twiddle factors, and optimization of twiddle factor multiplication. In FPGA implementation using Altera Stratix IV EP4SGX530KH40C3, the proposed FFT achieved 1.2 GSamples/s throughput and met the requirements of the 802.11ax standard. The synthesis results show that the proposed circuit is 6.19% lower latency and 30.2% lower area compared to a recently presented work while maintaining higher working frequency.

To investigate the prebiotic effect of lactulose at low dosages, we assessed changes in defaecation frequency following ingestion of 1, 2, or 3 g/day of lactulose for 2 weeks. Each test was carried out after a 2-week washout period. This was an open-label, before-after trial that enrolled 26 healthy Japanese women. The defaecation frequency, number of defaecation days, and number of faecal bifidobacteria increased significantly compared with before ingestion of 1, 2, and 3 g/day of lactulose. These results suggest that even 1 g/day of lactulose could have a prebiotic effect.

Industrial wireless system has been considered as a potential application in the upcoming wireless system (e.g. 5G and IoT era). The main requirements of this application are ultra-reliable low-latency and low-power massive machine type communication. Satisfying all these requirements at the same time is still big technical challenge, since many aspects from different layers of network system are inter-dependent in affecting overall system performance. Therefore, system design and optimization are difficult and could not be carried out solely in one part. To overcome these issues, this paper presents cross-layer optimization in order to achieve energy-efficient wireless system, while maintaining low-latency and high-reliability requirements. The cross-layer optimization is performed within Medium Access Layer (MAC) and Physical Layer (PHY), which are devoted as the backbone for radio access. The optimizations include system level design, low-power aware protocol and resource management design, signal processing algorithm design and circuit design techniques of transceiver system. Furthermore, the implementation of overall PHY-MAC hardware design for industrial wireless LAN system is presented. The proposed design offers an advantage, in terms of energy-efficient wireless system, as compared to the other classes of low-power wireless systems (e.g. Bluetooth, Zigbee) and the conventional WLAN systems.

High efficiency video coding (HEVC) is the newest video coding standard of the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. The introduction of multiple-input multiple-output (MIMO) eigenbeam-space division multiplexing (E-SDM) systems makes it possible to increase data rate by multiplexing different data streams on multiple parallel eigen-channels. In this paper, we propose a MIMO video transmission scheme for scalable high efficiency video coding (SHVC), which is the scalable extension of H.265/HEVC. Simulation results show that our video transmission scheme has more potential to broadcast video streams efficiently than conventional MIMO systems.

In this paper, we propose a positioning system using a time-synchronized wireless network that can achieve high positioning accuracy without being dependent on any global positioning system (GPS) devices with cm-level accuracy as the main goal and objective. The proposed system utilizes time of arrival (ToA) method to estimate the target's position. Based on the results, we can achieve time synchronization with less than 1ns accuracy with the average offset error of 0.05ns and cm-level positioning accuracy with the position error of 1.23cm through our simulation. Furthermore, increasing the number or measuring device in positioning system will increase the accuracy of positioning a target. High accuracy time synchronization is achievable by deploying proposed PTP with a high number of iteration performed inside the synchronization period. In this research, we aim to deploy the proposed system in industrial wireless LAN. It is applicable by embedding the system into customized wireless LAN chip with positioning ability.

Current and next generation WLAN devices have an increasing need for processing power to support new WLAN features that require high computation complexity. In this paper, we present our design for an 802.11ac/ax system with an application specific instruction-set processor (ASIP) to implement multiple disjoint system tasks at much faster speed compared to a general purpose processor. As a proof of concept, we implemented the channel SVD, channel compression/decompression and beam-forming weight computations at the same time in the embedded ASIP core to support the 802.11ac MU-MIMO beamforming feature. In addition, the design was synthesized in the Zynq zc706 evaluation board programmable logic (PL) along with the rest of the PHY. The actual task to be done by the ASIP core at any given time can be programmed via the zc706 processing system (PS) resulting in a very high hardware savings compared to an all hardware implementation.

The new use case of 5G network, such as industrial wireless control system and Machine-to-Machine (M2M) communication system, requires high reliability and real-time communication (ultra low-latency) at the same time. To increase system reliability, re-transmission scheme is one of popular technique, but it introduces a significant communication latency. To address this latency introduced by conventional re-transmission scheme, this paper presents re-transmission diversity through channel selectivity. Adjacent channel selection and random channel selection are the two channel selectivity schemes that are being considered as fast and low-latency channel selection method. The performance comparison of these two schemes are evaluated in an industrial wireless system. Evaluation results show that channel selectivity based on adjacent channel selection gives a better performance as compared with random channel selection. Furthermore, the impact of channel selectivity in different channel models are also presented to evaluate its effectiveness and to provide an insight for final deployment.

It is amazingly increasing the usage of industry robot such as in automobile assembly lines. Wire-connection networks, i.e. industry Ethernet, have been used for such robot control so far. For the recent demand of maintainanse-free and location-free-setup, wireless networks are required for industry robot control. However, the conventional WiFi PCF protocol cannot support industry Ethernet specifications such as low latency, e.g. less than 0.1 msec and error-free communication requirement for human being secure purpose. This talk will present a novel fast and secure wireless LAN system design for industry application. The error-free network protocol and system architecture as well as FPGA prototyping will be given in this talk.

Background: The high failure rate of rotator cuff repairs requires the development of methods to enhance healing at the tendon-bone junction of the repair site. Purpose: To assess functional recovery and structural outcomes in detail after implanting recombinant human bone morphogenetic protein–12 (rhBMP-12)/absorbable collagen sponge (ACS) as adjuvant treatment during open rotator cuff repair in patients over a 1-year postoperative follow-up. Study Design: Randomized controlled trial; Level of evidence, 2. Methods: A total of 20 patients were randomized into 2 groups, rhBMP-12/ACS and standard-of-care (SOC) control, with 16 and 4 patients, respectively. The patients underwent open repair of a rotator cuff tear at least 2 to 4 cm wide; in the rhBMP-12/ACS group, this was augmented with a bioscaffold containing rhBMP-12. Follow-up assessments were conducted with a 100-mm visual analog scale (VAS) for pain and active and passive ranges of motion (ROMs) including forward flexion, elevation in the scapular plane, abduction, and external rotation at 12, 16, 26, 39, and 52 weeks after surgery; isometric strength in scapular abduction and external rotation at 16, 26, 39, and 52 weeks; and magnetic resonance imaging (MRI) at 12 and 52 weeks. Results: The mean VAS score decreased from 37.9 mm preoperatively to 13.8 mm at week 52, and ROM and isometric strength recovered at week 52 in the rhBMP-12/ACS group. The mean VAS score decreased from 48.3 mm preoperatively to 1.5 mm at week 52, and ROM (excluding external rotation) and isometric strength recovered by week 52 in the SOC control group. Of the 16 patients in the rhBMP-12/ACS group, 14 showed an intact repair at week 12; the MRI scans of the other 2 patients could not be evaluated because of artifacts. In the SOC control group, 1 patient showed repair failure. At week 52, 14 repairs in the rhBMP-12/ACS group and 2 repairs with available MRI scans in the SOC control group remained intact. Conclusion: Functional recovery and structural outcomes in patients in whom rhBMP-12/ACS was used as adjuvant therapy in rotator cuff repair justify conducting future, larger, multicenter, prospective studies. Registration: NCT00936559, NCT01122498 (ClinicalTrials.gov identifier).

Recently, wireless technology experiences a fast growth to meet user demand and push toward the boundary limit of system performance. The simulation and verification framework play important role for accelerating investigation of technology proof of concept, field-trial, and large-scale commercial prototyping. In this paper, we present system-level simulation of heterogeneous model and unified HW/SW framework, particularly for next generation wireless system. The proposed framework includes a unified HW/SW co-evaluation methodology, the flexible HW/SW architecture, and fast HW/SW co-evaluation. The co-evaluation is carried out by employing hardware-in-the loop scheme that covers various abstraction level of simulation, from algorithm-level into physical-level simulation, with respect to system level simulation. The proposed co-verification framework allows a comprehensive system evaluation for a wireless system, involving various system parameters, hardware impairments, different channel conditions and cross-layer evaluations with fast run-time evaluations. Additionally, we also show an application example of multi-user wireless communication system and its experimental evaluations.

The rapid evolution and the popularity of wireless devices among worldwide users has made wireless communication as one of the main market of system-on-chip (SoC) development. The complexity of the design, the number of supported application, time-to-market, design technology are some critical challenges that need to be taken into consideration when designing the SoC for wireless communication. This paper reviews the design requirement of wireless communication system and the current SoC design technology. Finally, this paper proposes the improved HW/SW design methodology that can tackle the critical challenges for wireless communication system design. As an example of the implementation of the proposed methodology, the design and verification results of our proposed IEEE 802.11n WLAN system SoC are presented.

Interleave division multiple access (IDMA) is a potential candidate for the future fifth generation (5G) systems. In this paper, we propose a novel architecture for IDMA system with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially processes deinterleaving, despreading, spreading and interleaving for multiuser detection. The proposed architecture, which is called the interleaved domain, can perform multi-user detection directly without deinterleaving the received frame. Because of this, the interleaving is no longer needed in the interference cancellation loop resulting in the decrease of latency by half and the increase of throughput by twice. In VLSI implementation results, the proposed architecture has reduced circuit area and power consumption by 53% and 58% compared to the conventional architecture on the same throughput condition.

Recently, 802.11ax has introduced uplink Orthogonal Frequency Division Multiple Access (UL OFDMA)-based random access transmission to provide uplink multiuser capability to stations (STA) with unknown buffer status. These STAs include those that are waking up from sleep and unassociated STAs trying to establish connection for the first time. Due to the absence of carrier sensing per resource unit, this procedure has a maximum efficiency of only about 37% for high number of STAs. The efficiency will decrease further without properly choosing the random access parameters. In this paper, we first build an analytical model of the performance of UL OFDMA random access transmission and verify it using simulations. In addition, we propose methods to optimize various random access parameters to maintain a system efficiency near the 37% limit. Simulation results show that our optimization methods can increase the throughput of UL OFDMA random access by as much as 39% when compared to randomly chosen parameters.

This paper proposes a fast and low-complexity retransmission scheme for Industrial WLAN system. The proposed scheme exploits the frequency diversity and employs channel selectivity in order to achieve high-reliability and low-latency communication. The channel selectivity is carried out instantly by re-scheduling sub-carrier allocation during OFDM transmission in order to obtain diversity gain. Evaluation results show that the performance of the proposed scheme in terms of system-error rate and achievable transmission throughput rate, are significantly improved from the conventional re-transmission scheme. Furthermore, the proposed method only need a minor modification in both of communication protocol and transceiver design from the existing Industrial WLAN system. Hence, the low-complexity transmission scheme could be realized in current OFDM-based wireless system.

In this paper, we propose a novel architecture for IDMA system with low latency and high throughput for the uplink multi-user wireless system. The throughput of the proposed IDMA system can be improved to about double compared to the conventional IDMA system while the hardware complexity remains unchanged. To achieve this, the proposed system utilizes the interleaver/de-interleaver-less architecture to minimize the latency of the interference canceller in IDMA receiver. In the conventional architecture, the IDMA receiver sequentially processes the de-interleaving, interleaving, de-spreading and spreading that cause high latency. The proposed architecture can perform these sequential processes at the same time resulting in a reduction of interference cancellation operation cycles in half.

This study examined whether the global clinical data for bazedoxifene could be extrapolated to a Japanese population by evaluating the results of a phase 2 study in postmenopausal Japanese women with osteoporosis as compared to those of a pivotal, phase 3 study. The efficacy of bazedoxifene 20 and 40 mg versus placebo on lumbar spine bone mineral density (BMD), bone turnover markers, lipid profile, incidence of fractures, and safety parameters was compared between the Japanese phase 2 study (N = 429) and the global phase 3 study (N = 7,492) during a 2-year period. In the primary population for assessment of bridging, differences in the mean percent change from baseline in lumbar spine BMD at 2 years relative to placebo were greater for women treated with bazedoxifene 20 and 40 mg in the phase 2 study than in the phase 3 study. BMD changes in the bazedoxifene groups were confirmed to be similar between the phase 2 study population and a subset of the phase 3 study population with similar baseline characteristics. The effects of bazedoxifene on incidence of fractures, bone turnover markers, and lipid metabolism were similar between studies. There were no major differences in safety parameters between studies. The greater improvement in lumbar spine BMD and similar results in bone turnover markers, fracture incidence, and safety profile observed with bazedoxifene in the phase 2 study compared with the phase 3 study confirmed the feasibility of extrapolating the global clinical data to a Japanese population.

Thanks to the achievements in wireless technology, maximum data rate of wireless LAN systems was rapidly increased recently. As a key part of the WEP and the WPA security for the wireless LAN system, throughput of RC4 must be significantly improved also. This paper proposes two high throughput RC4 architectures. The first one is a RAM-based RC4 using a single of 256-byte tri-port RAM to store the S-box. The core generates 4 bits of ciphering key per clock cycle. This paper also proves that 4 bits/cycle is the maximum throughput can be achieved by a RAMbased RC4 circuit. The second architecture is a Register-based M-byte RC4 that uses a set of registers to store the S-box. It is able to generate multiple bytes of ciphering key per clock cycle, and is proposed as a novel solution for designing extremely high throughput RC4 core for future WLAN systems. Base on this proposal, a 4-byte RC4 core is developed (M = 4). The synthesis results in 90 nm ASIC show that: As the same throughput’s requirement, the proposed RAM-based and Register-based RC4 can respectively save 60% and 50% of power consumption as compare to that of the most recently works. Moreover, the proposed Register-based design is the best candidate for achieving high throughput at low frequency. key words: RC4, encryption, WEP, WPA, IEEE 802.11ac

This paper presentsa new architecture andASICimplementation of high throughput of Counter with Cipher Block Chaining - Message Authentication Code(CCM) for robust security network such as gigabit wireless IEEE 802.11ac in case considering trade-off between throughput and resource saving. We propose a new architecture of AES-CCM core adopted in parallel which utilizes two separated AES forward cipher cores for MIC calculation in Counter (CTR) Mode and encryption or decryption data in Cipher Block Chaining (CBC) Mode. The implementation of AES-CCM core in Synopsys CMOS SAED90nm process achieves2.69Gbps of throughput at 264MHz clock frequency.The proposed architecture of AES-CCM corereduces latencyby one AES cycle in comparison with conventional architectures. In addition,the AES-CCM core supports bothgeneration-encapsulation and decryption-verifica-tionprocess with symmetrical data processing routine. We also introduce an implementation of reordering AES transformation method comes along with composite Sbox in order to gain maximal period of the composition and saving resources compared to original AES algorithm implementation.  . Index Terms-AES, AES-CCM, CCMP, WPA2, 802.11i, Security

In the recent years, wireless technology has arised as a promising alternative to ethernet technology as a transmission medium for industrial automation system. This paper presents our wireless solution for industrial application, which is based on wireless LAN (WLAN) system. In this paper, our proposed system on chip (SoC) design and FPGA implementation for industrial wireless local area network (iWLAN) systems is introduced. The SoC design includes the dual-processor ARM based reconfigurable CPU, high-performance AMBA bus, model-based WLAN PHY, and HW/SW co-design WLAN MAC layer, and high-speed peripheral IP. The FPGA implementation is performed on our advanced FPGA verification platform. We utilize the multiprocessor architecture to satisfy the real-time property of iWLAN system. Our simulation results and FPGA implementation show that our design and implementation can meet the requirement of the system.

In this paper, we present unified Hardware (HW)/Software (SW) framework for efficient system level simulation of complex circuits, particularly high throughput wireless communication system. The proposed framework include a unified methodology covering both of system level simulation (e.g. MATLAB or C/C++) and physical level verification (e.g FPGA). It allows performing fast HW/SW evaluation in the context of system level performance and also covering large number of verification scenarios within acceptable time. Experimental evaluations show the example design case achieves improvement of simulation time several orders of magnitude faster than pure software simulation and also capable to run in near real-time processing. Moreover, the proposed verification platform can be used for complete performance characterization of a MIMO wireless system under various system parameters, hardware impairments and channel model.

In this paper, we propose an alternative positioning system using time-synchronized wireless network that can achieve high positioning accuracy without being dependent to any global positioning system (GPS) devices with cm-level accuracy as the main goal and objective. The proposed system utilizes time of arrival (ToA) method in order to estimate the target's position. Based on the results, we can achieve time synchronization with less than 1ns (average offset error of 0.05ns) accuracy and cm-level (position error of 1.23cm) positioning accuracy through our simulation. Furthermore, increasing the number or measuring device in positioning system will increase the accuracy of positioning a target. High accuracy time synchronization is achievable by deploying proposed PTP with high number of iteration in synchronization period. In this research, we aim to deploy the proposed system in industrial wireless LAN. It is applicable by embedding the system into customized wireless LAN chip with positioning ability.

Random access Orthogonal Frequency Division Multiple Access (OFDMA), a method for uplink multi-user transmission (UL-MU) for STAs with unknown transmit buffer has been adopted in the upcoming IEEE802.11ax next generation wireless LAN standard. In this paper, we propose a performance analysis model which use bidimensional Markov chain model of OFDMA random access. Via computer simulation, we show the usefulness of the proposed method even in the case of dense environment. In addition, we present a method in calculating the optimal number of resource units, which in 802.11ax refer to a subset of subcarriers to assign the user for OFDMA random access from numerical results.

This paper proposes a design of wireless communication system, particularly physical layer system (PHY) for Factory Automation (FA) system based on Wireless Local Area Network (WLAN) communication system. The designed PHY system is developed based on a fast and deterministic communication featuring a synchronous multi user round robin transmission protocol. Low overhead Packet Division Multiple Access (PDMA) scheme is utilized for Multi-user Downlink transmission, while the Frequency Division Multiple Access (FDMA) is employed for the uplink transmission. For efficient PHY implementation, several approaches on architectural aspects are also introduced. Implementation results show that the optimized design of transmitter and receiver have efficient logic resource while maintain required processing speed and error performance.

This paper presents fast design exploration with unified HW/SW co-verification framework, particularly for high throughput wireless communication system. Design exploration is an important task during design development in order to obtain optimum design with various possible methods/algorithms of implementation and also under various design constraints. The fast design exploration is enabled by employing co-operation between model-based RTL design and proposed unified HW/SW co-verification platform. Fast design exploration and unified HW/SW co-verification of MIMO MLD Decoder is selected as design example to show the effectiveness employed methodology and proposed platform. This approach gives significant improvement on reducing hardware design and verification time as compared with conventional approach, as well as provides reliable design.

For the last decades, the advancement of system on chips complexity and size are driving the verification process of the digital designs to be much more complicated and time consuming. Moreover, nowadays, the verification process takes up to 80% of overall design development time. This paper emphasizes the importance of automatic testbench generator for industrial wireless local area network (iWLAN) for factory automation system (FA). The proposed generated testbench is written in SystemVerilog to represent the functions and to reduce the code size compared to traditional Verilog testbench. It is also supported by assertion-based method to simplify the code and to improve the observability in SoC verification. Experimental results show that our proposed method produces smaller code size and can improve the efficiency of the verification of SoC designs. Moreover, we shows the verified iWLAN system data transfer.

This paper proposes a 4×4 MU-MIMO channel emulator with automatic channel sounding feedback used for beam-forming and MU-MIMO precoding features of IEEE 802.11ac. The main contribution of this paper is the design of a MU-MIMO channel emulator capable of sending channel feedback automatically to the AP from the generated channel coefficients after a programmable time duration. This function helps to evaluate the precoding algorithms without channel estimation error and uses very minimal MAC features. The second contribution is the design of single path implementation with serial processing which plays an important role on reducing the hardware complexity. The design choice makes it possible to generate channel coefficients for very high sampling rate systems with little increase in complexity. In addition, single path implementation allows the addition of the feedback channel output with only few additional nonsequential elements which would otherwise double in a parallel implementation. To demonstrate the functionality of our MU-MIMO channel emulator, we present actual hardware emulator results of precoded receive signal constellation on oscilloscope.