Search

Background Many studies have reported the J-shaped relationship between alcohol consumption and coronary heart disease (CHD) risk; therefore, light-drinkers is generally recognized to be associated with the lower risk of CHD. However, the mechanisms of lower risk for CHD in light-drinkers are still unclear. Alcohol drinking status is likely to be associated with not only CHD risk factors but also dietary intake. Nevertheless, few studies report these relationships in detail. Purpose The purpose of this study is to evaluate the relationships of alcohol drinking status with CHD classical risk factors and the intake of macro- and micro- nutrients in Japanese. Methods Study participants were 1,090 Japanese men and women aged 40–59 years from The INTERLIPID study excepted for 55 individuals who had missing data (n=26) and were past-drinkers (n=29). Alcohol consumption was assessed with two 7-day alcohol records, and average ethanol intake (per week) was calculated. Participants were classified into following 4 groups: non-drinkers (0g/week), light-drinkers ( Results Serum HDL cholesterol levels increased and LDL cholesterol levels decreased with increasing alcohol consumption. Systolic and diastolic BP increased with increasing alcohol consumption. J-shaped relationships with alcohol consumption were observed for the proportion of current smoker, number of cigarettes, and the prevalence of hypertension; that is, light-drinkers was lowest among all groups. The prevalence of dyslipidemia was the highest in non-drinkers, and decreased with increasing alcohol consumption. In heavy-drinkers, total energy (kcal/day) was the highest, but energy intake without alcohol (kcal/day) was the lowest. For macronutrients, the intake of carbohydrate (%kcal) decreased, and the intakes of total and animal protein (%kcal) increased with increasing alcohol consumption. The intakes of total cholesterol (mg/1000kcal) and sodium (mg/1000kcal) increased, and total fiber (g/1000kcal) decreased with increasing alcohol consumption. These associations were similar in men and women. Conclusions Alcohol consumption was related with not only CHD classical risk factors but also the intake of macro- and micro-nutrients. Non-drinkers had a higher proportion of some CHD risk factors than light-drinkers. These results might influence on J-shaped relationship between alcohol consumption and CHD risk. Acknowledgement/Funding 1: Ministry of Education, Science, Sports, and Culture of Japan, 2: National Institutes of Health, Bethesda, MD, USA

Display Omitted Triangular fin channel double-gate MOSFETs were fabricated on SOTB.A high threshold voltage shift was obtained in triangular fin devices.A smaller variability was confirmed in triangular fin devices by wet etching.Uniform line edges of a triangular fin were formed by wet etching.A damage-free BOX layer was obtained by the orientation dependent wet etching. Triangular fin (Tri-Fin) channel double-gate (DG) MOSFETs were successfully fabricated on (100) SOTB wafers using orientation dependent wet etching, and their electrical characteristics were systematically compared to the rectangular fin (Rec-Fin) ones by RIE. Thanks to the wide bottom area and the suppressed line edge roughness of Tri-Fins by the wet process, a higher threshold voltage (Vt) tunability and a smaller Vt variation were obtained as compared to the Rec-Fin ones. Moreover, the wet processed Tri-Fin devices provide a damage-free BOX layer, which is useful for the fabrication of multiple Vt devices with an ultrathin BOX layer.

We investigated the impact of fin length ( T fin ) on the threshold voltage ( V th ) modulation by back bias ( V b ) for independent double-gate (IDG) tunnel fin field-effect transistors (tFinFETs). It was found that V th can be tuned by V b for IDG tFinFETs regardless of T fin , which can be explained by the back-gate-effect model of IDG FinFETs. For IDG tFinFETs, the slope (back-gate-effect factor ( γ )) of V th with respect to V b increases with thinning T fin . This means that T fin thinning is effective for tuning V th by V b for IDG tFinFETs. Furthermore, it was demonstrated that this back-bias-effect is consistent with the results of device simulation using an advanced nonlocal band-to-band model.

The scaled charge trapping (CT) type silicon on insulator (SOI) FinFET flash memories with different blocking layer materials of Al2O3 and SiO2 have successfully been fabricated, and their electrical characteristics including short-channel effect (SCE) immunity, threshold voltage (Vt) variability, and the memory characteristics have been comparatively investigated. It was experimentally found that the better SCE immunity and a larger memory window are obtained by introducing a high-k Al2O3 blocking layer instead of a SiO2 blocking layer. It was also confirmed that the variability of Vt before and after one program/erase (P/E) cycle is almost independent of the blocking layer materials.

Y. X. Liu, T. Matsukawa, K. Endo, S. O’uchi, J. Tsukada, H. Yamauchi, Y. Ishikawa, W. Mizubayashi, Y. Morita, S. Migita, H. Ota, and M. Masahara National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba Central 2, 1-1-1 Umezono, Tsukuba-shi, Ibaraki 305-8568, Japan. Tel: +81-29-861-3417, Fax: +81-29-861-5170, E-mail: yx-liu@aist.go.jp Three-dimensional (3D) fin-channel devices provide excellent short-channel effect (SCE) immunity thanks to the strong controllability of channel potential by the multiple gates. Therefore, the scaled charge trapping (CT) type FinFET flash memories have actively been developed in the past few years (1-3). Very recently, we have also developed floating gate (FG) type SOI-FinFET flash memories with different gate structures (4, 5), and experimentally confirmed that tri-gate (TG) structure shows the better SCE immunity and a larger memory window than double-gate (DG) structure. As a further study, in this work, we fabricate CT type TG-structured SOI-FinFET flash memories with different gate materials and different blocking layer materials, and comparatively investigate their electrical characteristics. 1. Device Fabrication In the device fabrication, we used (110)-oriented SOI wafers, and the Si-fin channels were fabricated by using orientation dependent wet etching (6). To fabricate TG structure, the SiO2 fin hard-mask layer was removed by RIE. Then, a 4.3-nm-thick tunnel oxide was formed by thermal oxidation, followed by the deposition of a 10-nm-thick nitride (Si3N4) layer by LPCVD. As the blocking layer, a 10-nm-thick Al2O3 layer or a 9-nm-thick SiO2 layer was deposited on the different sample wafers. As the different gate materials, we used n+-poly-Si and PVD-TiN metal. Figure 1(a) shows the SEM image of the fabricated FinFET flash memory with a scaled gate length (Lg) of 26 nm. The cross-sectional STEM images of the fabricated n+-poly-Si gate SONOS, PVD-TiN metal gate MONOS and MANOS with a high-k Al2O3blocking layer are shown in Figs. 1(b), 1(c) and 1(d), respectively. It is clear that uniform and ultrathin Si-fin channels are successfully fabricated thanks to the orientation dependent wet etching. 2. Gate Material Dependent of Memory Property At first, we measured the initial Id-Vg characteristics of the fabricated SONOS and MONOS type FinFET flash memories, and the threshold voltage (Vt) values were evaluated at a constant drain current of Id = 1 mA. It was experimentally found that almost the same sVt is obtained in the SONOS and MONOS devices. This result indicates that Vt variation is independent of gate material. Then, we measured P/E characteristics of the fabricated SONOS and MONOS devices. It was found that a larger memory window is obtained in the MONOS devices than the SONOS ones due to the higher work function of PVD-TiN gate than the n+-poly-Si gate as shown in Fig. 2. The higher gate work function is effective to the suppression of electron back tunneling during erase operation [7]. 3. Blocking Layer Dependent of Memory Property To investigate blocking layer material dependence on the electrical characteristics of the CT type FinFET flash memories, we fabricated MONOS and MANOS type devices with different blocking layers of SiO2 and Al2O3 as mentioned before. The initial Id-Vg characteristics of the fabricated MONOS and MANOS type FinFET flash memories with different Lg values from 26 to 103 nm were measured and the SCE immunity was systematically evaluated. It was found that the smaller Vt roll-off and the better subthreshold slope (S-slope) are observed in the MANOS devices as compared to the MONOS ones due to the high-k effect of Al2O3 in MANOS devices. The P/E characteristics of the fabricated MONOS and MANOS devices were also comparatively investigated. It was found that a significant memory window increment is obtained by introducing an Al2O3 blocking layer instead of the SiO2 one as shown in Fig. 3. This result is reasonable because a high-k Al2O3blocking layer is effective to enhance the electric field across the tunnel oxide layer and to reduce the electric field across itself. Therefore, electron back tunneling from the gate to nitride layer is effectively suppressed during erase operation. As a result, a deep erase and a large memory window are obtained in the MANOS devices than the MONOS ones. It was also confirmed that the fabricated MONOS and MANOS devices can operate over 100 k cycles, and can maintain a reasonable memory window after 10 years. In summary, we have investigated the gate material and blocking layer material dependences on the electrical characteristics of the fabricated CT type FinFET flash memories. It was experimentally found that a high work function metal gate and a high-k blocking layer are very useful to the enhancement of memory window. Acknowledgment: This work was supported in part by the Nanotechnology Project of NEDO, Japan. [1] P. Xuan et al., IEDM Tech. Dig., 609 (2003). [2] M. Spechi et al., IEDM Tech. Dig., 1083 (2004). [3] S-K. Sung et al., Symp. VLSI Tech. Dig., 106 (2006). [4] Y. X. Liu et al., Ext. Abstract, SSDM, 985 (2011). [5] T. Kamei et al., IEEE EDL 33345 (2012). [6] Y. X. Liu et al., IEEE EDL 24484 (2003). [7] C. H. Lee et al., IEDM Tech. Dig., 613 (2003).

FinFETs with the low temperature microwave annealing process have been successfully fabricated and the superiority of the microwave annealing process has been precisely studied. For the first time, it is revealed that the microwave annealed FinFET exhibits less Vth variability and lower gate leakage.

We report on performance enhancement of FinFETs with a 25-nm-short extension of the source/drain by using atomic layer deposition (ALD) of SiO 2 thin films for the side-wall spacer (SWS) of the gate electrode. Recently, the higher parasitic resistance ( R para ) of the source/drain region due to the narrow fin width is one of the issues to be solved for the FinFET devices. In this study, the performance of the FinFETs has been successfully improved by the reduction of the parasitic resistance using the ALD-SWS.

ON-current (Ion) variability is comprehensively investigated for fin-shaped FETs (FinFETs) by measurement-based analysis. Variation sources of Ion are successfully extracted as independent contributions of threshold voltage Vt, transconductance Gm, and parasitic resistance Rpara. As well as Vt variability, Gm variation exhibits a linear relationship in the Pelgrom plot. However, the Gm variation is not reduced with scaling the gate dielectric thickness unlike the Vt variation. Perspective for 14-nm FinFETs represents that the Gm variation will be the dominant Ion variation source. A solution to reduce the Gm variation for the FinFET is also proposed.

The crystal-Si and poly-Si fin-channel flash memories with a thin n+-poly-Si floating-gate (FG) layer have successfully been fabricated, and their electrical characteristics have systematically been investigated. It was experimentally found that the better short-channel effect (SCE) immunity, the smaller threshold voltage (Vt) variations and a higher program speed are obtained in the crystal-Si fin-channel tri-gate (TG)-type flash memories than in the double-gate (DG)-type ones. It was also confirmed that split-gate crystal-Si fin-channel flash memories show highly suppressed over-erase as compared to that in stack-gate memories. Moreover, it was found that Vt variation in the poly-Si fin-channel flash memories after a program/erase (P/E) cycle became comparable to that in the crystal-Si fin-channel memories. The measured source-drain breakdown voltage (BVDS) was higher than 3.2 V even the gate length (Lg) was down to 76 nm. The developed technology is very useful for the fabrication of scaled NOR-type flash memory.

We compared the electrical characteristics, including mobility and on -state current Ion, of n+-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights Hfin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length Lg decreases, Ion for devices with tall fins becomes worse, probably due to a high parasitic resistance Rp. Furthermore, Vth variation increased with increasing Hfin due to rough etching of the fin sidewall. Process technologies for reducing Rp and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

The threshold voltage Vt variability in the scaled crystal channel and poly-Si channel double-gate fin-type metal-oxide-semiconductor field-effect transistors (FinFETs) with different gate oxide thicknesses Tox has been systematically analyzed. By investigating the Tox dependence of Vt variations in crystal channel FinFETs, the gate-stack origin sources, i.e., work function (φm) variation and gate oxide charge (Qox) variation sources, were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by the orientation-dependent wet etching contribute to the reduction of gate-stack origin Vt variations. Moreover, it was experimentally found that the standard Vt deviation (σVt) of poly-Si channel FinFETs is three times higher than that of crystal channel ones, and a good subthreshold slope in the poly-Si channel FinFETs was obtained with gate length Lg down to poly-Si grain size.

This paper demonstrates a FinFET operational amplifier (opamp), which is suitable to be integrated with digital circuits in a scaled low-standby-power (LSTP) technology and operates at extremely low voltage. The opamp is consisting of an adaptive threshold-voltage (Vt) differential pair and a low-voltage source follower using independent-double-gate- (IDG-) FinFETs. These two components enable the opamp to extend the common-mode voltage range (CMR) below the nominal Vt even if the supply voltage is less than 1.0V. The opamp was implemented by our FinFET technology co-integrating common-DG- (CDG-) and IDG-FinFETs. More than 40-dB DC gain and 1-MHz gain-bandwidth product in the 500-mV-wide input CMR at the supply voltage of 0.7V was estimated with SPICE simulation. The fabricated chip successfully demonstrated the 0.7-V operation with the 480-mV-wide CMR, even though the nominal Vt was 400mV.

In this paper, Ta/Mo interdiffusion dual metal-gate technology, which has an advantage in realizing dual gate work functions without etching of metals from the gate dielectrics, has been introduced for a FinFET. Gate-first fabrication of the FinFET was successfully implemented by optimizing the deposition and patterning of the Mo and Ta/Mo metal gates on the ultra- thin fin channels. The Ta/Mo-gated n-MOS and Mo-gated p-MOS FinFET exhibit symmetrical values of Vth (0.31/-0.36 V), which are desirable for FinFET CMOS circuit operation with enhanced current drivability, because the threshold voltage (Vth) is reduced due to Ta diffusion in the Ta/Mo gate. It was experimentally found that the Ta/Mo interdiffusion process causes no degradation in integrity of the gate dielectric or the carrier mobility. It was also confirmed that the Ta/Mo interdiffusion process is appropriate for a scaled gate length down to 100 nm.

We have investigated dual-work-function metal gates based on Mo and stacked Ta/Mo fabricated by an interdiffusion method that does not require a metal etching process from the gate dielectrics. The diffusion of Ta into the Mo layer provides a markedly reduced work function for the Ta/Mo gate (4.42 eV) in comparison with that for the single Mo gate (5.04 eV). The metal–oxide–semiconductor field-effect transistors (MOSFETs) with the Mo and Ta/Mo gates on 4-nm-thick SiO2 were fabricated by the gate-first process with dopant activation annealing at 850 °C. The Ta/Mo-gate n-MOSFET with the reduced gate work function and the Mo-gate p-MOSFET exhibited almost symmetrical threshold voltages (+0.53/-0.45 V). It was also confirmed that the Ta/Mo interdiffusion process did not degrade the gate dielectric integrity and electron mobility in contrast to the case of the single Mo gate.

This paper presents the fin-height controlled TiN-gate FinFET CMOS technology based on the experimental carrier mobility data. The good current matching by tuning the N-channel fin-height and the excellent transfer performance in the fabricated TiN-gate CMOS inverter are demonstrated. The developed technologies are attractive to materialize the high-performance FinFET CMOS circuits.

A novel resist etch-back process for fabrication of separated-gate four-terminal FinFETs has been investigates. This process enabled co-fabrication of three-terminal (3T) and four-terminal (4T) FinFETs on a same chip. The fabricated 3T-FinFET shows excellent sub-threshold characteristics and drain induced barrier lowering (DIBL) value whereas the 4T-FinFET provides efficient Vth controllability. The effective Vth controllability with keeping a small sub-threshold slope has been confirmed in the synchronized double gate (DD) operation mode

We systematically investigated the NBTI degradation of Si-channel p-type tunnel FETs (pTFETs). The NBTI degradation mechanism of pTFETs is almost the same as that of pFETs. It was clarified that the NBTI degradation of pTFETs is only caused by the trap charge and the interface state degradation located in the tunneling region near the n+ source/gate edge. Furthermore, in terms of the BTI degradation of n- and p-type TFETs, although the injection sources of carriers inducing PBTI and NBTI are different, applying a drain bias corresponding to the operation conditions has an effect on the BTI lifetime improvement of n- and p-type TFETs.

This paper reports the positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel field-effect transistors (TFETs) with high-k gate stacks. The subthreshold slope (SS) is not degraded at all while the threshold voltage (V th ) shifts in the positive direction by the PBTI stress. The activation energy of ΔV th for TFETs is almost the same as FinFETs, indicating that the PBTI mechanism for TFETs is almost the same as FinFETs. It was found that by applying a positive bias to the n+-drain, the PBTI lifetime is dramatically improved as compared with that in the conventional stress test. This is because carrier injection from the n+-drain is the main cause of the PBTI, especially for n-type TFETs. Thus, to accurately predict the PBTI lifetime of n-type TFETs, it is necessary to apply a drain bias for the reliability test.

Polycrystalline-silicon (poly-Si) and crystalline-silicon (crystal-Si) channel FinFET CMOS inverters were successfully fabricated and the variations of threshold voltage (V t ) for their individual n- and p-channel transistors and the logic gate V t (V Thc ) for the inverters were systematically investigated. It was found that poly-Si n- and p-channel devices show about 3 and 5 times larger σV t values, respectively and about 2 times larger σV Thc as compared to those in crystal-Si channel ones. The calculated σV THC values by using the error propagation low are good agreement with experimental results.

The titanium nitride (TiN) gate electrode with a tunable work function has successfully been deposited on the sidewalls of upstanding Si-fin channels of FinFETs by using a conventional reactive sputtering. It was found that the work function of the TiN (phiTiN) slightly decreases with increasing nitrogen (N2) gas flow ratio, RN=N2/(Ar+N2) in the sputtering, from 17% to 100%. The experimental threshold voltage (Vth) dependence on the RN shows that the more RN offers the lower Vth for the TiN gate n-channel FinFETs. The composition analysis of the TiN films with different RN showed that the more amount of nitrogen is introduced into the TiN films with increasing RN, which suggests that the lowering of phi TiN with increasing RN should be related to the increase in nitrogen concentration in the TiN film. The desirable Vth shift from -0.22 to 0.22 V was experimentally confirmed by fabricating n+ poly-Si and TiN gate n-channel multi-FinFETs without a channel doping. The developed simple technique for the conformal TiN deposition on the sidewalls of Si-fin channels is very attractive to the TiN gate FinFET fabrication

A high aspect ratio and damage-free vertical ultrathin channel for a vertical-type double-gate MOSFET was fabricated by using low-energy neutral-beam etching (NBE). NBE can completely eliminate the charge build-up and photon-radiation damages caused by the plasma. The fabricated FinFETs realize a higher device performance (i.e., higher electron mobility) than that obtained by using a conventional reactive-ion etching. The improved mobility is well explained by the NB-etched atomically flat surface. These results strongly support the effectiveness of the NB technology for nanoscale CMOS fabrication

Ultrathin-channel formation of a vertical-type double-gate metal oxide semiconductor field effect transistor using a low-energy neutral-beam etching (NBE) is proposed. The NBE can completely eliminate charge buildup and photon radiation damage from the plasma. By optimizing NBE conditions, rectangular vertical channels were fabricated with a SiO2 hard mask under low-energy NBE conditions.

We have investigated the fabrication processes and device characteristics for n-channel triple-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) on (100) silicon-on-insulator substrates. By optimizing the diagonal ion implantation conditions for the narrow fin channel, the fabricated triple-gate device showed an electron mobility almost compatible to a planar MOSFET with a supreme subthreshold slope of 64 mV/decade and drain induced barrier lowering (DIBL) of 15 mV/V.

We present an experimental study of effective carrier mobility ( µeff) of multi-fin-type double-gate metal–oxide–semiconductor field-effect transistors (FinFETs) with a (111) channel surface fabricated by orientation-dependent wet etching. The peak values of the obtained µeff of electrons and holes are approximately 300 and 160 cm2/(V s), respectively, which are close to those in (111) bulk metal–oxide–semiconductor field-effect transistors (MOSFETs). Moreover, the effective electric field (Eeff) dependence of the µeff of electrons and holes shows a good agreement with the mobility universal curves of (111) bulk MOSFETs. These results indicate that the quality and channel surface roughness of Si-fins by orientation-dependent wet etching are excellent. The obtained results of µeff are very useful for the modeling and design of FinFET-complementary metal–oxide–semiconductor (CMOS) circuits and the developed wet etching technique is very attractive in the fabrication of ultrathin and high-quality Si-fin channels.

This paper describes a comprehensive study on the threshold voltage (V/sub th/) controllability of four-terminal-driven double-gate (DG) MOSFETs (4T-XMOSFETs) with independently switched DGs. Two types of 4T-XMOSFETs (fin and vertical) are experimentally demonstrated and their V/sub th/ controllability is thoroughly investigated in relation to the initial V/sub th/ in the DG-mode based on comprehensible modeling of the devices. Based on the investigation and simulated predictions, device design guidelines for 4T-XMOSFETs are proposed. Decreasing the workfunction of the DGs and increasing the oxide thickness of the second gate (T/sub ox2/) are preferable for improving the performance of the 4T-XMOSFET. The optimum workfunction of DGs for attaining low I/sub off(stand-by)/ and high I/sub on(active)/ under the limited V/sub g2/ condition is also proposed.

This paper presents, for the first time, the experimental electron mobility in FinFETs with a (111) channel surface fabricated by the orientation-dependent wet etching. The maximum electron mobility (ueff) is around 300-cm2 /V-s, which is close to that in the (111) bulk MOSFETs. Moreover, the value of ueff is comparable or better than the reported ones in the usual FinFETs with a (110) channel surface prepared with careful surface treatments. This result indicates that the quality and channel surface roughness of the Si-fins by the orientation-dependent wet etching are much better than those fabricated by the conventional reactive ion etching (RIE) process.

A vertical ultrathin channel formation process for a vertical type double-gate (DG) MOSFET is proposed. Si wet etching using an alkaline solution has newly been found to be significantly retarded by introducing ion bombardment damage. We have also found that the ion-bombardment-retarded etching (IBRE) is independent of ion species and the implanted impurities can easily be transferred to be the dopants for source and drain regions of MOSFETs. By utilizing the IBRE, vertical type DG MOSFETs with a 12-nm-thick vertical channel were fabricated successfully. The fabricated vertical DG MOSFETs clearly exhibit the unique advantage of DG MOSFETs, i.e., high improvement of short-channel effect immunity by reducing the channel thickness. Thanks to the ultrathin channel, very low subthreshold slopes of 69.8 mV/dec. for a p-channel and 71.6 mV/dec for an n-channel vertical DG MOSFET are successfully achieved with the gate length of 100 nm.

The electrical characteristics of ideal rectangular cross section Si-Fin channel double-gate MOSFETs (FXMOSFETs) fabricated by a wet process have experimentally and systematically been investigated. The almost ideal S-slope of 64 mV/decade was obtained for the fabricated 20 nm Si-Fin and 125 nm gate-length FXMOSFET. This excellent subthreshold characteristic shows that the quality of the rectangular Si-Fin channel with (111)-oriented sidewall is good enough to realize high-performance FXMOSFETs. The current and transconductance multiplication accurately proportional to a number of 30 nm Si-Fin channels was confirmed in the fabricated multi-fin FXMOSFETs. The systematic investigation of the electrical characteristics of the fabricated FXMOSFETs in the 20-110-nm Si-Fin and 2.3-5.2-nm gate oxide regimes reveals that short-channel effects can be effectively suppressed by reducing the Si-Fin thickness to 20 nm or less. The developed processes are quite attractive for fabrication of ultranarrow Si-Fin channel double-gate MOSFETs.

The functional split-gate type trigate flash memory cell transistors have successfully been fabricated for the first time, and their threshold voltage (Vt) variations before and after NOR-mode program/erase cycle have systematically been compared with the stack-gate ones. It was experimentally found that split-gate type cell transistors with the same control gate length (LCG) of 176 nm show much smaller Vt distribution after erase compared to those of stack-gate ones. Moreover, the measured source-drain breakdown voltage (BVDS) is higher than 3.1 V even the LCG was down to 76 nm. This indicates that the developed split-gate type trigate flash memory is very effective for scaled NOR-type flash memory with highly suppressed over-erase.

We systematically investigated the bias temperature instability (BTI) of tunnel field-effect transistors (TFETs). The positive BTI and negative BTI mechanisms in TFETs are the same as those in metal–oxide–semiconductor FETs (MOSFETs). In TFETs, although traps are generated in high-k gate dielectrics by the bias stress and/or the interface state is degraded at the interfacial layer/channel interface, the threshold voltage (V th) shift due to BTI degradation is caused by the traps and/or the degradation of the interface state locating the band-to-band tunneling (BTBT) region near the source/gate edge. The BTI lifetime in n- and p-type TFETs is improved by applying a drain bias corresponding to the operation conditions.

The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k gate stacks have been thoroughly investigated and compared with conventional FinFETs. The subthreshold slope (SS) is not degraded at all while the threshold voltage (V th ) shifts in the positive direction by the PBTI stress. The activation energy of ?Vth for TFETs is almost the same as FinFETs, indicating that the PBTI mechanism for TFETs is almost the same as FinFETs. It was found that, by applying a positive bias to the n+-drain (normal operation condition), the PBTI lifetime is dramatically improved as compared with that in the conventional stress test (both the p+-source and n+-drain are grounded). This is because carrier injection from the n+-drain is the main cause of the PBTI, especially for n-type TFETs. Thus, the realistic impact of the PBTI is significantly mitigated for n-type TFETs.

The effectiveness of amorphous metal gate (MG) in suppressing low-frequency noise (LFN) for FinFETs has been thoroughly investigated. It was demonstrated that the amorphous TaSiN MGs with various atomic compositions provide flexible tuning of threshold voltage (V t ) as well as small V t variability, namely AVt. It was found that the TaSiN-MG FinFETs exhibit drastic reduction of LFN in comparison to the poly-crystalline TiN MG case. Modelling by 3D-TCAD reveals that work function variation (WFV) of the MG has a significant impact on LFN generation. Suppression of A Vt and LFN is highly beneficial to conduct further scaling of analog/digital components in SoC.

The 3D fin-channel charge-trapping (CT) type flash memories with a high-k Al 2 O 3 blocking layer (MANOS) have successfully been fabricated by scaling down L g to 22 nm, and their electrical characteristics including variability of threshold voltage (V t ), endurance and retention characteristics have systematically been investigated. Thanks to the high-k effect of an Al 2 O 3 blocking layer, it was found that the better short-channel effect (SCE) immunity and a larger memory window are obtained in the fabricated MANOS type flash memories than the MONOS ones with a SiO 2 blocking layer.

FinFETs with an amorphous metal gate (MG) are fabricated on silicon-on-thin-buried-oxide (SOTB) wafers for realizing both low variability and tunable threshold voltage (V t ) necessary for multiple V t solution. The FinFETs with an amorphous TaSiN MG record the lowest on-state drain current (I on ) variability (0.37 %μm) in comparison to bulk and SOI planar MOSFETs thanks to the suppressed variability of V t (A Vt =1.32 mVμm), drain induced barrier lowering (DIBL) and trans-conductance (G m ). Back-biasing through the SOTB provides excellent V t controllability keeping the low V t variability in contrast to V t tuning by fin channel doping.

Variability of TiN FinFET performance is comprehensively studied. It is found that the variation of the in the FinFET occurs and the standard deviations of the of nMOS and pMOS FinFETs are almost the same. From the analytical results, it is found that the variation of the TiN FinFET is due to the work function variation (WFV) of TiN metal gate. The WFV is also responsible for the on-current variation.

An independent-double-gate (IDG) fin-type MOSFET (FinFET) SRAM has been successfully fabricated with considerable leakage current reduction. The new SRAM consists of IDG-FinFETs which have flexible V th controllability. The IDG-FinFET with a TiN metal gate is fabricated by a newly developed gate-separation etching process. By appropriately controlling the V th of the IDG-FinFET, we have successfully demonstrated the reduction of the leakage current and power consumption of the SRAM circuitry.

A compact model (CM) for fin-type FETs (FinFETs) was successfully developed and applied to variability analysis of a fabricated state-of-the-art metal-gate (MG) FinFET. By combining the statistical measurements with the CM calibration, V th variation was, for the first time, broken down into structure-based (silicon fin thickness and gate length) and material-based (gate work function) components. As a result, the measured variation of MG FinFET performance was successfully reproduced by the CM. Characterization using the CM with the measured statistical data provides insight on the gate work function variation of 16 meV in short-channel molybdenum (Mo) gate FinFETs.

A Ta/Mo interdiffusion dual metal gate technology was successfully introduced to FinFET fabrication. The advantage of the proposed technology was examined by using the gate-first process without a metal-etch off step. The Ta/Mo gated nMOS FinFET with a reduced threshold voltage and the Mo gated pMOS FinFET exhibited symmetrical v alues of (0.31/0.36 V), which are desirable for the FinFET CMOS circuit operation with enhanced current drivability. It was also confirmed that the Ta/Mo interdiffusion process causes no degradation in the carrier mobility.

We investigated channel doping in fin-type double-gate (DG) MOSFETs. We demonstrated through experiments that the threshold voltage was more sensitive to the dopants in the accumulation mode than in the inversion mode. We also found that significant deviation in the threshold voltage from the expected value arose in ultrathin fin-type DG MOSFETs. We attributed this phenomenon to the unexpected dopant loss from the ultrathin channels due to segregation. This finding means that careful doping adjustments must be made in ultrathin-channel devices.

Cointegration of titanium nitride (TiN)-gate high-performance tied-gate three-terminal FinFETs with symmetric gate-oxide thicknesses (tox1=tox2=1.7 nm) and variable threshold-voltage Vth independent-gate four-terminal (4T) FinFETs with asymmetric gate-oxide thicknesses (tox1=1.7 nm for the driving-gate-oxide, and tox2=3.4 or 7.0 nm for the control-gate-oxide) has been successfully developed using conventional reactive sputtering, two-step Si-fin and gate-oxide formation, and resist etch-back processes. A significantly improved subthreshold slope and an extremely low OFF-state current Ioff are experimentally confirmed in the asymmetric gate-oxide thickness 4T FinFETs by increasing the control-gate-oxide thickness to twice or more the driving-gate-oxide thickness. The developed techniques are attractive for high-performance and low-power FinFET very large-scale integration circuits

Dynamically power-controllable CMOS inverters have been successfully demonstrated using separated-gate four-terminal (4T) FinFETs. The threshold voltages of the both pMOS and nMOS FinFETs can be flexibly controlled by applying a bias voltage to the control-gate. We demonstrate for the first time that the power consumption of the CMOS inverter can be dynamically controlled using the variable threshold voltage provided by the 4T-FinFET. These results strongly suggest the advantage of the power-managed CMOS circuits using 4T-FinFETs

A vertical ultrathin-channel (UTC) formation process using a low-energy neutral beam etching (NBE) for a double-gate (DG) metal–oxide–semiconductor field-effect transistor (MOSFET) is proposed for the first time. The NBE can perfectly eliminate the charge build-up and photon radiation damages from the plasma. By utilizing the NBE, fin-type vertical MOSFETs with damage-less smooth sidewalls were successfully fabricated. The fabricated FinFETs realized higher electron mobility than that using a conventional reactive ion etching. The improved mobility is well explained by the atomically-flat surface utilizing by the NBE.

The impact of heated ion implantation (I/I) technology on metal-gate (MG)/high-k (HK) CMOS SOI FinFET performance and reliability has been thoroughly investigated. It was demonstrated that heated I/I brings perfect crystallization after annealing even in ultrathin Si channel. For the first time, it was found that heated I/I dramatically improves the characteristics such as Ion-Ioff, Vth variability, and bias temperature instability (BTI) for both nMOS and pMOS FinFETs in comparison with conventional room temperature I/I.

In this paper, as a further study, we fabricated charge trapping type SOI-FinFET flash memories with different blocking layers of Al2O3 and SiO2, and comparatively investigate their electrical characteristics.

We have successfully demonstrated a Vth controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate. It is revealed that the Vth of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the Vth controllability in terms of the size dependence such as the gate length (LG) and the fin width (TFin).

We report guidelines for symmetric threshold voltage (V th ) in double gate (DG) tunnel FinFETs (tFinFETs) with single and dual metal gate electrodes. To realize the symmetric V th =±0.2V, the work function difference (ΔΦ m ) of each gate electrode in n- and p-type tFinFETs with a nondoped Si channel must be 1.34 eV, indicating that tuning the effective work functions in the dual metal gates is difficult. By adding Ge in the channel, the work function required in Ge-channel p-tFinFETs can be reduced to 4.46 eV, furthermore, ΔΦ m required to realize a symmetric V th in n- and p-type tFinFETs can be as small as the minimum value of 0.28 e V. This result means that a symmetric V th is realized in realistic dual metal gate materials by adding Ge. By using our independent DG tFinFETs with a novel source profile, a symmetric V th can be realized in a single metal gate in a Ge channel.