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Nickel-titanium alloys have been widely used in biomedical, aerospace and other fields due to their shape memory effect, superelastic effect, as well as biocompatible and elasto-thermal properties. Additive manufacturing (AM) technology can form complex and fine structures, which greatly expands the application range of Ni-Ti alloy. In this study, the development trend of additive manufactured Ni-Ti alloy was analyzed. Subsequently, the most widely used selective laser melting (SLM) process for forming Ni-Ti alloy was summarized. Especially, the relationship between Ni-Ti alloy materials, SLM processing parameters, microstructure and properties of Ni-Ti alloy formed by SLM was revealed. The research status of Ni-Ti alloy formed by wire arc additive manufacturing (WAAM), electron beam melting (EBM), directional energy dedication (DED), selective laser sintering (SLS) and other AM processes was briefly described, and its mechanical properties were emphatically expounded. Finally, several suggestions concerning Ni-Ti alloy material preparation, structure design, forming technology and forming equipment in the future were put forward in order to accelerate the engineering application process of additive manufactured Ni-Ti alloy. This study provides a useful reference for scientific research and engineering application of additive manufactured Ni-Ti alloys.

Time-varying characteristic of wireless channel plays an important role in the design of a reliable and efficient modern communication system. Measurement and modeling is often used to estimate channel behavior due to higher complexity in developing theoretical analysis for such channels. Comparing with narrowband system, broadband micro-power system achieves more excellent performance in both data rate and stability. In this paper, an integrated communication system employing broadband micro-power signal has been established to survey the fading channel. According to the measuring data, reliable models have been proposed to illustrate the features of various channels.

Usually on the top of Smart Chip covered with active shielding layer to prevent invasive physical exploration tampering attacks on part of the chip’s function modules, to obtain the chip’s critical storage data and sensitive information. This paper introduces a design based on UMC55 technology, and applied to the safety chip active shielding layer method for layout design, the layout design from the two aspects of the metal shielding line and shielding layer detecting circuit, using the minimum size advantage and layout design process when the depth of hidden shielding line interface and port order connection method and greatly increased the difficulty of physical attack. The layout design can withstand most of the current FIB physical attack technology, and has been applied to the actual smart card design, and it has important practical significance for the security design and attack of the chip.

With the rapid development of IoT technology in recent years, higher requirements have been put forward for wireless communication technology. Low Power Wide Area Network (LPWAN) technology is emerging rapidly, the technology is characterized by low power consumption, low bandwidth, long-distance, and a large number of connections, and is specifically designed for Internet of Things applications. LoRa (Low Power Long Range Transceiver), as a typical representative of LPWAN technology, has been widely concerned and studied. This paper analyzes the performance of LoRa modulation in the tree topology network and analyzes the performance of LoRa modulation in the imperfect environment for point-to-point communication and multipoint-to-point communication. From theoretical analysis and performance simulation, it can be seen that the influence of frequency offset or multipath fading on LoRa signal is very obvious. However, when LoRa modulation is used for networking, multi-user interference will be introduced. Under the influence of many imperfect factors, the signal receiver performance of LoRa modulation will be difficult to guarantee. Because of these effects, Coordinated Multiple Points based on Timing Delay (DCoMP) is presented. Multiple nodes close to each other send the same data to the target node. Due to the inaccurate synchronization between nodes, there will be a certain relative delay when sending signals to the same target node. After the receiving node combines the signals of multiple nodes according to different relative delays, the reception performance of the signals can be improved. At the same time, the cooperative node can also actively adjust the signal sending time to improve the reception performance of the receiving node signal merging algorithm. LoRa modulation, by using DCoMP transmission, improves the reception of signals and thus the overall capacity of the system. Through the analysis of multipoint communication and single point communication, this paper is of great help to LoRa network deployment.

As the integration of mainstream system on chips (SoCs) continues to increase, input/output (I/O) multiplexing technology is commonly used in SoC chips. For complex SoC circuits, the verification goals of I/O multiplexing circuits are comprehensive, fast, simple and efficient. When using traditional system-level simulation verification to verify the I/O reuse function, it is necessary to write scenario cases at the system level and then perform related assertion verification, which requires a lot of time and manpower. In this article, a static formal verification method is used to verify the I/O multiplexing at the chip level using VC Formal Connectivity Checking (CC). In the early stage of the verification, the I/O reuse was verified for connectivity, and the toggle coverage was also collected. During the verification process, there is no need to build a verification bench and write verification cases, which greatly saves verification man-hours and improves the verification quality.

The design of an MCU chip Bootloader program is introduced, and a UVM-based verification environment for interactive communication between the UART VIP and the Bootloader is built. The Bootloader design is simple and convenient, and has a strong security. The designed Bootloader can realize the import of interactive applications to the MCU chip through the interconnection of the UART interface and the computer RS232 interface, which is convenient for upgrading and maintaining the embedded programs in practical applications. Before the tape-out process, the UART VIP is used to simulate the host computer operation to pre-test whether the Bootloader meets the design expectations, thus reducing the risk of tape-out failure. The application of the UVM verification methodology makes the Bootloader’s verification environment more portable, and make it more convenient to construct complex verification scenarios.

This article introduces an endpoint function verification scheme in the USB communication protocol. When testing the underlying communication protocol, the Ellisys test equipment is generally used to collect USB communication data. In this solution, the Ellisys test equipment is used to simulate a Host to send instructions to the USB device on endpoint zero or non-zero endpoint. Such as sending USB Standard requests on endpoint zero, sending command requests on non-zero endpoints, etc. Using this scheme, command requests can be designed according to test requirements through software programming, and can be used to verify USB device endpoint data sending and receiving, processing functions, and collect USB devices in real time according to different timing characteristics communication data with Host, including communication time, specific command parameters, etc. It supports four transfer types on USB bus. By selecting the endpoint corresponding to the transfer type, it sends command requests to it, including status switching, command issuance, realize the process of communication and data interaction between the test software and the device under test.

The serial peripheral interface (SPI) is an important module for realizing communication between the APB bus in the SOC chip and peripheral SPI devices. Therefore, efficient and sufficient verification of the function of the SPI module is very important for the design and manufacture of the SOC chip. In this article, a verification environment for SPI module is built based on universal verification methodology (UVM). By introducing the register abstraction layer (RAL), the efficiency of register attribute checking and configuration is greatly improved. In addition, the use of constrained random excitation and automatic result comparison function has realized the full verification of the SPI function, with a coverage rate of 100%. Finally, the verification environment of the SPI module has been successfully migrated to the SOC verification environment.

SM9 is an identity-based cryptography and constitutes an important part of Chinese commercial cryptography system. It can avoid the complicated PKI system certificate management problems and provides new solution for IoT (Internet of Things) security applications. But SM9 needs the trusted third party KGC (Key Generator Center) to generate and manage the key for the user. So, key update is very troublesome. In order to solve the problem of SM9 key update, this paper proposes a decentralized identity authentication and key management scheme using block chain technology. In the scenario, the user only needs the IGC (Identity Generator Center) to generate its identifier and the key for the first time. Then, the user can automatically update the key. In the process, identifier remains the same as public key and only the private key and parameters update, so it is quite convenient for identity authentication. This paper redefines data structure of the transaction and each key update process is recorded in the chain blocks in the form of transaction. The block chain can guarantee the security and reliability of key update process since it can’t be tampered with. The research in this paper is quite valuable for the identity authentication and key management in decentralized IoT application scenarios.

Preprocessing is an important first step in side-channel attacks, especially for template attacks. Typical processing techniques, such as Principal Component Analysis (PCA) and Singular Spectrum Analysis (SSA), mainly aim to reduce noise and/or extract useful information from raw data, and they are barely robust to tolerate differences between profiling and target traces. In this paper, we propose an efficient and easy-to-implement approach to preprocessing by applying the data augmentation method from deep learning, whose appropriate parameters can be efficiently determined using a simple validation. Our trace augmentation method, when added prior to existing profiling methods, significantly enhances robustness and improves performance of the attacks. Simulation-based experiments show that our approach not only results in a more robust profiling (even show an enhancement to the known robust profilings), but also works well in the ideal scenario (no distortions between profiling and target traces). The results of FPGA-based and software experiments are consistent to the ones of simulation-based counterparts. Thus, we conclude that the proposed augmentation method is an efficient performance-boosting add-on to profiled side-channel attacks in real world.

SM4, a proposed commercial block cipher to be used in IEEE 802.11i standard, has been widely performed in the Chinese National Standard for Wireless LAN WAPI (Wired Authentication and Privacy Infrastructure). Although it provides mathematical security in theory, implementation of the algorithm can be vulnerable to some side-channel analysis, especially Differential Power Analysis (DPA). To counter this kind of attacks, various masking schemes and other countermeasures have been well developed. In this paper, we propose and implement a new masking scheme for SM4 to defend DPA-like attacks. This countermeasure is based on Boolean matrix product masking which is a provable security masking scheme and consists of both additive Boolean masking and inner product masking directions. We develop a first variant version of this full-masking scheme on SM4 and implement it particularly on ATMega2560 in pure C language. Though the security potential of this matrix masking scheme has been proved, we evaluate performance and efficiency of this masking scheme through experiments in the paper.

SM9 is identity-based cryptography designed by bilinear pairing, which can effectively solve the certificates management problems of the PKI and constitutes an important part of Chinese commercial cryptography system. Due to the high complexity of bilinear pairing, SM9 still faces the problem of low efficiency, especially in resource-constrained environments, so performance becomes the key factor that hinders its wide application. This paper has explicitly analyzed detailed computation process of Miller loop in SM9 bilinear pairings and proposed the optimization methods for the point addition, point doubling and line function computation on BN curves. Furthermore, we compare the computational cost of Miller loop under the projective coordinate system and the Jacobian coordinate system and the results show that the latter can improve the efficiency by 5% than the former. The research is very important to optimize the SM9 the performance.

It does not consider how similar words are distributed in the text that the traditional algorithm of the VSM characteristic weighs - TF-IDF. For solving the problem, from the semantic view and combined optimization techniques, a improved IF-IDF Weighting algorithm is proposed. This algorithm can effectually reduce the subjective factors of faceted classification, and further improve the effect of current most text clustering algorithm that based on Vector Space Model (VSM). By experiments, the algorithm is feasible and effective, and to some extent, the precision ratio and recall ratio of text clustering is enhanced.