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Conference of Symposium on Nonvolatile Memories 4 - 228th ECS Meeting ; Conference Date: 11 October 2015 Through 15 October 2015; Conference Code:115963; International audience; Oxide based resistive memories (OxRAMs) is one of the potential candidates for non-volatile logic circuits and neuromorphic circuits in the applications of wearable devices, internet of things (IoT), cloud computing, and big-data processing. One of the main OxRAMs issue is the noise behavior of the high resistance state (HRS). In this work, we will demonstrate a hybrid (CMOS logic plus ReRAM devices) Non Volatile Flip Flop designed to face OxRAM variability. Concerning neuromorphic circuits, we will focus on the impact of resistance variability on the performance of Convolutional Neural Network (CNN) systems for visual pattern recognition applications.

As the feature size of transistors gets smaller, fabricating them becomes challenging. Manufacturing process follows various corrective design-for-manufacturing (DFM) steps to avoid shorts/opens/bridges. However, it is not possible to completely eliminate the possibility of such defects. If spare units are not present to replace the defective parts, then such failures cause yield loss. In this paper, we present a fault tolerant technique to leverage the redundancy present in high speed regular circuits such as Kogge-Stone adder (KSA). Due to its regularity and speed, KSA is widely used in ALU design. In KSA, the carries are computed fast by computing them in parallel. Our technique is based on the fact that even and odd carries are mutually exclusive. Therefore, defect in even bit can only corrupt the even Sum outputs whereas the odd Sums are computed correctly (and vice versa). To efficiently utilize the above property of KSA in presence of defects, we perform addition in two- clock cycles. In cycle-1, one of the correct set of bits (even or odd) are computed and stored at output registers. In cycle-2, the operands are shifted by one bit and the remaining sets of bits (odd or even) are computed and stored. This allows us to tolerate the defect at the cost of throughput degradation while maintaining high frequency and yield. The proposed technique can tolerate any number of faults as long as they are confined to either even or odd bits (but not in both). Further, this technique is applicable for any type of fault model (stuck-at, bridging, complete opens/shorts). We performed simulations on 64-bit KSA using 180nm devices. The results indicate that the proposed technique incur less that 1% area overhead. Note that there is very little throughput degradation (0.3%) for the fault-free adders. The proposed technique utilizes the existing scan flip-flops for storage and shifting operation to minimize the area/performance overhead. Finally, the proposed technique is used in a superscalar processor, whereby the faulty adder is assigned lower priority than fault-free adders to reduce the overall throughput degradation. Experiments performed using Simplescalar for a superscalar pipeline (with four integer adders) show throughput degradation of 0.5% in the presence of a single defective adder.

A thermistor-based temperature indicator is described, which produces a parallel digital output proportional to absolute temperature, using the principle of a reciprocal time generator. The instrument is suitable for fast measurement of temperature, with easy facility of range adjustment. Temperature indication in degrees Celsius is also possible, using additional simple circuitry. Experimental results are given in support of the proposed method. ? 1994 IEEE