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Semiconductor products used in high-performance computing (HPC) and artificial intelligence (AI) applications require higher memory bandwidth, greater input/output (I/O) count, better power delivery network (PDN) performance and improved heat dissipation characteristics. To meet these requirements, a 2.5D package architecture with a Through Silicon Via (TSV)-bearing silicon (Si) interposer is mainly used in volume production. However, a redistribution layer (RDL) interposer is emerging as a cost effective and higher performance alternative. To implement an improved high-performance, multifunctional interposer, S-Connect technology has been developed that uses a multi-chip, fan-out interposer with various functionalities, such as a die-to-die (D2D) connection, where integrated passive devices (IPDs) and active devices can be integrated. If active devices are included in the interposer, S-Connect technology enables a 3D system where multiple active chips are vertically integrated. In this paper, the S-Connect design differences from the existing 2.5D package using Si interposer with TSVs and its fabrication process flow are explained. S-Connect technology provides manufacturing flexibility to apply various types of interconnects. Two different connect features will be discussed. Firstly, a Si connect will be explored having a back end of line (BEOL) and TSV approach that can provide the same die-to-die routing with smaller than $1-\mu \mathrm{m}$ line/space (L/S) and vertical connections as a Si interposer. The second option uses a multilayer RDL, which can be fabricated on Si, glass and even on the epoxy mold compound (EMC). The RDL can also provide vertical interconnects such as TSVs in Si. For demonstration, a test vehicle (TV) with one logic chip and two memory chips mounted on a multi-chip, fan-out interposer with an area approximately 1.5 times larger than the reticle was used. The interposer consists of two connect chips with $2-\mu \mathrm{m}$ L/S RDL and 6 mechanical IPDs located under the logic die. Two types of the connect chips were used - RDL on Si wafer and RDL on EMC having TMVs. The top die to interposer joints were made using $\mu$ -bumps with $25-\mu \mathrm{m}$ size on a $45-\mu \mathrm{m}$ pitch in the logic and $25-\mu \mathrm{m}$ size on a $55-\mu \mathrm{m}$ pitch in the memory die. Both the top and bottom sides of the fan-out interposer have a single layer of RDL. To interconnect the bottom side of the interposer and the package substrate, copper (Cu) pillar C4 bumps at $150-\mu \mathrm{m}$ pitch were formed. Once the top die and interposer assembly is complete, the subsequent processes are standard flip chip ball grid array (FCBGA) process flows. Moisture sensitivity and long-term reliability test results will be presented as well as warpage behavior, which is critical for the large body packages. Lastly, the advantages of the S-Connect package will be compared to other 2.5D and flip chip solutions in terms of manufacturability, ability to integrate multiple functionalities and cost.

In spite of a great success of stacked package (PoP) in the market, some reliability issues have been raised. One of them is a board level reliability evaluation of PoP with 2nd level underfill. Some customers have issued the application of 2nd level underfill for PoP to improve the reliability for drop test. Unfortunately, using the 2nd level underfill for PoP package causes reducing the reliability for thermal cycling test. Under temperature cycling test, PoP with 2nd level underfill shows early failures before 300 cycles whereas most of samples without 2nd level underfill survived over 1000 cycles. This paper discusses the optimal underfill material for PoP to achieve reliable board level performances. Various factors such as filler content, CTE, Tg and underfill dispensing pattern are considered. As a result, it is found that lower CTE & higher Tg underfill are better than other factors for temperature cycle performance. Non filler type underfill was passed 500 cycles for PoP but filler type underfill was passed 2500 cycles under the JEDEC JESD22-104C Condition G (-40'C~125'C, 1 cycle/hour). Especially one of non filler type underfill material with different dispensing pattern passed 1730 cycles without any failure. We assumed that this results caused by specific dispensing patterns & damping effect of non filler type underfill. In the drop test, most of underfill materials have better performances than no underfill case. Especially, several no filler type underfills have no failure until 400 drops.

This paper discusses the optimal design for PS-etCSP to achieve reliable thermal fatigue life of solder joint. For this purpose design analysis was performed using both simulation and experimental approaches. Since reduction of warpage is most critical issue to ensure good solder joint connection for thin packages, parametric study was performed to find the optimal set of package outline dimensions using finite element method. Next to find the optimal design far solder joint reliability, 3D FEA fatigue model was established with non linear material properties of solder joint. Various factors such as ball land size, motherboard thickness and surface mounting type were studied. As a result, it is found that thin die with small size and small CTE molding compound is better for minimizing package warpage and larger opening size, thinner board and single mounting on board are good for solder joint reliability. The stack of package however has little effect on solder joint reliability. The effects of board thickness and surface mounting type (single/double) were investigated in terms of assembly stiffness and solder joint reliability. Simulation results showed good correspondence with experiment. The fatigue life and failure location predicted by simulation agreed well with experimental data. The fatigue life of optimal design was 1225 cycles for single PS-etCSP and 990 cycles for stacked PS-etCSP with single side mounting on board under the thermal cycling loading of temperature of -40/spl deg/C/spl sim/125/spl deg/C. Subsequently it can be concluded that optimal design of PS-etCSP can meet the requirement for most portable product applications.