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1. Architecture d'un processeur multiflot orienté temps-réel

Author

Jonathan Barre, Christine Rochange, and Pascal Sainrat

Subjects
business.industry, Computer science, Concurrency, Thread (computing), Simultaneous multithreading, computer.software_genre, Execution time, Microarchitecture, Worst-case execution time, Embedded system, Operating system, Predictability, Architecture, business, computer
Abstract

Simultaneous multithreading (SMT) processors might be good candidates to fulfill the ever increasing performance needs of embedded applications. However, off-the-shelves SMT architectures do not fit the timing predictability requirements of hard real-time systems: to schedule critical threads so that they are guaranteed to meet their deadlines, it is necessary to estimate their Worst-Case Execution Times which is not possible when simultaneous threads might interfere. In this paper, we propose an SMT architecture designed to enforce isolation of hard real-time threads so that their worst-case execution time can be safely estimated. We report experimental results that show that this architecture still provides a high level of performance and we give an insight into how the thread isolation feature could be controlled by a real-time task scheduler.

Published
2010
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2. Parallelizing industrial hard real-time applications for the parMERASA multicore

Author

Jörg Mische, Hugues Cassé, Florian Kluge, Sebastian Kehr, Sascha Uhrig, Francisco J. Cazorla, Armelle Bonenfant, Bert Böddeker, Lucie Matusova, Jaume Abella, Christian Bradatsch, Milos Panic, Zai Jian Jia Li, Mike Gerdes, Theo Ungerer, Carles Hernandez, Christine Rochange, Martin Frieb, Eduardo Quinones, David George, Zlatko Petrov, Ian Broster, Pavel Zaykov, Ralf Jahr, Hans Regler, Pascal Sainrat, Arthur Pyka, Haluk Ozaktas, Andreas Hugl, Alexander Stegmeier, Nick Lay, Mathias Rohde, Institute of Computer Science - University of Augsburg (ICS), Universität Augsburg [Augsburg], University of Augsburg [Augsburg], Honeywell Technology Solutions international development centre, Brno (HTS), Honeywell International S.r.o. [Prague], DENSO (JAPAN), Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Technische Universität Dortmund [Dortmund] (TU), project partners : Honeywell International s.r.o., Czech Republic, DENSO AUTOMOTIVE Deutschland GmbH,Germany, BAUER Maschinen GmbH, Germany, Rapita Systems Ltd, UK, Barcelona Supercomputing Center, Spain, Université Paul Sabatier, Toulouse, France, Technical University of Dortmund, Germany, and and University of Augsburg, Germany

Subjects
010302 applied physics, Multi-core processor, Control algorithm, business.industry, Computer science, Parallel design, Real-time computing, Automotive industry, Program transformation, 02 engineering and technology, Parallel computing, 01 natural sciences, 020202 computer hardware & architecture, Automatic parallelization, Hardware and Architecture, Embedded system, 0103 physical sciences, Management system, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], Motion planning, business, Software
Abstract

International audience; The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore processor. A pattern-supported parallelization approach was developed to ease sequential to parallel program transformation based on parallel design patterns that are timing analyzable. The parallelization approach was applied to parallelize the following industrial hard real-time programs: 3D path planning and stereo navigation algorithms (Honeywell International s.r.o.), control algorithm for a dynamic compaction machine (BAUER Maschinen GmbH), and a diesel engine management system (DENSO AUTOMOTIVE Deutschland GmbH). This article focuses on the parallelization approach, experiences during parallelization with the applications, and quantitative results reached by simulation, by static WCET analysis with the OTAWA tool, and by measurement-based WCET analysis with the RapiTime tool.

Published
2016
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3. Case study: Performance and WCET analysis for parallelised avionic applications with ODC2

Author

Pavel Zaykov, Sascha Uhrig, Christine Rochange, Arthur Pyka, Haluk Ozaktas, and Hugues Cassé

Subjects
Hardware_MEMORYSTRUCTURES, business.industry, Computer science, Cache coloring, CPU cache, 02 engineering and technology, Parallel computing, Cache pollution, 020202 computer hardware & architecture, Smart Cache, Cache invalidation, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Cache, business, Cache algorithms, Cache coherence
Abstract

In a hard Real-Time (HRT) domain such as avionics, the high application performance is as important as delivering a predictable execution time. More precisely, the performance is defined by the application Worst-Case Execution Time (WCET). A common practice to boost the application performance in general purpose computing is by parallelisation and parallel execution on a shared memory multicore processor. Hence, local caches, used for bridging the long memory latency, need to allow coherent accesses to shared data. Conventional cache coherence protocols impede a suitable timing analysis because of multiple reasons. In this paper, we introduce an avionics case study to analyse the applicability of the earlier proposed On-Demand Coherent Cache (ODC2). We experiment with a 3D Path Planning (3DPP) application executed on a multicore processor. By varying the number of cores and the level of application parallelism, we compare and analyse observed average case execution times (ACET) of the 3DPP application with ODC2, Uncached (bypassing the cache for shared data), and Cache Flush (software-triggered cache invalidation) configurations. The ACET results of the 3DPP application suggest that ODC2 significantly outperforms the Uncached configuration by 1.53 times and Cache Flush by 2.15 times. Furthermore, we study the WCET speedup of the 3DPP application by applying a static analysis OTAWA tool. In terms of worst-case performance, the ODC2 achieves a speedup of 1.63 compared to Uncached and 3.17 compared to Cache Flush configurations.

Published
2015
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4. Distributed run-time WCET controller for concurrent critical tasks in mixed-critical systems

Author

Claire Pagetti, Christine Rochange, Sylvain Girbal, Angeliki Kritikakou, Madeleine Faugere, Matthieu Roy, Daniel Gracia Perez, Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA), ONERA - The French Aerospace Lab [Toulouse], ONERA, Équipe Tolérance aux fautes et Sûreté de Fonctionnement informatique (LAAS-TSF), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Thales Research and Technology [Palaiseau], THALES, Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), and THALES [France]

Subjects
business.industry, Computer science, Distributed computing, 020208 electrical & electronic engineering, 02 engineering and technology, 020202 computer hardware & architecture, Task (computing), Software, Criticality, Control theory, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Predictability, [INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC], business
Abstract

International audience; When integrating mixed critical systems on a multi/many-core, one challenge is to ensure predictability for high criticality tasks and an increased utilization for low criticality tasks. In this paper, we address this problem when several high criticality tasks with different deadlines, periods and offsets are concurrently executed on the system. We propose a distributed run-time WCET controller that works as follows: (1) locally, each critical task regularly checks if the interferences due to the low criticality tasks can be tolerated, otherwise it decides their suspension; (2) globally, a master suspends and restarts the low criticality tasks based on the received requests from the critical tasks. Our approach has been implemented as a software controller on a real multi-core COTS system with significant gains.

Published
2014
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5. Effects of structured parallelism by parallel design patterns on embedded hard real-time systems

Author

Theo Ungerer, Pavel Zaykov, Ralf Jahr, Haluk Ozaktas, Mike Gerdes, Christine Rochange, University of Augsburg [Augsburg], Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, and Honeywell International S.r.o. [Prague]

Subjects
Pipelines, business.industry, Computer science, Data parallelism, Parallel design, Message systems, Real-time computing, Task parallelism, Static timing analysis, 02 engineering and technology, Parallel computing, Synchronization, Structured parallelism, 020202 computer hardware & architecture, Software, Parallel processing (DSP implementation), Synchronization (computer science), Parallel processing, 0202 electrical engineering, electronic engineering, information engineering, [INFO]Computer Science [cs], 020201 artificial intelligence & image processing, business, Real-time systems
Abstract

International audience; Parallel multi-threaded applications are needed to gain advantage from multi- and many-core processors. Such processors are more frequently considered for embedded hard real-time with defined timing guarantees, too. The static timing analysis, which is one way to calculate the worst-case execution time (WCET) of parallel applications, is complex and time-consuming due to the difficulty to analyze the interferences of threads and the high annotation effort to resolve it.

Published
2014
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6. Building Timing Predictable Embedded Systems

Author

Alain Girault, Reinhard von Hanxleden, Daniel Grund, Philip Axer, Peter Marwedel, Heiko Falk, Wang Yi, Bengt Jonsson, Nan Guan, Jan Reineke, Christine Rochange, Maurice Sebastian, Reinhard Wilhelm, Rolf Ernst, Institute of Computer and Network Engineering [Braunschweig] (IDA), Technische Universität Braunschweig = Technical University of Braunschweig [Braunschweig], Universität Ulm - Ulm University [Ulm, Allemagne], Sound Programming of Adaptive Dependable Embedded Systems (SPADES), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire d'Informatique de Grenoble (LIG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF), Compiler Design Lab [Saarbrücken], Saarland University [Saarbrücken], Uppsala University, Technische Universität Dortmund [Dortmund] (TU), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Christian-Albrechts-Universität zu Kiel (CAU), Universität des Saarlandes [Saarbrücken], European Project: 214373,ICT,FP7-ICT-2007-1,ARTISTDESIGN(2007), Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Toulouse Mind & Brain Institut (TMBI), Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT), Laboratoire d'Informatique de Grenoble (LIG), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)-Université Pierre Mendès France - Grenoble 2 (UPMF)-Université Joseph Fourier - Grenoble 1 (UJF)-Inria Grenoble - Rhône-Alpes, and Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)

Subjects
safety-critical systems, resource sharing, timing analysis, business.industry, Semantics (computer science), Computer science, Distributed computing, Static timing analysis, ACM: D.: Software/D.4: OPERATING SYSTEMS/D.4.7: Organization and Design/D.4.7.4: Real-time systems and embedded systems, Instruction set, Hardware and Architecture, Multithreading, Embedded system, predictability, Programming paradigm, Systems design, embedded systems, [INFO]Computer Science [cs], [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, Predictability, business, Software, Abstraction (linguistics)
Abstract

A large class of embedded systems is distinguished from general-purpose computing systems by the need to satisfy strict requirements on timing, often under constraints on available resources. Predictable system design is concerned with the challenge of building systems for which timing requirements can be guaranteed a priori . Perhaps paradoxically, this problem has become more difficult by the introduction of performance-enhancing architectural elements, such as caches, pipelines, and multithreading, which introduce a large degree of uncertainty and make guarantees harder to provide. The intention of this article is to summarize the current state of the art in research concerning how to build predictable yet performant systems. We suggest precise definitions for the concept of “predictability”, and present predictability concerns at different abstraction levels in embedded system design. First, we consider timing predictability of processor instruction sets. Thereafter, we consider how programming languages can be equipped with predictable timing semantics, covering both a language-based approach using the synchronous programming paradigm, as well as an environment that provides timing semantics for a mainstream programming language (in this case C). We present techniques for achieving timing predictability on multicores. Finally, we discuss how to handle predictability at the level of networked embedded systems where randomly occurring errors must be considered.

Published
2014
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7. Minimizing the Cost of Synchronisations in the WCET of Real-Time Parallel Programs

Author

Christine Rochange, Pascal Sainrat, Haluk Ozaktas, Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), and Université Toulouse 1 Capitole - UT1 (FRANCE)

Subjects
Lock, business.industry, Computer science, Parallel programming, Système d'exploitation, Static timing analysis, Réseaux et télécommunications, Parallel computing, Systèmes embarqués, Software, Architectures Matérielles, business, Real-time, WCET
Abstract

Designing time-predictable architectures to support the requirements of hard real-time systems is the goal of several research projects. In this paper we assume that such platforms exist and we focus on the timing analysis of parallel real-time applications. One of the main challenges is to determine how much the delays induced by software constructs such as synchronisations can impact the worst-case execution times (WCETs) of parallel threads. In this paper, we refine state-of-the-art analysis: first, we derive more accurate estimations of stalls at critical sections; second, we introduce new locking primitives that minimise stall times on the worst-case path. Experimental results show noticeable improvements on the WCETs of benchmarks.

Published
2014

8. parMERASA -- Multi-core Execution of Parallelised Hard Real-Time Applications Supporting Analysability

Author

Arthur Pyka, Haluk Ozaktas, Dave George, João Carlos Lopes Fernandes, Hugues Cassé, Florian Kluge, Milos Panic, Pavel Zaykov, Theo Ungerer, Armelle Bonenfant, Ralf Jahr, Bert Böddeker, Zlatko Petrov, Hans Regler, Mike Gerdes, Andreas Hugl, Christian Bradatsch, Sascha Uhrig, Jaume Abella, Mathias Rohde, Sebastian Kehr, Francisco J. Cazorla, Ian Broster, Nick Lay, Christine Rochange, Pascal Sainrat, Eduardo Quinones, Jörg Mische, University of Augsburg [Augsburg], Honeywell International S.r.o. [Prague], DENSO (JAPAN), Bauer Group (GERMANY), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Rapita Systems Ltd [York], Barcelona Supercomputing Center - Centro Nacional de Supercomputacion (BSC - CNS), Universitat Politècnica de Catalunya [Barcelona] (UPC), Consejo Superior de Investigaciones Científicas [Madrid] (CSIC), Technische Universität Dortmund [Dortmund] (TU), Barcelona Supercomputing Center – Centro Nacional de Supercomputación - BSC-CNS (SPAIN), Centre National de la Recherche Scientifique - CNRS (FRANCE), Consejo Superior de Investigaciones Científicas - CSIC (SPAIN), Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Universitat Politècnica de Catalunya - UPC (SPAIN), Honeywell (USA), Rapita System (USA), Technische Universität Dortmund - TU Dortmund (GERMANY), University of Augsburg (GERMANY), Institut de Recherche en Informatique de Toulouse - IRIT (Toulouse, France), Technical University of Catalonia – Barcelona Tech (Girona, Espagne), and Institut National Polytechnique de Toulouse - INPT (FRANCE)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Computer science, Embedded systems, Parallel programming, Real-time computing, Système d'exploitation, Automotive industry, Réseaux et télécommunications, 02 engineering and technology, [INFO.INFO-NI]Computer Science [cs]/Networking and Internet Architecture [cs.NI], Many core, Architectures Matérielles, 0202 electrical engineering, electronic engineering, information engineering, Mixed criticality, Multi-core processor, Control algorithm, Multiprocessing systems, business.industry, Avionics, Systèmes embarqués, 020202 computer hardware & architecture, Embedded system, Scalability, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, 020201 artificial intelligence & image processing, [INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS], business, System software
Abstract

International audience; Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard real-time applications and running them on an embedded multi-core processor, which enables combining the requirements for high-performance with timing-predictable execution. parMERASA will provide a timing analyzable system of parallel hard real-time applications running on a scalable multicore processor. parMERASA goes one step beyond mixed criticality demands: It targets future complex control algorithms by parallelizing hard real-time programs to run on predictable multi-/many-core processors. We aim to achieve a breakthrough in techniques for parallelization of industrial hard real-time programs, provide hard real-time support in system software, WCET analysis and verification tools for multi-cores, and techniques for predictable multi-core designs with up to 64 cores.

Published
2013
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9. Hardware architecture specification and constraint-based WCET computation

Author

Mamoun Filali, Christine Rochange, Hugues Cassé, Hajer Herbegue, Institut National Polytechnique de Toulouse - Toulouse INP (FRANCE), Centre National de la Recherche Scientifique - CNRS (FRANCE), Université Toulouse III - Paul Sabatier - UT3 (FRANCE), Université Toulouse - Jean Jaurès - UT2J (FRANCE), Université Toulouse 1 Capitole - UT1 (FRANCE), Institut National Polytechnique de Toulouse - INPT (FRANCE), Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Assistance à la Certification d’Applications DIstribuées et Embarquées (IRIT-ACADIE), and Centre National de la Recherche Scientifique (CNRS)

Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR], Critical real-time systems, Computer science, computer.internet_protocol, Computation, WCET analysis, 02 engineering and technology, [INFO.INFO-SE]Computer Science [cs]/Software Engineering [cs.SE], computer.software_genre, Interface homme-machine, Instruction set, [INFO.INFO-CR]Computer Science [cs]/Cryptography and Security [cs.CR], Architectures Matérielles, 0202 electrical engineering, electronic engineering, information engineering, Génie logiciel, [INFO.INFO-HC]Computer Science [cs]/Human-Computer Interaction [cs.HC], Hardware architecture, business.industry, Programming language, Process (computing), Modular design, Static analysis, Modélisation et simulation, [INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation, Systèmes embarqués, 020202 computer hardware & architecture, Microarchitecture, Sim-nML, Cryptographie et sécurité, 020201 artificial intelligence & image processing, [INFO.INFO-ES]Computer Science [cs]/Embedded Systems, business, computer, XML
Abstract

International audience; The analysis of the worst-case execution times is necessary in the design of critical real-time systems. To get sound and precise times, the WCET analysis for these systems must be performed on binary code and based on static analysis. OTAWA, a tool providing WCET computation, uses the Sim-nML language to describe the instruction set and XML files to describe the microarchitecture. The latter information is usually inadequate to describe real architectures and, therefore, requires specific modifications, currently performed by hand, to allow correct time calculation. In this paper, we propose to extend Sim-nML in order to support the description of modern microarchitecture features along the instruction set description and to seamlessly derive the time calculation. This time computation is specified as a constraint solving problem that is automatically synthesized from the extended Sim-nML. Thanks to its declarative aspect, this approach makes easier and modular the description of complex features of microprocessors while maintaining a sound process to compute times.

Published
2013

10. The Split-Phase Synchronisation Technique: Reducing the Pessimism in the WCET Analysis of Parallelised Hard Real-Time Programs

Author

Mike Gerdes, Florian Kluge, Theo Ungerer, and Christine Rochange

Subjects
010302 applied physics, Multi-core processor, Atomicity, Computer science, business.industry, Split-phase electric power, 02 engineering and technology, Parallel computing, 01 natural sciences, Memory controller, Synchronization, 020202 computer hardware & architecture, Instruction set, Consistency (database systems), Software, 0103 physical sciences, 0202 electrical engineering, electronic engineering, information engineering, ComputerSystemsOrganization_SPECIAL-PURPOSEANDAPPLICATION-BASEDSYSTEMS, business
Abstract

In this paper we present the split-phase synchronisation technique to reduce the pessimism in the WCET analysis of parallelised hard real-time (HRT) programs on embedded multi-core processors. We implemented the split-phase synchronisation technique in the memory controller of the HRT capable MERASA multi-core processor. The split-phase synchronisation technique allows reordering memory requests and splitting of atomic RMW operations, while preserving atomicity, consistency and timing predictability. We determine the improvement of worst-case guarantees, that is the estimated upper bounds, for two parallelised HRT programs. We achieve a WCET improvement of up to 1.26 with the split-phase synchronisation technique, and an overall WCET improvement of up to 2.9 for parallel HRT programs with different software synchronisations.

Published
2012
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11. OTAWA: An Open Toolbox for Adaptive WCET Analysis

Author

Christine Rochange, Clément Ballabriga, Hugues Cassé, Pascal Sainrat, Groupe de Recherche en Architecture et Compilation pour les systèmes embarqués (IRIT-TRACES), Institut de recherche en informatique de Toulouse (IRIT), Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse III - Paul Sabatier (UT3), Sang Lyul Min, Robert Pettit, Peter Puschner, and Theo Ungerer

Subjects
Schedule, business.industry, Computer science, Distributed computing, 020207 software engineering, 02 engineering and technology, Static analysis, Worst-Case Execution Time, Toolbox, 020202 computer hardware & architecture, Task (project management), Domain (software engineering), Abstraction layer, Instruction set, Worst-case execution time, static analysis, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, [INFO.INFO-DL]Computer Science [cs]/Digital Libraries [cs.DL], business, Real-time
Abstract

International audience; The analysis of worst-case execution times has become mandatory in the design of hard real-time systems: it is absolutely necessary to know an upper bound of the execution time of each task to determine a task schedule that insures that deadlines will all be met. The OTAWA toolbox presented in this paper has been designed to host algorithms resulting from research in the domain of WCET analysis so that they can be combined to compute tight WCET estimates. It features an abstraction layer that decouples the analyses from the target hardware and from the instruction set architecture, as well as a set of functionalities that facilitate the implementation of new approaches.

Published
2010
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12. MBBA: A Multi-Bandwidth Bus Arbiter for Hard Real-Time

Author

Christine Rochange, Marianne de Michiel, Roman Bourgade, and Pascal Sainrat

Subjects
Instruction set, Multi-core processor, Worst-case execution time, business.industry, Computer science, Embedded system, Arbiter, Thread (computing), Energy consumption, Parallel computing, Local bus, business, Control bus
Abstract

Multi-core architectures are being increasingly used in embedded systems as they offer several advantages: improved hardware integration, low thermal dissipation and reduced energy consumption, while they make it possible to improve the computing power. In order to run real-time software on a multicore architecture, computing the Worst-Case Execution Time of every thread should be achievable. This notably involves bounding memory latencies by employing a predictable bus arbiter. However, state-of-the-art techniques prove to be irrelevant to schedule unbalanced workloads in which some threads require more bus bandwidth than the other ones. This paper proposes a new bus arbitration scheme that ensures that the shared bus latencies can be upper bounded. Compared to other schemes that make the bus latencies predictable, like the Round-Robin protocol, our approach defines several levels of bandwidth to meet requirements that may vary from one thread to another. Experimental results (WCET estimates) show that the worst-case bus latency is noticeably shortened, compared to Round-Robin, for the cores with highest priority that get the largest bandwidth. The relevance of the scheme is shown through an example workload composed of various benchmarks.

Published
2010
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13. Merasa: Multicore execution of hard real-time applications supporting analyzability

Author

Francisco J. Cazorla, Christine Rochange, Pascal Sainrat, Stefan Metzlaff, Hugues Cassé, Michael Houston, Theo Ungerer, Mike Gerdes, Irakli Guliashvili, Sascha Uhrig, Guillem Bernat, Eduardo Quinones, Jörg Mische, Marco Paolieri, Zlatko Petrov, Julian Wolf, and Florian Kluge

Subjects
Multi-core processor, Computer science, business.industry, Real-time computing, 02 engineering and technology, Execution time, 020202 computer hardware & architecture, Instruction set, Software, Hardware and Architecture, 0202 electrical engineering, electronic engineering, information engineering, 020201 artificial intelligence & image processing, Electrical and Electronic Engineering, business, System software
Abstract

The Merasa project aims to achieve a breakthrough in hardware design, hard real-time support in system software, and worst-case execution time analysis tools for embedded multicore processors. The project focuses on developing multicore processor designs for hard real-time embedded systems and techniques to guarantee the analyzability and timing predictability of every feature provided by the processor.

Published
2010
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14. RTOS support for parallel execution of hard real-time applications on the MERASA multi-core processor

Author

Mike Gerdes, Hugues Cassé, Sascha Uhrig, Julian Wolf, Florian Kluge, Theo Ungerer, Stefan Metzlaff, Jörg Mische, Pascal Sainrat, and Christine Rochange

Subjects
Multi-core processor, Computer science, business.industry, Real-time computing, 02 engineering and technology, Yarn, Thread (computing), computer.software_genre, Application software, Execution time, 020202 computer hardware & architecture, Low energy, Embedded system, visual_art, 0202 electrical engineering, electronic engineering, information engineering, visual_art.visual_art_medium, Operating system, 020201 artificial intelligence & image processing, business, computer, Real-time operating system, System software
Abstract

Multi-cores are the contemporary solution to satisfy high performance and low energy demands in general and embedded computing domains. However, currently available multi-cores are not feasible to be used in safety-critical environments with hard real-time constraints. Hard real-time tasks running on different cores must be executed in isolation or their interferences must be time-bounded. Thus, new requirements also arise for a real-time operating system (RTOS), in particular if the parallel execution of hard real-time applications should be supported. In this paper we focus on the MERASA system software as an RTOS developed on top of the MERASA multi-core processor. The MERASA system software fulfils the requirements for time-bounded execution of parallel hard real-time tasks. In particular we focus on thread control with synchronisation mechanisms, memory management and resource management requirements. Our evaluations show that all system software functions are time-bounded by a worst-case execution time (WCET) analysis.

Published
2010

15. An architecture for the simultaneous execution of hard real-time threads

Author

Christine Rochange, Jonathan Barre, and Pascal Sainrat

Subjects
Computer science, business.industry, Yarn, Thread (computing), Simultaneous multithreading, Scheduling (computing), visual_art, Embedded system, Multithreading, visual_art.visual_art_medium, Architecture, Predictability, Software architecture, business
Abstract

Simultaneous multithreading (SMT) processors might be good candidates to fulfill the ever increasing performance needs of embedded applications. However, off-the-shelves SMT architectures do not fit the timing predictability requirements of hard real-time systems: to schedule critical threads so that they are guaranteed to meet their deadlines, it is necessary to estimate their worst-case execution times which is not possible when simultaneous threads might interfere. In this paper, we propose an SMT architecture designed to enforce isolation between hard real-time threads so that their worst-case execution time can be safely estimated. We report experimental results that show that this architecture still provides a high level of performance and we give an insight into how the thread isolation feature could be controlled by a real-time task scheduler.

Published
2008
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16. A time-predictable execution mode for superscalar pipelines with instruction prescheduling

Author

Christine Rochange and Pascal Sainrat

Subjects
Pipeline transport, Focus (computing), Mode (computer interface), business.industry, Computer science, Embedded system, Limit (music), Static analysis, Predictability, business, Pipeline (software), Microarchitecture
Abstract

The time predictability of the components of a real-time system is required whenever it must be guaranteed that deadlines will be met. Research on techniques to evaluate the Worst-Case Execution Time (WCET) of programs has received much attention these last years but current high-performance processors prove to be hard to model both safely and tightly. We acknowledge the difficulty of taking into account more and more dynamic mechanisms within static analysis and this motivates our approach that consists in making the processor fit WCET estimation techniques. We focus on out-of-order superscalar pipelines and we propose to regulate the instruction flow so that subsequent basic blocks execute independently one of each other. This would allow any WCET estimation tool to limit the measurement to individual basic blocks.

Published
2005
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17. Pushing away the communication bottleneck with optical interconnects in symmetric multiprocessors

Author

Jacques H. Collet, Daniel Litaize, Wissam Hlayhel, and Christine Rochange

Subjects
Hardware_MEMORYSTRUCTURES, Memory hierarchy, Chipset, business.industry, Computer science, Distributed computing, Optical engineering, Computer data storage, Bandwidth (computing), Context (language use), Optical performance monitoring, business, Bottleneck
Abstract

We analyze the bandwidth needed for transmitting the addresses in future symmetric multiprocessor machines (SMP), constructed around a shared bus due to the critical obligation to preserve the coherence of the memory hierarchy. We show that an address-transaction bandwidth as high as several hundreds of Gbit/s will be necessary not to slow down the execution of most applications in large SMP's. This communication bandwidth seems incompatible with the operation constraints of shared electrical busses, making necessary the search for other implementations of the address transmission network. We consider the introduction of optical interconnects (OI) in this context. We review several solutions, in the ascending order of complexity of the optical subsystems as one critical issue concerns the degree of sophistication of the optical solutions and their cost. We first consider simple point to point OI's for a SMP chipset. The interest for OI's comes from the low energy consumption and from the possibility, in the future, to integrate several thousands of optical input/outputs per electronic chip. The we consider the implementation of an optical bus that is a multipoint optical line involving more optical functionality. We discuss the possibility of multiple accesses to the bus, and the constraints related to the necessity to maintain the coherence of caches.© (2000) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Published
2000
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