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To address the integration of software threads and hardware accelerators into the Linux Operating System (OS) programming models, an accelerator architecture is proposed, based on micro-programmable hardware system calls, which fully export these resources into the Linux OS user-space through a design-specific virtual file system. The proposed HAL-ASOS accelerator model is split into a user-defined Hardware Task and a parameterizable Hardware Kernel with three differentiated transfer channels, aiming to explore distinct BUS technology interfaces and promote the accelerator to a first-class computing unit. This paper focuses on the Hardware Kernel and mainly its microcode control unit, which will leverage the elasticity to naturally evolve with Linux OS through key differentiating capabilities of field programmable gate arrays (FPGAs) when compared to the state of the art. To comply with the evolutive nature of Linux OS, or any Hardware Task incremental features, the proposed model generates page-faults signaling runtime errors that are handled at the kernel level as part of the virtual file system runtime. To evaluate the accelerator model’s programmability and its performance, a client-side application based on the AES 128-bit algorithm was implemented. Experiments demonstrate a flexible design approach in terms of hardware and software reconfiguration and significant performance increases consistent with rising processing demands or clock design frequencies., This work has been supported by FCT-Fundação para a Ciência e Tecnologia within the R&D Units Project Scope: UIDB/00319/2020.

Conventional sequential processing on software with a general purpose CPU has become significantly insufficient for certain heavy computations due to the high demand of processing power to deliver adequate throughput and performance. Due to many reasons a high degree of interest could be noted for high performance real time video processing on embedded systems. However, embedded processing platforms with limited performance could least cater the processing demand of several such intensive computations in computer vision domain. Therefore, hardware acceleration could be noted as an ideal solution where process intensive computations could be accelerated using application specific hardware integrated with a general purpose CPU. In this research we have focused on building a parallelized high performance application specific architecture for such a hardware accelerator for HOG-SVM computation implemented on Zynq 7000 FPGA. Histogram of Oriented Gradients (HOG) technique combined with a Support Vector Machine (SVM) based classifier is versatile and extremely popular in computer vision domain in contrast to high demand for processing power. Due to the popularity and versatility, various previous research have attempted on obtaining adequate throughput on HOG-SVM. This research with a high throughput of 240 FPS on single scale on VGA frames of size 640x480 out performs the best case performance on a single scale of previous research by approximately a factor of 3-4. Further it's an approximately 15x speed up over the GPU accelerated software version with the same accuracy. This research has explored the possibility of using a novel architecture based on deep pipelining, parallel processing and BRAM structures for achieving high performance on the HOG-SVM computation. Further the above developed (video processing unit) VPU which acts as a hardware accelerator will be integrated as a co-processing peripheral to a host CPU using a novel custom accelerator structure with on chip buses in a System-On-Chip (SoC) fashion. Thi

Field-programmable gate arrays (FPGAs) have recently evolved as a valuable component of the heterogeneous computing. The register transfer level (RTL) design flows demand the designers to be experienced in hardware, resulting in a possible failure of time-to-market. High-level synthesis (HLS) permits designers to work at a higher level of abstraction through synthesizing high-level language programs to RTL descriptions. This provides a promising approach to solve these problems. However, the performance of HLS tools still has limitations. For example, designers remain exposed to various aspects of hardware design, development cycles are still time consuming, and the quality of results (QoR) of HLS tools is far behind that of RTL flows. In this paper, we survey the literature published since 2014 focusing on the performance optimization of HLS tools. Compared with previous work, we extend the scope of the performance of HLS tools, and present a set of three-level evaluation criteria, covering from ease of use of the HLS tools to promotion on specific metrics of QoR. We also propose performance evaluation equations for describing the relation between the performance optimization and the QoR. We find that it needs more efforts on the ease of use for efficient HLS tools. We suggest that it is better to draw an analogy between the HLS development process and the embedded system design process, and to provide more elastic HLS methodology which integrates FPGAs virtual machines., This work was supported by the National Natural Science Foundation of China under Grant No. 61772227, the Development Project of Jilin Province of China under Grant Nos. 20190201273JC and 2020C003, Guangdong Key Project for Applied Fundamental Research under Grant No. 2018KZDXM076, and Jilin Provincial Key Laboratory of Big Date Intelligent Computing under Grant No. 20180622002JC.

A widely recognized issue when implementing dynamic binary translation is the condition codes (CCs) or flag bits emulation. The authors in the literature have approached this problem with software optimization techniques based on dataflow analysis, instruction set architecture (ISA) extensions and additional dedicated hardware, i.e., field-programmable gate array. We introduce a novel technique to handle CCs using commercial off-the-shelf architectural debug hardware as a triggering mechanism while assessing and comparing it with two existent CCs evaluation methods on the resource-constrained embedded systems arena. Our method is functionality-wise comparable with reconfigurable hardware modules or ISA extensions in open architectures and is source architecture independent, with possible applications in other use scenarios, such as application debugging and instrumentation., This work was supported by COMPETE under Grant POCI-01-0145-FEDER-007043 and Fundacao para a Ciencia e Tecnologia (FCT) under Project UID/CEC/00319/2013. The work of F. Salgado was supported by FCT under Grant SFRH/BD/81681/2011. This manuscript was recommended for publication by A. Gordon-Ross. (Corresponding author: Filipe Salgado.)

Virtualization technology starts becoming more and more widespread in the embedded space. The penalties incurred by standard software-based virtualization is pushing research towards hardware-assisted solutions. Among the existing commercial off-the-shelf technologies for secure virtualization, ARM TrustZone is attracting particular attention. However, it is often seen with some scepticism due to the dual-OS limitation of existing state-of-the-art solutions. This letter presents the implementation of a TrustZone-based hypervisor for real-time embedded systems, which allows multiple RTOS partitions on the same hardware platform. The results demonstrate that virtualization overhead is less than 2 percent for a 10 milliseconds guest-switching rate, and the system remains deterministic. This work goes beyond related work by implementing a TrustZone-assisted solution that allows the execution of an arbitrary number of guest OSes while providing the foundation to drive next generation of secure virtualization solutions for resource-constrained embedded devices., This work has been supported by COMPETE: POCI-01-0145- FEDER-007043 and FCT – Fundação para a Ciência e Tecnologia – (grant SFRH/BD/91530/2012 and UID/CEC/00319/2013).

Bringing IPv6 connectivity to low-end wireless sensor nodes leads to considerable device resources utilization, e.g., central processing unit and energy, caused by the increased amount of data transferred over the network that needs to be handled. In order to reduce these overheads, this letter proposes an IEEE 802.15.4 accelerator for heterogeneous wireless sensor systems that target the Internet of Things sensing applications, which include on the same node, field-programmable gate array technology beside a microcontroller provided with wireless connectivity. The deployed solution implements the Third-level of filtering specified by the standard, and performs basic packet handling such as the detection of multiple receptions of the same frame. The obtained results show the benefits of including such accelerator on the reconfigurable computing unit, offering nearly 17 of overhead reduction. All filtering functionalities are executed by the accelerator to discard unneeded data frames, which avoids unnecessary interrupts to the operating system and increases the system availability up to 59.

With the advent of the Internet of Things (IoT), security has emerged as a major design goal for smart connected devices. This explosion in connectivity created a larger attack surface area. Software-based approaches have been applied for security purposes; however, these methods must be extended with security-oriented technologies that promote hardware as the root of trust. The ARM TrustZone can enable trusted execution environments (TEEs), but existing solutions disregard real-time needs. Here, the authors demonstrate why TrustZone is becoming a reference technology for securing IoT edge devices, and how enhanced TEEs can help meet industrial IoT applications real-time requirements., This work has been supported by COMPETE (POCI-01-0145-FEDER-007043) and Fundacao para a Ciencia e Tecnologia (FCT) under grant SFRH/BD/91530/2012 and UID/CEC/00319/2013., info:eu-repo/semantics/publishedVersion

Computer systems are permanently present in our daily basis in a wide range of applications. In systems with mixed-criticality requirements, e.g., autonomous driving or aerospace applications, devices are expected to continue operating properly even in the event of a failure. An approach to improve the robustness of the device's operation lies in enabling fault-tolerant mechanisms during the system's design. This article proposes Lock-V, a heterogeneous architecture that explores a Dual-Core Lockstep (DCLS) fault-tolerance technique in two different processing units: a hard-core Arm Cortex-A9 and a soft-core RISC-V-based processor. It resorts a System-on-Chip (SoC) solution with software programmability (available trough the hard-core Arm Cortex-A9) and field-programmable gate array (FPGA) technology, taking advantages from the latter to support the deployment of the RISC-V soft-core along with dedicated hardware accelerators towards the realization of the DCLS.

Computer Vision is an emerging field with diverse applications which encompasses many algorithms with heavy computations. Histogram of Oriented Gradients-Support Vector Machine (HOG-SVM) is one such versatile algorithm used for object detection and image classification despite it's heavy computation load. Processing such an algorithm in real time with adequate throughput is a challenging task for a general purpose processor. Moreover, an embedded CPU with very limited processing power could least cater such heavy processing. Therefore our research in general focuses on developing application specific architectures for hardware acceleration of computer vision algorithms. This paper presents a continuation of a series of research to hardware accelerate HOG-SVM algorithm on FPGA. In this paper we mainly present the high performance application specific architecture for hardware acceleration of HOG-SVM which was successful in achieving a high throughput of 240fps on HD frames of size 1920x1080 which is a significant improvement of performance compared to previous research. On the other-hand, both hardware utilization and power consumption are minimized. A mechanism based around Block RAM (BRAM) structures and deep pipelining are used as the key architectural techniques of achieving high performance. The proposed design was deployed on Zynq 7000 FPGA platform which contains a hardwired ARM CPU along with the programmable FPGA fabric. The accelerator is deployed on the FPGA and integrated with the ARM CPU using AXI memory interfaces. A hardware thread model and bare-metal device drivers were developed which encapsulate the behavior of the accelerator as a hardware thread to the applications running on the ARM CPU.

With predictions pointing to more than 20 billion Internet-enabled 'things' by 2020 and much more to come, smart sensor nodes are expected to be predominant in the Internet of Things (IoT) era. As these systems are connected to the Internet and tend to implement an ever-growing number of mixed-criticality features, there is huge pressure for strong isolation to guarantee a reliable, secure, and predictable infrastructure. While virtualization has been a game-changer for consolidation and isolation in mid-to high-end embedded applications, for low-end and low-cost systems it is still in its infancy, and only a limited number of solutions have been proposed so far. This work aims at developing a lightweight hypervisor which provides strong isolation on resource-constrained devices. Our approach leverages TrustZone technology available on modern Arm microcontrollers (TrustZone-M) to implement a predictable virtualization infrastructure for low-end and low-cost systems. Experiments conducted on an Arm Musca-A multi-core platform demonstrate our solution achieves low memory footprint, high efficiency, and strict timing predictability.

This article describes a non-intrusive hardware acceleration approach for Dynamic Binary Translation (DBT) in modern resource-constrained embedded systems, detailing its motivation, design decisions and overall architecture. It was deployed and tested on DBTOR, an in-house DBT system that targets constrained embedded systems. The performed evaluations demonstrate the feasibility of the proposed method in handling condition code (CC) flags, peripheral remapping and interrupt support, by running legacy MCS-51 code on a modern Arm v7-M architecture (Cortex-M3) that resorts field-programmable gate array (FPGA) technology for acceleration purposes., This work has been supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: UID/CEC/00319/2019.

This letter proposes ChamelIoT, an agnostic operating system (OS) framework for reconfigurable Internet of Things (IoT) devices. ChamelIoT is bringing a reconfigurable hardware OS stack supported by a semantically enriched infrastructure that aims at offering an easy-to-use tool for building (mainly) low-power and low-cost IoT sensors with performance, real-time, and power consumption advantages., (undefined)

This article describes a dynamic binary translation (DBT) system specially tailored to fit resource-constrained embedded systems, detailing its design decisions and architectural components. Although designed to support a wide range of low-end architectures, to test its feasibility, we present and evaluate two distinct and widely known source and target architectures, commonly used in embedded systems. The performed evaluations demonstrate legacy Intel MCS-51 code running on a modern Arm v7-M architecture (Cortex-M3) and shows the impact of using DBT techniques on resource-constrained devices., INCT-EN - Instituto Nacional de Ciência e Tecnologia para Excitotoxicidade e Neuroproteção (UID/CEC/00319/2019)

This article presents Lock-V, a heterogeneous fault tolerance architecture that explores a dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA and Lock-VM by applying design diversity in two processor architectures at the instruction set architecture (ISA)-level. Lock-VA features an Arm Cortex-A9 with a RISC-V RV64GC, while Lock-VM includes an Arm Cortex-M3 along with a RISC-V RV32IMA processor. The solution explores field-programmable gate array (FPGA) technology to deploy softcore versions of the RISC-V processors, and dedicated accelerators for performing error detection and triggering the software rollback system used for error recovery. To test Lock-V in both versions, a fault-injection mechanism was implemented to cause bit-flips in the processor registers, a common problem usually present in heavy radiation environments.

Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware offloading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively., This work has been supported by COMPETE: POCI-01-0145-FEDER-007043 and FCT - Fundação para a Ciência e Tecnologia within the Project Scope: UID/CEC/00319/2013.

The Internet of Things (IoT) is revolutionizing the Internet of the future and the way smart devices, people and processes interact with each other. Challenges in endpoint devices communication are due not only to the security and privacy-related requirements but also due to the ever-growing amount of data transferred over the network that needs to be handled, which can considerably reduce the system availability to perform other tasks. This article presents a 6LoWPAN accelerator for the IP-based IoT networks, which is able to process and filter IPv6 packets received by an IEEE 802.15.4 radio transceiver without interrupting the microcontroller. It offers nearly 13.24% of performance overhead reduction for the packet processing and the address filtering tasks, while guaranteeing full system availability when unwanted packets are received and discarded. The contribution is meant to be deployed on heterogeneous endpoint devices at the network edge, which include on the same architecture, field-programmable gate array (FPGA) technology beside a microcontroller and an IEEE 802.15.4-compliant radio transceiver. Performed evaluations include the low FPGA hardware resources utilization and the energy consumption analysis when the processing and accepting/rejection of a received packet is performed by the 6LoWPAN accelerator., This work was supported in part by the COMPETE: POCI-01-0145-FEDER-007043 and in part by the Fundacao para a Ciencia e Tecnologia under Grant UID/CEC/00319/2013. The work of T. Gomes was supported by Fundacao para a Ciencia e Tecnologia under Grant SFRH/BD/90162/2012., info:eu-repo/semantics/publishedVersion

El hemangioendotelioma epitelial es una neoplasia poco frecuente, y tiene su origen en el endotelio vascular. Puede crecer en varios órganos y tejidos. No hay ningún esquema terapéutico aprobado y el pronóstico es impredecible. Se presenta el caso de un paciente masculino de 54 años de edad, con el diagnóstico de hemangioendotelioma epitelioide pulmonar, con imagen atípica y la presentación clínica y la participación de múltiples órganos en el momento del diagnóstico. El paciente no comenzó la quimioterapia y murió dos meses después del diagnóstico histológico. Debido a la rareza de esta neoplasia y la inexistencia de régimen terapéutico aprobado, al reportar este caso, tenemos la intención de contribuir a los estudios clínicos futuros.

The ubiquitous connectivity of the low-end devices in the Internet of Things (IoT) brings new challenges over the traditional wireless sensor networks' architectures. Such challenges require not only security and privacy-related features, but also solutions to handle the ever-growing amount of data transferred over the network. However, performing such tasks on resource constrained devices is not straightforward. The need for energy-efficient devices, while preserving their performance and security capabilities, requires new solutions at the architectural level of the wireless device. This paper proposes a heterogeneous architecture that targets low-end and resource constrained IoT devices, combining a hardcore microcontroller unit (MCU) and a reconfigurable computing unit (RCU) with an IEEE 802.15.4 radio transceiver. The MCU hosts an embedded operating system with an IoT-enabled network stack, and exploits the available field-programmable gate array technology to implement the RCU and to deploy customized sensing- and network-related accelerators, offloading heavy, and/or complex software tasks to dedicated hardware blocks. The customizable and trustable end-device mote was implemented using the proposed architecture and the achieved results demonstrates the benefits, both in terms of performance and energy, of accelerating network-related tasks in always-connected resource constrained IoT devices., FCT - Fundação para a Ciência e a Tecnologia (POCI-01-0145-FEDER-007043), info:eu-repo/semantics/publishedVersion

With the increased complexity of low-end devices in the Internet of Things (IoT), mainly due to the connectivity and interoperability requirements, the development and configuration of embedded operating systems (OSes) for such devices is not straight forward. The complexity of the communication requirements is usually mitigated by the OS, e.g., the Contiki-OS, as it already incorporates an IoT-compliant network stack. Yet, the configuration of such stack requires major knowledge on the code structure, leading to additional development time, particularly when the network comprises several wireless nodes and individual configurations with subsequent firmware that needs to be generated. Based on a developed software modeling domain-specific language, this paper presents the EL4IoT framework. It aims to reduce and ease the development time by promoting a design automation tool that can configure, and automatically generate code (ready to compile) for low-end IoT devices running the Contiki-OS. Although leveraging the whole Contiki-OS modeling, this work only refactored and modeled the network stack while approaching the OS itself as one big building block or component. The proposed approach can be extended to other IoT-enabled OSes as well as integrated in other design automation tools., This work has been supported by COMPETE: POCI-01-0145-FEDER-007043 and FCT - Fundação para a Ciência e Tecnologia within the Project Scope: UID/CEC/00319/2013. Tiago Gomes is supported by FCT PhD grant SFRH/BD/90162/2012.

IT job market seems to be an interesting alternative for those who are deaf or hearing impaired (DHI). All accessible (interface+content+learning objects) online courses have the reach and the means to, potentially, impact the status quo. All lab offers such courses to both DHI and non-DHI communities. Still, DHI graduates legs behind non-DHI in debugging-related tasks when the industry-standard Eclipse (Development Environment) is used [1]. Visual debuggers improve DHI performance [2]. In this paper, we present Java Accessible Visual Debugger (JAD). JAD was conceived to be the first accessible visual debugger and to leverage debugging performance between DHI and non-DHI. This paper presents a study involving DHI/non-DHI and JAD. Three metrics were used to assess performance: 1) number of fully completed tasks (TFC); 2) time to task completion (TCT); 3) number of external help requests (HR). Non-paired t-Student's tests show no significant difference in any of the above criteria.

Virtualization technology is well established in the server and desktop spaces, and has been spreading across embedded system market. This technology allows for the coexistence and execution of multiples operating systems on top of the same hardware platform, with proven technological and economic benefits. Hardware extensions for easing virtualization have been added into several commercial off-the-shelf processors. Among existing technologies, ARM TrustZone is gaining particular attention due to its broadly availability into ARM processors. However, existent TrustZone-assisted virtualization solutions are limited to a dual-guest and single-core configuration, which can lead to the starvation of the non-secure side when the secure world does not yield the processor. This work presents the extension of a TrustZone-assisted hypervisor to an asymmetric multi-processing configuration. We describe and demonstrate how to run a general-purpose operating system side-by-side with an real-time operating system in a Xilinx Zynq-based platform, enhanced with a dual ARM Cortex-A9. The achieved results demonstrate that the implemented multicore approach not only completely eliminates starvation, but also increases the general-purpose operating system's performance, especially when the real-time workload is demanding.

Over the past few decades, many researchers have tested course designs that may better engage students in developing countries, accommodate for Millennials’ desires to learn and teach at will, and teach students the skills they need for their first jobs. The vision of this paper for a web design course seeks to address these issues for engineering students. The paper first details the ‘study everywhere, anytime, from any device and using any tool’ approach, following the CDIO (Conceive, Design, Implement and Operate) contextual learning model sustained by gamified crowdsourcing. Then the multi-pronged approach has been tested in a high-enrollment (269-student) web design course at a university in China. The success of integrating the gamification and crowdsourcing techniques into the web design course is then analyzed. Results are positive overall. A linear upward trend is observed in the number of students who completed the course exercises over the duration of the course, marking an increase in student engagement over time.

Background:Many attempts at personalisation have been made in education. They all collect learning data and analyse learning behaviours, and ultimately achieve personalised learning dynamically. However, further research is needed on the ways to effectively access and analyse information about learning within an enjoyable environment and with positive results when realising personalised learning.Material and methods:In order to solve this problem, we connect the time in class and after class with semantic knowledge and combine these elements with gamification and a better interaction experience. We explore whether this teaching method can offer students a better learning experience and positive learning outcomes.Results:Our approach plays an obvious role in personalised learning.Conclusions:Our results indicate that a teaching method which connects the two parts of a class with gamification and a means of interaction in AR (augmented reality) produces novel and enjoyable feelings, stimulates students' enthusiasm and improves the learning effects when they do personalised learning.

Virtualization has been deployed as a key enabling technology for coping with the ever growing complexity and heterogeneity of modern computing systems. However, on its own, classical virtualization is a poor match for modern endpoint embedded system requirements such as safety, security and real-time, which are our main target. Microkernel-based approaches to virtualization have been shown to bridge the gap between traditional and embedded virtualization. This notwithstanding, existent microkernel-based solutions follow a highly para-virtualized approach, which inherently requires a significant software engineering effort to adapt guest operating systems (OSes) to run as userland component s. In this paper, we present μRTZVisor as a new TrustZone-assisted hypervisor that distinguishes itself from state-of-the-art TrustZone solutions by implementing a microkernel-like architecture while following an object-oriented approach. Contrarily to existing microkernel-based solutions, μRTZVisor is able to run nearly unmodified guest OSes, while, contrarily to existing TrustZone-assisted solutions, it provides a high degree of functionality and configurability, placing strong emphasis on the real-time support. Our hypervisor was deployed and evaluated on a Xilinx Zynq-based platform. Experiments demonstrate that the hypervisor presents a small trusted computing base size (approximately 60KB), and a performance overhead of less than 2% for a 10 ms guest-switching rate., FCT - Fundação para a Ciência e a Tecnologia (POCI-01-0145-FEDER-007043), info:eu-repo/semantics/publishedVersion

In the near future, billions of new smart devices will connect the big network of the Internet of Things, playing an important key role in our daily life. Allowing IPv6 on the low-power resource constrained devices will lead research to focus on novel approaches that aim to improve the efficiency, security and performance of the 6LoWPAN adaptation layer. This work in progress paper proposes a hardware-based Network Packet Filtering (NPF) and an IPv6 Link-local address calculator which is able to filter the received IPv6 packets, offering nearly 18% overhead reduction. The goal is to obtain a System-on-Chip implementation that can be deployed in future IEEE 802.15.4 radio modules., Tiago Gomes is supported by FCT - Fundação para a Ciência e Tecnologia (grant SFRH/BD/90162/2012). This work has been supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: PEst-UID/CEC/00319/2013., info:eu-repo/semantics/publishedVersion

Most hypervisors today rely either on (1) full virtualization on high-end hardware (i.e., hardware with virtualization extensions), (2) paravirtualization, or (3) both. These, however, do not fulfill embedded systems' requirements, or require legacy software to be modified. Full virtualization on low-end hardware (i.e., hardware without virtualization extensions), on the other end, has none of those disadvantages. However, it is often claimed that it is not feasible due to an unacceptably high virtualization overhead. We were, nevertheless, unable to find real-world quantitative results supporting those claims. In this paper, performance and footprint measurements from a case study on low-end hardware full virtualization for embedded applications are presented. More specifically, this paper presents: (1) an evaluation of the virtualization overhead in a Linux-based system as a guest on POK/rodosvisor, a real time operating system for embedded systems featuring low-end hardware full virtualization; (2) a detailed look at the performance of POK/rodosvisor's internal operation, namely, interrupt handlers and context switching; and (3) POK/rodosvisor's footprint for various configurations. To the best of our knowledge, this is the first paper ever to present performance measurements about a Linux-based system as a guest on a hypervisor based on low-end hardware full virtualization, and therefore, targeting a common real-world scenario., This work has been supported by COMPE IL: POCI-01-0145-FEDER-007043 and FCT (Fundacao para a Ciencia e Tecnologia) within the Project Scope: UID/CEC/00319/2013. The work of A. Carvalho and V. Silva was supported by FCT (grants SFRH/BD/81640/2011 and SFRH/BD/82732/2011, respectively)., info:eu-repo/semantics/publishedVersion

The growing complexity of current embedded systems increases not only the time-to-prototype and time-to-market, but it also requires a major effort around repetitive engineering tasks in order to maximize the efficiency and minimize the money investment. A lot of research has been done on this field, leading system development, test automation and system reutilization to huge relevance and considerable importance in industry and academia. Using eXtensible Markup Language (XML) files to store Intellectual Property (IP) metadata, the IP-XACT standard arises as a possible solution for IP reutilization and vendor independence. This paper describes a RTL design generator that uses IP-XACT components description and apply XSLT transformations for complete system generation, following a generative programming (GP) approach while automating the design flow through the integration and interoperability of external tools needed to design, implement and finally deploy the final system under the chosen FPGA board. The aim is to provide a unified and easy to use interface for code generation and deployment independent from FPGA vendors, i.e., fostering vendor-agnosticism.

We investigated how visual debuggers impact the performance of a Java programmer who is deaf or hearing impaired (DHI). In previous work, we had shown that despite having attended accessible java course, deaf programmers still perform poorer than their hearing counterparts in tasks like debugging. In this text, we show that visual debuggers present a hope of bridging the gap between the two populations. Typical debugging tasks were assigned to both groups who used industry standard IDE (Eclipse) and a Visual Debugger (JGrasp). Qualitative and quantitative analysis show advantages for the former.

The emergence of hardware multithread (HW-MT) architectures increased the performance of MT applications. However, traditional HW-MT architectures are not suitable to real-time operating systems as their performance-oriented scheduling algorithm may conflict with RTOS software scheduling. This letter presents RT-SHADOWS, a portable architecture which provides a unified hardware-software scheduling, bringing the benefits of HW-MT to the RTOS domain. We show that tightly-coupled real-time compliant hardware integration achieves throughput benefits, maintaining the RTOS scheduling policy intact while increasing the predictability of RTOSes. Our solution shows on average, speed-ups between 3 and 4 times over the native versions with very low area usage/performance overhead ratio, due to its minimal cost (2% of extra slices per hardware-supported thread). This work surpasses related work by providing a complete and agnostic hardware solution which is independent of any specific RTOS., This work was supported by the FCT within the Project Scope: PEst-UID/CEC/00319/2013. The work of T. Gomes was supported by the FCT, Fundacao para a Ciencia e Tecnologia (Grant SFRH/BD/81682/2011). This manuscript was recommended for publication by W. Zhao., info:eu-repo/semantics/publishedVersion

RodosVisor is an object-oriented and bare-metal virtual machine monitor (VMM) or hypervisor designed for the aerospace industry, mainly to provide time and spatial separation to the NetworkCentric core avionics machine, Montenegro and Dittrich (2009). The NetworkCentric core avionics machine consists of several harmonized components working together to implement dependable computing in a simple way, with computing units managed by the local real-time operating system RODOS. To support partitioned software architectures such as AIR, Rufino et al. (2009), and MILS, DeLong, R. (2007), RodosVisor adapted the Popek and Goldberg's fidelity, efficiency and resource control virtualization requirements, Popek and Goldberg (1974), to the space application domain by extending them with extra ones, like timing determinism, reactivity and improved dependability. Another distinctive RodosVisor feature is the customized design based on generative programming techniques, such as aspect oriented programming and template meta-programming.

The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. Field Programmable Gate Arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.

Embedded virtualization possesses inherent challenges which differentiate the domain from traditional virtualization application fields such as server and desktop computing. Standard software virtualization solutions have a negative impact, not only on memory footprint and performance, but also on determinism and interrupt latency which are critical for the embedded real-time domain. Thus, efficient embedded virtualization requires domain-specific software and hardware support. This paper presents work in progress results of hardware-based Hypervisor implementation. The use cases of embedded virtualization are analyzed, justifying the reasoning for hardware-supported virtualization. Architectural and micro-architectural improvements to an ARM v5TE processor are described, demonstrating the performance advantages, and compared against ARM Virtualization Extensions, identifying respective vulnerabilities and providing alternative solutions which enable higher flexibility, minimizing virtualization costs. The research roadmap towards a hardware-complete Hypervisor, based on the presented results, is described.

With the development of Internet of Things technology, radio-frequency identification localization methods have been widely applied due to their low cost and ease of deployment. The indoor radio-frequency identification localization algorithm based on received signal strength indication technology is a currently hot topic. Because the received signal strength is highly dependent on environments, the classic algorithms may result in large errors in localization accuracy. This article proposed a new radio-frequency identification localization algorithm, named BP_LANDMARC, by utilizing the back propagation neural network, which is designed to address nonlinear changes in radio-frequency signals. A strategy for selecting different working parameters in variable environments is presented. The evaluation methods of root mean square error and cumulative distribution function are used to compare the proposed algorithm with some existing algorithms. Experimental results show that the proposed algorithm remarkably improves the localization accuracy of both absolute distance and cumulative probability. Moreover, the proposed algorithm performs effectively and efficiently when it is applied to a logistics warehouse management system., The author(s) disclosed receipt of the following financial support for the research, authorship, and/or publication of this article: This work was supported by the National Natural Science Foundation of China (61472158, 61503150, and 61572228), the Zhuhai Premier Discipline Enhancement Scheme (2015YXXK02), and the Guangdong Premier Key-Discipline Enhancement Scheme (2016GDYSZDXK036) and Science & Technology Development Foundation of Jilin Province (20180201045GX and 20160520012JH).

It is not enough to offer accessible learning material, accessible learning platform and bilingual tutoring. Deaf or hearing impaired (DHI) java graduates still show poorer perfomance in debugging tasks when compared to their hearing counterparts. Direct manipulation and visual debuggers might improve the odds of securing the DHI a position in the IT industry. We present a study where DHI java graduates perform debugging tasks using a visual debugger and Eclipse. Situated analysis, usability assessment and a formal task performance evaluation show visual debuggers might benefit the DHI programmer.

Multithreading is a key feature for dealing with the complexity of current generation embedded devices. Real-Time Operating Systems (RTOSes) provide a higher level of abstraction that alleviates design complexity and time-to-market pressure, inducing, however, undesired latencies and unpredictable execution times. Research works have been focusing on improving performance, determinism or agnosticism, but none simultaneously tackled the three metrics. This work in progress paper presents RT-SHADOWS, a co-designed architecture that promotes configurability, determinism and agnosticism from the outset. A multi-thread ARM softcore processor was exploited and extended by offloading the scheduling-related features into the hardware layer. The hardware multi-thread support is transparent for the standard RTOS applications and independent of the Operating System (OS). Promising preliminary results demonstrate huge improvements on performance and determinism, with only a small cost on hardware.

With the growing ubiquity of Internet of Things (IoT), myriads of smart devices connect and share important information over the internet. In order to provide connectivity and interoperability of all the existing heterogeneous wireless devices, a full communication stack is proposed by the IoT Architecture Reference Model (IoT-ARM). From the sensor to the cloud, the proposed stack can be implemented on all IoT devices avoiding the battle for the wireless standard that will be adopted. This work in progress paper proposes an FPGA-based edge device for IoT, which uses SoC (System-on-Chip) FPGA technology to offload critical features of the communication stack to dedicated hardware, aiming to increase systems performance.

The pervasive use of embedded computing systems in modern societies altogether with the industry trend towards consolidating workloads, openness and interconnectedness, have raised security, safety, and real-time concerns. Virtualization has been used as an enabler for safety and security, but research works have proven that it must be extended and improved with hardware-based security foundations. ARM Trustzone has been used for the realization of Trusted Environments, however in this case real-time requirements are completely disregarded. This work in progress paper presents FreeTEE, an embedded architecture that emphasizes and preserves the real-time properties of the system but still guarantees security from the outset. TrustZone technology is exploited to implement the basic building blocks of a Trusted Execution Environment (TEE) as a lower-priority thread of a RTOS. Preliminary results demonstrated that the real-time properties of the RTOS remain practically intact., Sandro Pinto is supported by FCT - Fundação para a Ciênciae Tecnologia (grant SFRH/BD/91530/2012). This work hasbeen also supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: PEst-UID/CEC/00319/2013, info:eu-repo/semantics/publishedVersion

In the development of real-time systems, predictability is often hindered by technological factors which break the timing abstractions offered by real time operating systems (RTOSs); namely, the priority space separation between threads and interrupts induces the rate-monotonic problem. Software approaches have tackled this issue, attempting to unify the priority space with varying degrees of success. We present a hardware approach to the problem: unifying the priority space at the interrupt handling subsystem, predictability is greatly enhanced with minimum software modifications. Our solution provides the interrupt controller with awareness of the currently running task's priority making the solution independent of the used operating system. We show how our approach is minimally intrusive at hardware architecture level and provides benefits beyond the capabilities of previous approaches. Our technique shows a 0.05% run-time overhead if no interrupts occur, and run-time reduction proportional to interrupt rate for rates higher than 5 per s, for a interrupt workload around 0.07 ms., This work was supported by the FCT within the Project Scope:PEst-OE/EEI/UI0319/2014. The work of T. Gomes was supported by the FCT, Fundação para a Ciência e Tecnologia (Grant SFRH/BD/81682/2011)., info:eu-repo/semantics/publishedVersion

Teaching a programming language to a person who is deaf or hearing impaired (DHI) has, along with other challenges, the lack of signs to convey basic concepts in computing. This shortage of signs makes learning even harder for the DHI.The creation of signs from co-present discussions involving instructors, translators and the DHI can lead to regionalism, which might hinder their acceptance by members of other DHI communities throughout the country. A way to combat regionalism is through the asynchronous collaborative creation of signs, normally supported by web tools.But are the signs created through web discussions inferior in any way to those created via co-present discussions? This article presents a comparative study on the acceptance of signs created by both methods showing that acceptable and legitimate signs can also be produced using web discussions and the users can not distinguish from which method they come from.

Migration to multicore is inevitable. To harness the potential of this technology, embedded system designers need to have available operating systems (OSes) with built-in capabilities for multicore hardware. When designed to meet real-time requirements, multicore SMP (Symmetric Multiprocessing) OSes not only face the inherent problem of concurrent access to shared kernel resources, but still suffer from a bifid priority space, dictated by the co-existence of threads and interrupts.This work in progress paper presents the offloading of the FreeRTOS kernel components to a commercial-off-the-shelf (COTS) multicore hardware. The ARM Generic Interrupt Controller (GIC) is exploited to implement a multicore hardware centric version of the FreeRTOS that not only solves the priority inversion problem, but also removes the need of internal software synchronization points. Promising preliminary results on performance and determinism are presented, and the research roadmap is discussed., Sandro Pinto is supported by FCT - Fundação para a Ciência e Tecnologia (grant SFRH/BD/91530/2012). This work has been supported by FCT - Fundação para a Ciência e Tecnologia within the Project Scope: PEst-UID/CEC/00319/2013.

Traditionally, operating system (OSes) suffers from a bifid priority space dictated by the co-existence of threads managed by kernel scheduler and asynchronous interrupt handlers scheduled by hardware. On real-time systems, where reliability and determinism plays a critical role, this approach presents a noteworthy lack, as any interrupt handler can interrupt an execution thread, regardless of its priority. This paper presents the implementation of an unified priority space approach (SLOTH), handling each thread as an interrupt. A light-weight version of FreeRTOS was internally redesigned, to replace the software scheduler by a hardware one, which exploits a Commercial Off-The-Shelf (COTS) hardware interrupt controller, provided by ARM Cortex-M3. The results showed that our implementation solves the priority inversion problem, and simultaneously improves the system performance, reduces the memory footprint and simplifies maintainability.

Virtualization has been used as the de facto technology to allow multiple operating systems (virtual machines) to run on top of the same hardware platform. In the embedded systems domain, virtualization research has focused on the coexistence of real-time requirements with non-real-time characteristics. However, existent standard software-based virtualization solutions have been shown to negatively impact the overall system, especially in performance, memory footprint and determinism. This work in progress paper presents the implementation of an embedded virtualization architecture through commodity hardware. ARM TrustZone technology is exploited to implement a lightweight virtualization solution with low overhead and high determinism, corroborated by promising preliminary results. Research roadmap is also pointed and discussed.

As real-time embedded systems become overwhelmingly complex, hypervisor-based architectures are increasingly being used. Hypervisor-based architectures can support such level of complexity and, at the same time, provide real-time performance while reducing the size, cost and time-to-market of such systems. Modern processors provide cache facilities which can increase their performance substantially. Similarly, in hypervisor-based architectures, by providing virtual machines (VM) with such facilities a significant improvement in their performance can be obtained as we conclude in this work. This article presents a methodology to fully virtualize the cache facilities of the IBM PowerPC 405-S. To the best of our knowledge, this is the first time cache virtualization is openly described. A careful mapping between a VM's cache-related configuration and the processor's configuration is done, accompanied by the emulation of 5 cache-related privileged instructions. Even though some issues have been detected, a simple solution is provided for all of them. The results show that cache virtualization works with minimal virtualization overhead.

Wireless Sensor Networks are an emerging technology which has been recently adopted in many applications. Due to its wireless nature, the analysis of the radio propagation models plays an important role for performance evaluation in both theoretical and practical aspects. In this regards, path loss exponent is one of the most important parameter which has been considered widely in wireless communications analysis. There are several theoretical evaluations of path loss exponent for wireless sensor networks available in the literature. However there is a lack of experimental evaluation of both path loss exponent and the effect of shadowing. In this paper, three environments (free space, in building and industrial), where wireless sensor nodes are widely deployed, have been chosen in order to evaluate the experimental analysis. Path loss and path loss exponent are measured by means of Received Signal Strength Indicator (RSSI) and based on them, the standard deviation of shadowing effect is also calculated. All the measured parameters are compared with the theoretical analysis available in the literatures.

In today's advanced technological age, embedded and real time systems have become ubiquitous, covering a wide range of applicability. As a result there is an ever growing need for low power capabilities along with reasonable performance, thus presenting a virtual demand for power-aware devices. The purpose of this work was leveraging key techniques and technologies such as design laziness, componentware design, generative design, separation of mechanism and policy, voltage-frequency island, state encoding, clock gating, and operand isolation, and then investigating their effects while designing an energy and power-conscious microcontroller based on 8051 ISA (Instruction Set Architecture) without disregard to silicon area, required application functionalities and performance. Simulations show that our purposed 2 stage pipeline system with built-in hybrid scheduler operates at 230μW@1MHz., Fundação para a Ciência e a Tecnologia (FCT)

In this paper the ClimaWin concept is introduced. The ClimaWin project's main goals are to improve both indoor air quality and the energy efficiency of new and refurbished buildings, through the use of novel green smart windows. Generally, in order to improve windows' energy efficiency better insulation materials are used in windows frames and glasses. However, this approach leads to a severe deterioration of indoor air quality (IAQ) especially in buildings that are not equipped with heating, ventilation and air conditioning (HVAQ) systems. The Climawin windows do not require wires neither for power nor for communications. The window is powered through a battery (for blind operation) and a solar panel, which makes it an ideal solution for retrofitting. In order to achieve the energy efficiency requirements, the Climawin system hardware, the microcontroller software architecture and the radio communication strategy were designed for low power consumption. Furthermore, all the information about the system status can be monitored and actuated using intuitive graphical applications developed for PCs and Android OS smartphones. A remote database keeps all the relevant information about the system, making it easy to detect any anomaly or even to adjust the control algorithm parameters from a remote location. A full-set of web services are also provided in order to simplify the communication with home automation systems.

Nowadays, the growing complexity of embedded systems demands for configurability, variability and reuse. Conditional compilation and object-orientation are two of the most applied approaches in the management of system variability. While the former increases the code management complexity, the latter leverages the needed modularity and adaptability to simplify the development of reusable and customizable software at the expense of performance and memory penalty. This paper shows how C++ TMP (Template Metaprogramming) can be applied to manage the variability of an object-oriented operating system and at the same time get ride out of the performance and memory footprint overhead. In doing so, it will be statically generated only the desired functionalities, thus ensuring that code is optimized and adjusted to application requirements and hardware resources., Fundação para a Ciência e a Tecnologia (FCT)

The developers' need for shorter time to market and the increasing complexity of electronic systems caused by the demand for a myriad of functional and non-functional characteristics, led to the adoption of novel design and implementation techniques to bridge the concept to implementation gap. This paper presents model-driven generative design in the implementation of IP cameras for integration on Home Appliance Networks. The refinement process for the Product Family is depicted for two camera configurations and the use of generative design for implementing the models is described, displaying the variability in terms of features and implementation. The topology is also described to show how architectural models can be used to aid the process and ensure ease of integration and interoperability between functionalities, regardless of their implementation (gateware, software or hybrid).

Performance and determinism are two critical metrics in most embedded systems with real-time requirements. Owing to the complexity of current embedded systems, along with increased application demands, real-time operating systems (RTOSs) have become a de facto solution providing specific services to the system tasks. However, this extra layer, which abstracts the hardware from the software, makes it harder for a system to achieve good performance and determinism. To ease the impact of a RTOS in the system, RTOS run-time services are offloaded to the hardware layer. This paper presents a hybrid RTOS implementation, where several critical RTOS services were migrated from software to hardware, improving system latency and predictability. Special focus was given to the RTOS scheduler and to the mutexes handling subsystem. The developed hardware accelerators were synthesised on a field-programmable gate array (FPGA), exploiting the point-to-point fast simplex link (FSL) bus to interconnect to the Xilinx Microbaze soft-core processor. Our approach shows that hybrid RTOS has a better performance and predictability when compared to its software-only version.

The growth in embedded systems complexity has created the demand for novel tools which allow rapid systems development and facilitate the designer's management of complexity. Especially since systems must incorporate a variety of often contradictory characteristics, achieving design metrics in short development time is an increasing challenge. This paper presents RAPTOR-Design, a framework for System-on-Chip (SoC) design which incorporates a customizable processor architecture and allows rapid software-to-hardware migration, custom hardware integration in a tightly-coupled fashion and seamless Fault Tolerance (FT) capabilities for FPGA platforms. Impact on design metrics of processor customization, FT-capabilities and custom hardware integration are presented, as well as an overview of the design process using RAPTOR-Design.