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In 5 nm FinFET technology and beyond, SRAM cell size reduction to 6 tracks is required with a fin pitch of 24 nm. Fin depopulation is mandatory to enable the area scaling, but it becomes challenging at small pitches. In the first part, each process flow is simulated in order to obtain a 3D model of a FinFET SRAM device. Layout dependent effects on silicon and process non-idealities are characterized in a second part and used to calibrate the 3D model. In the third part, a process sensitivity analysis is conducted to compare the impact of overlay and CD variations on various options.

The origin of the roughness of Fin FET channel sidewalls in the heterointegration scheme was discussed. It is shown that its presence is caused by the original roughness of the Si sidewalls of the “fin” structures formed during plasma etching. A number of processing steps affecting the morphology of the Si fin structures were analyzed. The smoothing of the resistive polymeric mask in the HBr-containing plasma, distributed trimming in the layered mask, and control of the temperature conditions are among these technologies.

We demonstrate Si-cap-free SiGe p-channel FinFETs and gate-all-around (GAA) FETs in a replacement metal gate (RMG) process, for Ge contents of 25% and 45%. We show that the performance of these devices is substantially improved by high-pressure (HP) deuterium (D 2 ) anneal, which is ascribed to a 2x reduction in interface trap density (D IT ). Furthermore, it is found that (1) TMAH treatment of SiGe prior to HK deposition and (2) HK post-deposition annealing (PDA) are beneficial for D IT reduction as well, and that NBTI reliability is improved by both HP D 2 anneal and TMAH treatment.

Tensile strained Si (sSi) layers were epitaxially deposited onto fully relaxed Si0.78Ge0.22 (SiGe) epitaxial layers (4 μm) on silicon substrates. Periodic arrays of 150 nm × 150 nm and 150 nm × 750 nm pillars with a height of 100 nm were fabricated into the sSi and SiGe layers by electron-beam lithography and subsequent reactive ion etching. The strain in the patterned and unpatterned samples was analyzed using high-resolution UV micro-Raman spectroscopy. The 325 nm excitation line used probes strain in Si close to the surface (penetration depth of ∼9 nm). The Raman measurements revealed that the nano-patterning yields a relaxation of strain of ∼33% in the large pillars and ∼53% in the small pillars of the ∼0.95% initial strain in the unpatterned sSi layer.

Plasma etching of lithium niobate with fluorine gases is limited by the redeposition LiF. This results in a low etch rate and nonvertically etched walls. Etching of proton-exchanged lithium niobate can prevent the LiF deposition to a large extent because of the greatly reduced lithium concentration in lithium niobate. We performed different inductively coupled plasma etching processes using SF6 or CHF3∕Ar on proton-exchanged lithium niobate. Negligible underetching and nearly vertically etched walls on proton-exchanged lithium niobate samples were obtained by CHF3∕Ar gas at chamber pressure of 6mTorr and 130V dc bias.

Dry plasma etching of sub-micron structures in a SiO"2/Si/SiO"2 layer system using Cr as a mask was performed in a fluorocarbon plasma. It was determined that the best anisotropy could be achieved in the most electropositive plasma. A gas composition yielding the desired SOI planar photonic crystal structures was optimized from the available process gases, Ar, He, O"2, SF"6, CF"4, c-C"4F"8, CHF"3, using DC bias data sets. Application of the c-C"4F"8/(noble gas) chemistry allowed fabrication of the desired SOI planar photonic crystal. The average etching rates for the pores and ridge waveguide regions were about 71 and 97nm/min, respectively, while the average SiO"2/Si/SiO"2 to Cr etching selectivity for the ridge waveguide region was about 33:1 in case of the c-C"4F"8/90%Ar plasma with optimized parameters.

RIE-plasma etching of sub-micron structures in 150-200-nm thick Cr layers deposited on 4-inch SiO"2/Si/SiO"2 wafers was investigated as a function of the gas composition, RF power, and resist type. An optimal recipe is obtained yielding a Cr etching rate of about 7 nm/min and a ratio of the resist to the Cr etching rates of about 2 in case of etching the sub-micron structures in Cr with a ZEP 520 resist mask. SEM investigations show nearly vertical sidewalls of features etched in Cr layers with a lateral size ranging from 0.3 to 0.5 @mm.

The effect of the transformer-coupled capacitive tuning (TCCT) parameter on the etch rate uniformity (ERU) in a high density plasma etch chamber was studied by the following means: blanket wafer experiments; tests on patterned wafers with 20-nm half-pitch BEOL interconnect trenches, created by spacer defined double patterning; and PlasmaVolt™ X2 (PVx2) sensor wafer experiments. Besides pure Ar and pure SF 6 chemistries, several typical process chemistries of poly-Si and SiO 2 etching were selected for study. It was shown that the ERU data (expressed as 3σ) were in good agreement for all the chemistries applied to both PVx2 and blanket SiO 2 with different TCCTs. The ERU of blanket poly-Si, however, did not generally correlate well with the PVx2 data. Only Ar sputtering and Cl 2 /HBr–based processes showed a similar 3σ trend for both PVx2 and poly-Si. For the 20-nm half-pitch wafers, a study was performed on three separate etch steps with different chemistries, used for SiOC, BARC, and SiN etching. The critical dimension (CD) uniformity data was compared to the PVx2 results and demonstrated a good correlation in the first two cases. Based on these results, it was concluded that PVx2 is able to predict the behavior of the ion-assisted etch component in terms of uniformity, while spontaneous chemical reactions and/or ion-assisted polymer deposition could result in a substantial discrepancy between the actual ERU data and the PVx2 results. Finally, for materials that are typically etched using a dominant ion-assisted etch component, it was estimated that use of this PVx2-based method of ERU tuning may result in lot turn time savings of 80% when compared to single-use blanket wafer ERU tests.

An etch-stop phenomenon taking place in Cl2/O2/N2 plasma was investigated by means of the actinometry technique as well as using PlasmaVolt and PlasmaTemp in-situ sensor wafers from K-T promesys of KLA Tencor. The temperature of TCP quartz window was determined to increase from 50°C to more than 100°C during sequential plasma processing that in turn induces a plasma composition change. Based on the optical spectra a 20% increase in both atomic [O] and [Cl] concentrations was determined to take place in Cl2/O2/N2 plasma used for STI etching. Performing experiments on the blanket wafers the dependence of the etch-stop on O2-flow, pressure, TCP power, wafer temperature and quartz window temperature was determined. The values of RF voltage and temperature were measured locally at different positions on the wafer surface providing additional information about plasma homogeneity. Finally, the results are discussed in terms of the well-known recombination model considering the increase of [O] concentration results in the etch stop in the middle of the wafer.© (2008) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

We present a new high-index-contrast material system to realize ridge waveguides and PhC waveguides made of a thin silicon slab embedded in two silica layers. Hence fully symmetrical structures can be etched and two important conditions for low-loss guiding of light can be matched: The symmetry properties of the material avoid polarization mixing and the high index contrast leads to strong confinement of light. Because of operating completely below the lightcone the PhC waveguides allow theoretically lossless guiding of light.

Microdisks based on in-plane embedded size-controlled Si nanocrystal∕SiO2 superlattices (Si-NCs∕SiO2 SLs) were mass-fabricated arranged in well-ordered arrays. The microdisks were fabricated with size irregularity of below 0.2% over large-scale areas. Overlapping whispering-gallery modes (WGM) of the visible nanocrystalline-silicon luminescence were observed. A comparison between analytical calculation and experimental results is reported. We found that only one axial and one radial WGM exist due to their thin disk thickness and birefringence characteristic of Si-NCs∕SiO2 SLs, and that the mode spacing is 15nm and 6nm for microdisks with a diameter of 8.8μm and 23.7μm, respectively. The advantages of such size-controlled Si-NCs∕SiO2 embedded in microdisk arrays for Si-based photonic application will be discussed.