Search

This paper presents a metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) device, operating in enhancement mode, with a double-channel triple-barrier (DCTB) Al0.15Ga0.85N/GaN/Al0.07Ga0.93N/GaN/Al0.05Ga0.95N device structure. Initially, we simulate the Al0.15Ga0.85N/GaN single-channel single-barrier (SCSB) MIS-HEMT, featuring a T-gate design that offers a significant gap between the gate and a drain electrode, resulting in a high breakdown voltage (VBD) and low parasitic capacitance, enhancing cut-off frequency (ft) and a maximum frequency of oscillation (fmax). In the current era, high breakdown voltage, high current drive, and high-frequency enhancement-mode-operated devices are needed for power switching circuits and high-frequency power amplifier applications. To meet these requirements, we propose a DCTB MIS-HEMT device structure that adds additional back-barrier layers and channel layers to form a double-hump characteristic due to the interaction between two-dimensional electron gas (2DEG) accumulation layers and the electric field across the device. We optimize the devices with an optimistic doping profile in channel and buffer layers, a field plate, recessed gate structure, and control the barrier layers thickness, ensuring enhancement-mode operation. Numerical simulations of the DCTB device provide high drain current (Ids) of 1.5 A/mm, transconductance (gm) of 0.232 S/mm, threshold voltage (Vt) of 2.8 V, VBD of 633.1 V, ON resistance (RON) of 6.074 Ω mm, ft of 49.8 GHz, and fmax of 107.8 GHz. Due to improvements in these parameters, the DCTB MIS-HEMT outperforms the SCSB MIS-HEMT, making it suitable for high-current drive, high-frequency, and high-speed switching applications. In this work, we also examine the merits of utilizing DCTB MIS-HEMT as the switching element in an ultra-low-loss boost converter circuit. [ABSTRACT FROM AUTHOR]

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times. [ABSTRACT FROM AUTHOR]

This paper proposes and investigates a novel 4H‐SiC trench MOSFET (TMOS) with integrated high‐K deep trench and gate dielectric (INHK‐TMOS). The integrated high‐K (INHK) consists of a high‐K gate dielectric and an extended high‐K deep trench dielectric in the drift region. Firstly, the high‐K gate dielectric together with the metal‐forming high‐K metal gate structure, which increases the gate oxide capacitance (COX), reduces the threshold voltage (VTH) and the specific on‐resistance (Ron,sp). Secondly, the extended high‐K deep trench dielectric not only modulates the electric field in the drift region by introducing a new electric field peak at the bottom of the high‐K deep trench dielectric, thereby enhancing the breakdown voltage (BV), but also improves the doping concentration (ND) of the drift region by the assist depletion effect of the high‐K dielectric, further optimizing the forward conduction characteristics. Simulation results demonstrate that when compared to the conventional TMOS, the INHK‐TMOS using HfO2 exhibits a 52.6% reduction in VTH, a 52.1% reduction in Ron,sp, a 20.3% increasement in BV and a 202.3% improvement in figure of merit. [ABSTRACT FROM AUTHOR]

In this study, we propose an optimized AlGaN/GaN high-electron-mobility transistor (HEMT) with a considerably improved breakdown voltage. First, we matched the simulated data obtained from a basic T-gate HEMT with the measured data obtained from the fabricated device to ensure the reliability of the simulation. Thereafter, to improve the breakdown voltage, we suggested applying a gate-head extended structure. The gate-head-top and gate-head-bottom lengths of the basic T-gate HEMT were symmetrically extended by 0.2 μm steps up to 1.0 μm. The breakdown voltage of the 1.0 μm extended structure was 52% higher than that of the basic T-gate HEMT. However, the cutoff frequency ( f T ) and maximum frequency ( f m a x ) degraded. To minimize the degradation of f T and f m a x , we additionally introduced a gate-recessed structure to the 1.0 μm gate-head extended HEMT. The thickness of the 25 nm AlGaN barrier layer was thinned down to 13 nm in 3 nm steps, and the highest f T and f m a x were obtained at a 6 nm recessed structure. The f T and f m a x of the gate-recessed structure improved by 9% and 28%, respectively, with respect to those of the non-gate-recessed structure, and further improvement of the breakdown voltage by 35% was observed. Consequently, considering the trade-off relationship between the DC and RF characteristics, the 1.0 μm gate-head extended HEMT with the 6 nm gate-recessed structure was found to be the optimized AlGaN/GaN HEMT for high-power operations. [ABSTRACT FROM AUTHOR]

In this paper, a new efficient technique is used in silicon-on-insulator metal–semiconductor field-effect transistors (SOI MESFETs) to simultaneously increase the breakdown voltage and drain current and also improve the frequency parameters. This proposed structure is presented for SOI MESFET with; he displaced gate contact toward the source region and creating distinct silicon oxide packets with different sizes under both sides of the gate electrode inside the channel. Gate electrode displacement from the middle of the device toward the source rises the transistor breakdown voltage. Increasing the distance between the drain and gate electrodes decrease the accumulation of equipotential lines in the corner of the gate on the drain side, and reduces the field, thereby increasing the breakdown voltage in the suggested device. In addition, moving the gate metal toward the source has negative effects on the frequency performance, so by adding two oxide zones on both sides of the gate region the device parasitic capacitances are suppressed to compensate the frequency performance. Numerical simulations reveal that the breakdown voltage in the basic and suggested structures are about 15 and 30 V, respectively. Also, the drain current of the presented structure shows a significant increase compared to its basic counterpart. Here, the maximum output power density is 0.32 W/mm for the presented device and 0.12 W/mm for the basic structure, indicating 166% enhancement. Also, the RF specifications of the suggested structure, including maximum available power gain, current gain, unilateral power gain, and maximum stable gain, were improved by 21, 66, 50, and 52%, respectively, and cutoff frequency in the basic structure is 19.5, increased to 21.5 GHz by applied adaptations. [ABSTRACT FROM AUTHOR]

In this Letter, we demonstrate the Schottky gated p-AlGaN/u-GaN/AlGaN p-channel field-effect transistors (p-FETs) with an extremely low interface state density of 2.5 × 1011 cm−2 eV−1. Benefiting from the high-quality Schottky interface with suppressed interface states, the excellent stability with negligible hysteresis is proved, even after ten sequential dual I–V sweeps at 150 °C. Meanwhile, the trap density, confirmed by the temperature-dependent conductance method, is still below 1012 cm−2 eV−1 at high temperature. Furthermore, the fabricated p-AlGaN/u-GaN/AlGaN p-FET with a gate to drain distance of 1.8 μm shows a breakdown voltage of −128 V and an effective on-resistance of 7.2 kΩ mm, which allows the further scale down in terms of the source–drain spacing to improve the conduction current for low voltage application. The ultra-stable I–V characteristics of the fabricated Schottky-gated p-AlGaN/u-GaN/AlGaN p-FETs show great potential for next-generation integrated circuit application at high temperatures. [ABSTRACT FROM AUTHOR]

The current collapse has been one of the most challenging problems in AlGaN/GaN high electron mobility transistors (HEMTs). In recent years, the virtual gate effect has been the most widely accepted cause of the current collapse effect. To effectively improve the current collapse effect and reduce the influence of the virtual gate effect on the device, a point‐contact gate AlGaN/GaN HEMT structure is proposed in this article. Tests show that the device has high transconductance, high cut‐off frequency, and good transfer, output, and breakdown characteristics. The maximum saturation drain current is 18 mA mm−1, the maximum transconductance is 200 mS mm−1, the breakdown voltage is 994 V, the maximum current gain is about 190 dB, and the cut‐off frequency is up to 206 GHz when the gate length and width are 0.1 μm × 0.001 μm. The experimental analysis shows that the point‐contact gate AlGaN/GaN HEMT structure shortens the gate length, thereby improving the virtual gate effect and effectively suppressing the current collapse effect, increasing the breakdown voltage of the device, and further improving the device performance, which lays the foundation for the future research of AlGaN/GaN HEMT. [ABSTRACT FROM AUTHOR]

The authors' present a silicon‐on‐insulator (SOI) laterally diffused metal‐oxide‐semiconductor field‐effect transistor (LDMOSFET) with β‐Ga2O3 , which is a large bandgap semiconductor (β‐LDMOSFET), for increasing breakdown voltage (VBR) and power figure of merit. The fundamental purpose is to use a β‐Ga2O3 semiconductor instead of silicon material due to its large breakdown field. The characteristics of β‐LDMOSFET are analysed to those of standard LDMOSFET, such as VBR, ON‐resistance (RON), power figure of merit (PFOM), and radio frequency (RF) performances. The effects of RF, such as gate‐drain capacitance (CGD), gate‐source capacitance (CGS), transit frequency (fT), and maximum frequency of oscillation (fMAX) have been investigated. The β‐LDMOSFET structure outperforms performance in the VBR by increasing it to 500 versus 84.4 V in standard LDMOSFET design. The suggested β‐LDMOSFET has RON ~ 2.3 mΩ.cm−2 and increased the PFOM (VBR2/RON) to 108.6 MW/cm2. All the simulations are done with TCAD and simulation models are calibrated with the experimental data. [ABSTRACT FROM AUTHOR]

Surface passivation impact on DC and RF characteristics of GaN MESFETs was studied using ATLAS simulator from Silvaco. It has been shown that when the relative permittivity, εr, of the inter-electrode passivation layers increases, the breakdown voltage as well as the maximum output power density increases thus improving the applications of the MESFET device in high voltage and high power. However, the high values of relative permittivity lead to an increase in the gatesource CGS and gate-drain CGD capacitances on which the radio frequency performance of GaN MESFET transistors depends strongly. In effect, this increase leads to a limitation of the performances, RF of the GaN MESFET transistors. Finally, the variations of the parameters studied as a function of εr have been quantified and mathematical expressions are established. These formulas can be very useful for the judicious choice of the passivation layer in GaN MESFETs. [ABSTRACT FROM AUTHOR]

Nonlinearity operation and early gain suppression limit the high‐frequency operation of GaN‐HEMTs. Nonlinear transconductance and resistance drop‐off at relatively large VGS are the major sources for the nonlinear operation of the high electron mobility transistors (HEMTs). In this article, we present the In0.1Ga0.9N channel‐based HEMTs for stable transconductance operation. The device performance is evaluated for both Al0.3Ga0.7N, and In0.17Al0.83N barrier materials with silicon nitride passivation. The In0.17Al0.83N/In0.1Ga0.9N/GaN heterostructure device shows remarkable improvement in gate voltage swing than Al0.3Ga0.7N/In0.1Ga0.9N/GaN. LG 55 nm T‐gate In0.17Al0.83N/In0.1Ga0.9N HEMT exhibited 5 A/mm of maximum drain current density (IDS, max) for 1 V gate bias, 0.72 S/mm of stable transconductance (gm,max), 43.5 V of off‐state breakdown voltage (VBR), and 275/289 GHz of fT/fmax. The HEMT with AlGaN/InGaN/GaN heterostructure showed 2.81 A/mm of maximum drain current density for 1 V gate bias, 0.66 S/mm of stable transconductance, 55.3 V of VBR, and 252/263 GHz of fT/fmax. Moreover, a highest theoretical OIP3 value of 61.2 and 67.6 dBm obtained for AlGaN and InAlN barrier HEMTs, respectively. The proposed InGaN/GaN channel‐based HEMTs are more reliable for high‐frequency linear operation. [ABSTRACT FROM AUTHOR]

In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with a 2D numerical simulator—ATLAS. The investigation results have demonstrated that the breakdown voltage in the proposed structure is enhanced by 21.2%, and the FOM is improved by 39.6%. In addition, the proposed structure has an increased short-circuit capability. [ABSTRACT FROM AUTHOR]

Shallow trench isolation drain extended MOS (STI-DeMOS) devices, known for their superior gate oxide reliability under high drain voltages, are widely used for the integration of CMOS-compatible high-voltage devices. However, they offer moderate high-frequency performance that limits the use of these devices even in mid-band 5G applications. A novel island drain and a double-gate drain-extended MOS (IDDG DeMOS) device with improved high-frequency performance is proposed in this work. The proposed device has a core MOSFET and an STI-DeMOS with a self-aligned pocket well, both feature a shorter channel length than a typical STI-DeMOS device. The shorter gate length enhances the proposed device’s RF performance without degrading the breakdown voltage. We have performed simulations using a well-calibrated deck in the Sentaurus TCAD environment. We have shown an increase in the transit frequency from 25 GHz in STI-DeNMOS to 53 GHz in the proposed IDDG DeNMOS device, and from 11 to 31 GHz for a p-type device at a 65-nm technology node. This work also presents the well edge variation immunity of the proposed device. All these features are achieved in the mainstream SoC-compatible CMOS process flow without any additional fabrication mask or process complexity. [ABSTRACT FROM AUTHOR]

In this paper, a new lateral double-diffused metal oxide semiconductor (LDMOS) device is presented by considering the SiC window under the drift region and in the buried oxide. The SiC region with a higher band gap than silicon is useful for increasing the breakdown voltage. However, the mismatch of the SiC and silicon limits the application of this material. In the new SiC window in the LDMOS (SCW-LDMOS) structure, a Si3N4 layer is considered between the silicon of the drift region, as well as interface charges at the interface of the SiC/SiO2. Simulation with the two-dimensional ATLAS simulator shows that the SCW-LDMOS transistor has higher breakdown voltage than the conventional LDMOS structure (C-LDMOS). Moreover, the SiC window creates new peaks in the horizontal electric field and thus reduces the main peaks, which is the main reason for achieving high breakdown voltage. To achieve excellent performance of the new proposed transistor, accurate values of the SiC length, thickness, and doping density are determined. Also, the proper thickness of the Si3N4 is chosen in this study. [ABSTRACT FROM AUTHOR]

In the present study, a silicon on insulator metal–semiconductor FET (SOI MESFET) with embedded metal and L-shaped oxide layers (EMLO) is introduced. This structure consists of two-part oxide section (stepped) in the channel area and a nickel-metal layer in the upper part of the buried oxide, where the dimensions have been optimized to achieve the proper result. We named this structure briefly as EMLO-SOI MESFET. The performed simulations show that the presence of the mentioned variations causes noteworthy enhancement in breakdown voltage. The additional oxide sheet at the top of the channel has greater critical electric field than silicon. Also, the metal layer scatters the potential lines at the edge of the gate and inside the drift layer. As a result, the breakdown voltage experience 41% improvement. Drain current also increases by 42% in the proposed structure. The study on the maximum output power density shows 108% increase for new structure. The result reveals that both maximum oscillation and cut-off frequencies are increased by about 23% compared to the conventional structure. This improvement in RF parameters is due to the modifications in GS and DS capacitances. [ABSTRACT FROM AUTHOR]

A small subthreshold swing (SS) hydrogen-terminated diamond field-effect transistor is realized by using a wide bandgap material (SnO2). Results showed an SS of 106.4 mV/dec, which should be ascribed to the low interface state density (1.05 $\times10$ 12 cm $^{-2}\cdot $ eV−1) between SnO2 and diamond. The fixed charge density and trapped charge density are $1.1\times10$ 12 cm−2 and $8.6\times10$ 11 cm−2, respectively. Leakage current between source and gate is less than $2.1\times10$ −8 A at gate voltages from −5.0 to 1.0 V and the breakdown voltage is measured to be −180 V. In addition, the devices exhibit normally- OFF characteristics, whose threshold voltage and maximum drain current density are −0.12 V and −21.6 mA/mm with 4- $\mu \text{m}$ gate at ${V}_{GS} = -3$ V. The ON/OFF ratio is around 107 and the maximum effective mobility is extracted to be 165 cm2/(Vs). This work indicates that SnO2 dielectric could form low interface state density with hydrogen-terminated diamond surface and it also provides a simple method to realize normally- OFF devices. [ABSTRACT FROM AUTHOR]

A hybrid Schottky–ohmic drain technology for millimeter-wave (mmW) AlGaN/GaN high-electron-mobility transistors (HEMTs) is proposed. The Schottky metal extension in the ohmic region of drain reduces the actual source–drain spacing, resulting in a smaller ON-resistance and a higher maximum current. Extended Schottky metal in the drain region modulates the electric-field distribution, thereby leading to an improved breakdown voltage, suppressed current collapse, and high reliability. Compared with the ohmic drain, the current gain cutoff frequency (${f}_{T}$) was improved from 64 to 76 GHz, and the maximum oscillation frequency (${f}_{\text {max}}$) was improved from 125 to 157 GHz, resulting from the decreased parasitic drain resistance (${R}_{d}$). Moreover, large-signal measurements in continuous wave (CW) at 30 GHz demonstrated a peak power-added efficiency (PAE) of 45.5% and a saturated output power density (${P}_{\text {sat}}$) of 8.5 W/mm at ${V}_{\text {ds}}= {30}$ V. In addition, the direct current (DC) and radio frequency (RF) characteristics showed a negligible degradation after large-signal measurements at 30 GHz. [ABSTRACT FROM AUTHOR]

An improved 4H-SiC metal–semiconductor field-effect transistor (MESFET) with a double-symmetric-step buried oxide layer is proposed, and the mechanism is studied through TCAD simulation. The double-step buried oxide layer is mainly to improve the drain current and reduce the leakage current to the substrate. At the same time, the oxide layer changes the electric field distribution, and the breakdown voltage (Vb) is improved. The charge distribution of the device is also changed, and the frequency characteristics are also improved. The results show that the Vb and maximum output power density (Pout) are about 14% and 21.8% larger than those of the double-recessed (DR) 4H-SiC MESFET, respectively. In radio frequency characteristics, cutoff frequency (ft) and maximum oscillation frequency (fmax) are 11.9% and 20.3% higher than those of the DR MESFET. The maximum power-added efficiency in the L-band and S-band reaches 63.5%, which is 23.7% higher than in the DR structure. Compared with the 4H-SiC MESFET reported in recent years, the proposed structure has great advantages in high-frequency applications. [ABSTRACT FROM AUTHOR]

In this work, we examine the direct-current (DC) behavior and the radio frequency (RF) performance of both single-gate simple-channel (SGSC), single-gate double-channel (SGDC) and double-gate double-channel (DGDC) AlGaN/GaN/BGaN high electron mobility transistor (HEMT) with BGaN back-barriers consist of 250 nm gate length. Using technology computer aided design (TCAD) Silvaco, our isothermal simulation results reveal that the proposed structure of double-gate double-channel HEMT with BGaN back-barriers (DGDCBB HEMT) increases electron concentration and consequently the saturation drain current, breakdown voltage, the transconductance. On the other hand, decreases the gate leakage current compared to a conventional HEMT and to a double-channel HEMT back-barriers. Furthermore, the proposed double-gate double-channel backbarrier HEMT device shows good cutoff frequency (94 GHz) and a maximum oscillation frequency (170 GHz). These results suggest that double-gate double channel HEMT back-barriers could be useful for high frequency and high-power microwave applications. [ABSTRACT FROM AUTHOR]

In this study, design considerations of a new device structure are presented to improve the self‐heating effect (SHE) and the breakdown voltage of the Deep Gate LDMOS (Lateral Double Diffused Metal Oxide Semiconductor) transistor and compared with a conventional LDMOS (C‐LDMOS). In this case, triple oxide trenches with an N+ trench are embedded in the drift region. These trenches create additional peaks in the electric field profile, so the electric field is modified. The authors demonstrate that by optimising the trenches, the breakdown voltage of the device increases. Also, a partially buried oxide is used in the proposed structure to create a conduction path that significantly reduces the SHE. Moreover, the results indicate that the specific on‐resistance, lattice temperature, and breakdown voltage of the proposed device are improved considerably compared to the C‐LDMOS. [ABSTRACT FROM AUTHOR]

In this work, a novel trench-gated CAVET featuring a p-GaN island for breakdown voltage improvement is proposed. The p-GaN island inserted between the two p-GaN current-blocking-layer (CBL) constructs a dual-current-aperture vertical transistor (DCAVET), which enables to engineer the electric-field (E-field) distribution in the buried p–n-junction for voltage sustaining. The device operation mechanism and characteristics were investigated by TCAD simulation. By delicately designing the device structural parameters and optimizing the doping concentration, the premature punchthrough and high ${E}$ -field induced avalanche breakdown were effectively suppressed at even higher reverse blocking voltage. The proposed DCAVET achieves excellent balance between punchthrough and avalanche breakdown, delivering a high breakdown voltage of 1504 V and low ${R}_{\text {on,sp}}$ of 0.77 $\text{m}\Omega \cdot $ cm2. The trench gate DCAVET demonstrates a flexible approach to engineer the ${E}$ -field distribution to achieve kilo-volts GaN power transistors. [ABSTRACT FROM AUTHOR]

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance RON, breakdown voltage VBR, threshold voltage VTH, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance RDSon, where a 14 % increase was observed after 6 · 107 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I -- V curves was observed with considerable impact on the RON where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance CDG and input capacitance Cin was observed in all three types of analysed structures. DLTS was used to verify the generation/ activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO2 and on interfaces were detected on stressed samples. [ABSTRACT FROM AUTHOR]

We fabricated AlN metal semiconductor field effect transistors (MESFETs) with an epitaxially grown n-type AlN channel layer and characterized the temperature dependence of their device properties. As the temperature was varied from room temperature to 500°C, maximum drain current increased from 0.42 to 45 mA/mm and maximum transconductance increased from 0.05 to 4.5 mS/mm. This enhanced device performance with increasing temperature is attributed to increased carrier concentration in n-type AlN due to the large ionization energy of Si donors. Owing to a large Schottky barrier height of 2.08 eV for the Ni gate electrode/n-type AlN interface, reverse leakage current is less than $10^{-{10}}$ A/mm at temperatures ranging from room temperature to 500°C. Off-state breakdown voltage is as high as 1720 V for gate-drain spacing of 16 ${\mu }\text{m}$. These results indicate that AlN MESFETs are promising for high-voltage electronic devices operating at high temperature. [ABSTRACT FROM AUTHOR]

Discharge in dielectric liquid is an active field of research involved in many technological applications. Such multiple discharges are often applied during an experiment and that the electrode and liquid are altered by these stochastically behaving discharges. Therefore, it is important to address the variation of discharge characteristics as a function of discharge occurrence. In this study we analyze the electrical characteristics of multiple discharges run at low repetition rate (5 Hz) in a liquid of known initial composition using an electrode with a specific geometry. The discharges are run continuously until they fail to occur due to the increase in gap distance, and the recorded voltage and current waveforms are processed using an algorithm in order to determine the probability of discharge occurrence, breakdown voltage, discharge current, and discharge delay. The injected charge and energy of each discharge are also calculated. Furthermore, the effects of applied voltage, pulse width, electrode configuration, and liquid composition on the characteristics of the discharge are investigated. The obtained results demonstrate that the highest and lowest numbers of occurred discharges are achieved using the plate-to-plate and pin-to-pin configurations, respectively. Moreover, the composition of the liquid has an appreciable effect on the discharge current, as well as on electrode erosion. For discharges in water and cyclohexane, we measured the lowest and highest current, respectively. As for the erosion rate, it was comparable for the three liquid hydrocarbons but relatively smaller than that in water. The plot of breakdown voltage as a function of discharge current varies depending on the discharge parameters and displays regions that may be linked to the ignition mechanisms. The original data reported herein is of great significance for various applications that utilize repetitive discharges in liquid. [ABSTRACT FROM AUTHOR]

In this Letter, the p-GaN high electron mobility transistor (HEMT) with hybrid drain of recessed Schottky (RS) and p-GaN isolation blocks' drain (HSP drain) is proposed and fabricated for good reverse blocking capability. The related operation mechanism has been investigated and revealed. The proposed device features a drain terminal consisting of the array-distributed recessed Schottky and p-GaN isolation blocks. Based on the features, the reverse leakage current (5 × 10−9 A/mm at VDS = −100 V) is obviously reduced by two orders of magnitude compared with that (5 × 10−7 A/mm) of p-GaN HEMTs only with recessed Schottky (RS) drain, which is the lowest leakage current among the reported GaN-on-Si reverse blocking transistors. The introduction of these p-GaN isolation blocks has a negligible impact on Von (Von = 0.63 V). Therefore, a good improvement in the trade-off between the reverse leakage current and Von could be achieved because of the significant reduction in the reverse leakage current without sacrificing Von. In addition, the reverse breakdown voltage of −800 V at 1 μA/mm with a substrate grounded in the proposed device is evidently improved compared with the counterpart (−680 V), which is attributed to effective alleviation of the high electric field near the HSP drain. These results demonstrate the significance and potential of p-GaN HEMTs with HSP drain in reverse blocking applications. [ABSTRACT FROM AUTHOR]

ScAlN/GaN dielectric superjunction high-electron-mobility transistors (HEMTs) with high-k passivation layer Bi1.5Zn1.0Nb1.5O7 (BZN) are demonstrated for enhancement of breakdown voltage. The BZN thin film deposited by RF magnetron sputtering has a dielectric constant of 192 after postdeposition annealing at 400 °C for 10 min. The HEMT with Lg = 200 nm and Lsd = 2.0 μ m has a maximum current density of 1.98 A/mm, a maximum transconductance of 0.52 S/mm, and a threshold voltage of Vth = −3 V. With the use of SiN/BZN/SiN sandwiched passivation layer, the average value of breakdown voltage is improved from 68.9 to 121.5 V, due to the reduction of the peak electrical field between the gate and the drain. The device has a cutoff frequency (ƒT) and maximum oscillation frequency (ƒmax) of 59 and 69 GHz, respectively. Overall, the devices exhibit a significantly higher breakdown voltage with essentially the same ƒT and ƒmax values. Pulse measurements suggest that SiN/BZN/SiN has a similar passivation effect in comparison with devices passivated by a SiN-only layer. This work demonstrates that high current and high breakdown voltage can be achieved simultaneously on semiconductor heterostructures with a high sheet charge density by integration of high-k dielectrics. [ABSTRACT FROM AUTHOR]

High-performance AlGaN/GaN lateral Schottky barrier diodes (SBDs) with recess structure and dual metal nitride anodes were demonstrated. With high work-function and nonrecess structure, a NiN anode enhances the breakdown voltage (BV), while a TiN anode reduces the turn-on voltage (VON) due to its low work-function and contact to the two-dimensional electron gas (2DEG) layer directly on a recess structure. As the length of the NiN anode (Lr) on the nonrecess region decreases from 75 to 3 μm, VON is reduced from 0.56 to 0.30 V, while the reverse leakage current slightly increases from 3 × 10−4 to 2 × 10−3 A/cm2 at the bias of −10 V. The lateral AlGaN/GaN SBD with a Lr of 3 μm at a distance of cathode–anode (LAC) of 20 μm achieves a high BV of 1.62 kV, an ultralow VON of 0.30 V and a small capacitance of 6.0 pF at zero bias with little degradation on ON-resistance, indicating superior potential application in high-frequency and high-power devices. [ABSTRACT FROM AUTHOR]

In this article, a mathematical model is presented for the drain current and electric field of silicon carbide gate all around junctionless field effect transistors (SiC GAA JLFETs). The model is based on an accurate description of the device structure and takes into account the detailed charge distribution in the transistor. The model is then used to predict the drain current and electric field in the device, which can be useful for device optimization. It is possible to achieve a more efficient volume depletion by including a P+ pocket on both the source and drain side regions of the JLFET. This results in a widening of the tunneling width at the channel-drain interface. A reduction of orders of 10−15 is achieved in the L-BTBT's OFF-state current. Additionally, the model can be used to study how the P+ pocket impacts the distribution of the electric field in JLFETs. The widening of the tunneling width at the channel-drain interface helps to reduce the resistance of the channel in the OFF-state, resulting in a decrease in OFF-state current. Furthermore, the P+ pocket helps to reduce the electric field intensity in the channel, which helps to reduce the switching time of the device. The wide band gap material of SiC makes the device temperature-resistant at high drain voltages. P+ pocket SiC GAA JLFETs have been studied using an analytical model incorporating Poisson's equation for nanowires. The analytical model shows that the device has a good trade-off between on-resistance and breakdown voltage. The SiC GAA JLFETs also show excellent thermal stability. Based on simulation results obtained from the SILVACO TCAD, a further validation of the analytical model's analog performance has been conducted, and the simulation results have been well in agreement with the proposed analytical model's analog performance. • A temperature-dependent compact model for the drain current and electric field of SiC GAA JLFETs that takes into account the P+ pocket has been developed. • The analog performance of the proposed device as a function of the temperature and the length of the P+ pocket has been discussed. As a result of fully efficient volume depletion occurring even beyond the gate edges of the SiC GAA JLFETs with P+ pockets and into the source and drain regions, the OFF-state current has been significantly reduced. • WBG material SiC enhances breakdown voltage and raises ON-state current in high temperature NW JLFET. Improved SiC channel mobility lowers resistance, reduces the gate charge of the transistor. The ON-state current also increases as the P+ pocket is lengthened. [ABSTRACT FROM AUTHOR]

In this work, flexible ferroelectric films of P(VDF‐TrFE) softened by a plasticizer are elaborated. Morphology, piezoelectric, mechanical, thermal, and crystalline properties of the films are studied. We show that the elastic constant is reduced up to 30% while increasing the remanent polarization and the piezoelectric coefficient thanks to the lubricant property of the plasticizer, helping the orientation of the crystallites. Plus, the decrease of the coercive field from 46 to 32 V/μm after an annealing at 138°C for a plasticizer content ranging between 20 and 50 wt% is observed and an explanation by based on a polymer/plasticizer demixing is provided. It leads to an easier polarization process with a significant saving in time and applied electric field reducing the breakdown voltage. Both effects could be interesting for an industrial production. Finally, a first sensor is elaborated and characterized electrically with homemade test bench. We show that the softening of the P(VDF‐TrFE) offers to the device a larger amplitude range of deformations. The combination of the flexibility with high ferroelectric properties of the plasticized P(VDF‐TrFE) make it a very promising material for biomedical sensor applications. [ABSTRACT FROM AUTHOR]

A novel silicon carbide (SiC) on silicon (Si) heterojunction lateral double-diffused metal–oxide semiconductor field-effect transistor with p-type buried layer (PBL Si/SiC LDMOS) is proposed in this paper for the first time. The heterojunction has breakdown point transfer (BPT) characteristics, and the BPT terminal technology is used to increase the breakdown voltage (BV) of Si/SiC LDMOS with the deep drain region. In order to further optimize the surface lateral electric field distribution of Si/SiC LDMOS with the deep drain region, the p-type buried layer is introduced in PBL Si/SiC LDMOS. The vertical electric field is optimized by Si/SiC heterojunction and the surface lateral electric field is optimized by the p-type buried layer, which greatly improves the BV of device and alleviates the relationship between BV and specific on-resistance (Ron,sp). Through TCAD simulation, when the drift region length is 20 μm, the BV is significantly improved from 249 V for the conventional Si LDMOS to 440 V for PBL Si/SiC LDMOS, increased by 77%; And the BV is improved from 384 V for Si/SiC LDMOS with the deep drain region to 440 V for the proposed structure, increased by 15%. The figure-of-merit (FOM) of the Si/SiC LDMOS with the deep drain region and PBL Si/SiC LDMOS are 4.26 MW/cm2 and 6.37 MW/cm2, respectively. For the PBL Si/SiC LDMOS with the drift length of 20 μm, the maximum FOM is 6.86 MW/cm2. The PBL Si/SiC LDMOS breaks conventional silicon limit. [ABSTRACT FROM AUTHOR]

In this work, 100, 200, and 400 nm SiO2 films are deposited on the electrode surface by magnetron sputtering, and the effect of film thickness on the insulation performance of propylene carbonate is studied. We use the Weibull distribution to calculate the breakdown voltage of propylene carbonate under different conditions. Space charge distribution of the liquid is measured based on the Kerr effect. Test results show that the breakdown voltage of propylene carbonate increases from 8.4 to 18.7% with increasing film thickness compared with the case where the SiO2 film is not deposited. Bipolar injection mode of space charge is not affected by the increase of SiO2 film thickness, but the amount of space charge injection is significantly reduced. The thicker the SiO2 film deposited on the electrode surface, the higher the ratio of increasing the breakdown voltage of propylene carbonate, but the smaller the magnitude of the increase. [ABSTRACT FROM AUTHOR]

This paper reports on the fabrication of an enhancement-mode AlGaN/GaN metal-insulator-semiconductor-high electron mobility transistor with a new barrier epi-layer design based on double Al0.2Ga0.8N barrier layers separated by a thin GaN layer. Normally-off transistors are achieved with good performances by using digital etching (DE) process for the gate recess. The gate insulator is deposited using two technics: plasma enhance chemical vapour deposition (sample A) and atomic layer deposition (sample B). Indeed, the two devices present a threshold voltage (Vth) of +0.4 V and +0.9 V respectively with ΔVth about 0.1 V and 0.05 V extracted from the hysteresis gate capacitance measurement, a gate leakage current below 2 × 10−10 A mm−1, an ION/IOFF about 108 and a breakdown voltage of VBR = 150 V and 200 V respectively with 1.5 µm thick buffer layer. All these results are indicating a good barrier surface quality after the gate recess. The DE mechanism is based on chemical dissolution of oxides formed during the first step of DE. Consequently, the process is relatively soft with very low induced physical damages at the barrier layer surface. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage (VBR) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of 18.5 μm exhibits a VBR of 1344 V at ID of 1 μA/mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high IDS,max of 450 mA/mm and a low specific ON-resistance of 3.92 mΩ·cm2. Moreover, a large threshold voltage of 1.6 V (at ID of 10 μA/mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications. [ABSTRACT FROM AUTHOR]

A novel silicon-on-insulator lateral insulated gate bipolar transistor (SOI LIGBT) is proposed in this paper. The proposed device has a P-type buried layer and a partial-SOI layer, which is called the BPSOI-LIGBT. Due to the electric field modulation effect generated by the P-type buried layer and the partial-SOI layer, the proposed structure generates two new peaks in the surface electric field distribution, which can achieve a smaller device size with a higher breakdown voltage. The smaller size of the device is beneficial to the fast switching. The simulation shows that under the same size, the breakdown voltage of the BPSOI LIGBT is 26% higher than that of the conventional partial-SOI LIGBT (PSOI LIGBT), and 84% higher than the traditional SOI LIGBT. When the forward voltage drop is 2.05 V, the turn-off time of the BPSOI LIGBT is 71% shorter than that of the traditional SOI LIGBT. Therefore, the proposed BPSOI LIGBT has a better forward voltage drop and turn-off time trade-off than the traditional SOI LIGBT. In addition, the BPSOI LIGBT effectively relieves the self-heating effect of the traditional SOI LIGBT. [ABSTRACT FROM AUTHOR]

A Ka-band AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) with SiN gate dielectric grown by plasma-enhanced atomic layer deposition (PEALD) is demonstrated. The gate reverse leakage current in a controlled HEMT is reduced by about three orders of magnitude by the PEALD-SiN, contributing to an improved breakdown voltage of 92.5 V (source–drain separation of 2.0~μm) in the fabricated MIS-HEMTs. The MIS-HEMTs also feature small threshold voltage hysteresis in dc transfer and capacitance–voltage characterizations, suggesting a good PEALD-SiN/AlGaN interface. The fabricated MIS-HEMTs deliver a high output power density of 7.16 W/mm and a peak power-added efficiency of 60.3%, respectively, at VDS = 30 V and VDS = 10 V in pulse mode at 28 GHz. PEALD-SiN could be a compelling gate dielectric for fabrication of high-power and high-efficiency MIS-HEMTs. [ABSTRACT FROM AUTHOR]

We demonstrate a high-performance normally-OFF AlGaN/GaN fin metal–insulator–semiconductor high electron mobility transistor (fin-MISHEMT) on silicon with a low work function metal-source contact ledge (LWFM-SCL). In order to realize the normally-OFF operation, an optimized gate-recessed fin structure is used. The fin structure inherently containing a gate-connected field plate (FP) design improves the breakdown voltage (VBD). Moreover, the LWFM-SCL can improve the device overall ON-resistance (RON) by lowering the gate–source access resistance (Ra). The proposed device with a gate–drain length (LGD) of 7 μm exhibits superior characteristics such as a threshold voltage (VTH) of +1.2 V, maximum drain current (ID, max) of 825 mA/mm, ON-state/OFF-state current (ION/IOFF) ratio of 109–1010, subthreshold swing (SS) of 76 mV/decade, VBD of 810 V, and specific RON (Ron, sp) of 0.63 mΩ ⋅ cm2. It also possesses excellent VTH hysteresis, temperature stability, and dynamic RON characteristics. These results suggest that the proposed device is very suitable for high power switching applications. [ABSTRACT FROM AUTHOR]

This article reports the demonstration and fabrication of 400–600 V, 4H-SiC lateral MOSFETs on 6-in, N+ substrates. The P-top was implanted on an N-drift region to create a single reduced surface field (RESURF) structure to alleviate the electric field on the surface. The different layout methodologies (source-centered and drain-centered) for making lateral MOSFETs are discussed. The process and design split, such as rapid thermal anneal (RTA) temperatures (900 °C and 1000 °C), different channel designs [accumulation-mode (ACCU) and inversion-mode (INV)], and channel lengths were varied and experimentally analyzed to optimize the device performance. It was confirmed that channel components (channel design and channel length) and RTA temperature are the key ingredients to improve the forward characteristic of the lateral MOSFETs. With the gate to drain length (Lgd) of 5~μm , the breakdown voltage of 600 V was achieved with a voltage supporting capability of 120 V/μm. On the other hand, a lateral MOSFET with Lgd of 2.5~μm and with a further reduced channel length (Lch = {0.3 μm), a record specific ON-resistance of 7.7 m Ω-cm21 00.21a0nd breakdown voltage of 450 V were achieved. Device design, layout, fabrication, and electrical characteristics of the 400–600 V, 4H-SiC lateral MOSFETs are discussed and reported. [ABSTRACT FROM AUTHOR]

We survey impact-ionization coefficients for silicon, wide bandgap semiconductors (gallium nitride and 4H-silicon carbide), and ultrawide-bandgap semiconductors (aluminum gallium nitride, beta-gallium oxide, and diamond). We employ a custom genetic algorithm to fit those existing coefficients into a modified Thornber model. This fitting process leads to an estimation of material properties, such as ionization energy, optical-phonon energy, and mean free path. After evaluating electric-field profiles by solving the Poisson equation, we use the impact-ionization integral to fundamentally calculate the breakdown voltage and the critical field of various p-i-n structures. This work captures how the doping concentration and the thickness of the drift layer shape the breakdown voltage as well as the critical field achievable with a given material. It is observed that a wider bandgap is not the sole requirement for the achievement of a higher breakdown voltage. Impact-ionization coefficients and dielectric constants are additional material properties that influence the calculation of the breakdown voltage. The performance limits of diamond are found to be surprisingly poor for its large bandgap. AlxGa1–xN and β-Ga2O3have almost the same performance limits, but it is observed that aluminum gallium nitride can outperform gallium oxide at high voltage if its background doping (doping floor) can be reduced. [ABSTRACT FROM AUTHOR]

This paper presents a new structure of Metal Semiconductor Field Effect Transistor (MESFET) for high power applications. One of the problems that we face in the design of the MESFET devices is that in most cases, the increase of breakdown voltage is accompanied by a decrease in the saturation drain current. Our aim to propose this structure is to improve these two parameters simultaneously. Using the insulator region under the sides of the gate (IR) and the hide field plate (HFP) in the buried oxide (BOX) are the fundamental solution for improving these parameters. We named the proposed structure as spread potential contours towards the drain MESFET (SPC-MESFET). By applying the proposed structure, the drain current and the breakdown voltage improve 20 and 27 percent compared to a conventional structure (C-MESFET), respectively. Therefore, the proposed device has a higher maximum power density than the C-MESFET structure. Also, this idea reduces the gate capacitance and thus the frequency characteristics such as cut off frequency (fT), maximum oscillation frequency (fmax), and Maximum Available Gain (MAG) improve in comparison with the C-MESFET structure. [ABSTRACT FROM AUTHOR]

A novel self-modulated superjunction lateral double-diffused MOSFET (SM-SJ LDMOS) is proposed and experimentally realized in this letter. When a SJ is introduced into a lightly doped N-drift region, the 3-D depletion regions appear surrounding the P-pillars. This 3-D junction field effect transistor (JFET) effect decreases the current paths in both N-pillars and N-drift, causing a largely increased specific on-resistance ${R} _{\text {on,sp}}$ especially for the SJ with a narrow cell pitch. To suppress the inherent 3-D JFET effect, the SM-SJ structure is proposed by replacing the P-pillars with a series of P-islands. These P-islands with linearly reduced lengths modulate the surface electric field to increase the breakdown voltage ${V} _{{\text {B}}}$ while the N-drift areas between P-islands weaken the 3-D JFET effect to reduce ${R} _{\text {on,sp}}$. Compared with the conventional SJ device, the measured ${V} _{\text {B}}$ of the SM-SJ LDMOS is increased by 53.1% from 260 V to 398 V with ${R} _{on,sp}$ reduced by 22.3% from 35.4 $\text{m}\Omega ~\cdot $ cm2 to 27.5 $\text{m}\Omega ~\cdot $ cm2. [ABSTRACT FROM AUTHOR]

This study explores the breakdown properties of three C 4 F 7 N binary gas mixtures under lightning impulse and the reduction of dielectric strength in the presence of insulation defects. The 50% breakdown voltage (U 50%) of three C 4 F 7 N binary gas mixtures in a quasi-uniform electric field is observed to determine the basic dielectric strength, which has the ranking C 4 F 7 N/Air ≈ C 4 F 7 N/CO 2 > C 4 F 7 N/N 2. A coefficient S E is introduced to quantitatively describe the sensitivity of dielectric strength to electric field inhomogeneity. The S E of different gas medium can be ranked as SF 6 < C 4 F 7 N/CO 2 < C 4 F 7 N/Air < C 4 F 7 N/N 2 , indicating that C 4 F 7 N mixed with nitrogen, carbon dioxide, or dry air is less capable of tolerating insulation defects than SF 6 , which merits consideration in insulation designs. [ABSTRACT FROM AUTHOR]

A GaN-based current-aperture vertical electron transistor with source-connected field-plates (SFP-CAVET) is proposed and investigated by means of two-dimensional simulations. This device is characterized by the source-connected field-plates (SFP) at both sides, which leads to remarkable improvement of breakdown voltage (BV) without degradation of specific on-resistance (Ron). Systematic analyses are conducted to reveal the mechanism of the SFP modulation effect on the potential and the electric field distributions and thus the BV improvement. Optimization and design of SFP-CAVET are performed for the maximum BV. Simulation results exhibit a Ron of 2.25 mΩ · cm2 and a significantly enhanced BV of 3610 V in SFP-CAVET, indicating an average breakdown electric field of more than 240 V μm−1. Compared with conventional CAVET, both BV and average breakdown electric field in SFP-CAVET are increased by more than 121% while Ron remains unchanged. And the trade-off performance of BV and Ron in SFP-CAVET is also better than that in GaN-based CAVET with superjunctions (SJ CAVET). In addition, the fabrication process issues of the proposed SFP-CAVET are also presented and discussed. These results could break a new path to further improve the trade-off performance of BV and Ron in GaN-based vertical devices. [ABSTRACT FROM AUTHOR]

In this article, a novel 3.3-kV integrated emitter turn-off thyristor (IETO) with single-gate controlling is proposed. Unlike the conventional emitter turn-off thyristor (ETO) using external MOSFETs, the IETO integrates the MOSFETs monolithically to switch ON and OFF. By featuring a P-layer beneath the trench of the carrier store trench bipolar transistor (CSTBT) to form self-biased pMOSs, the IETO clamps the potential of the P-layer, which shields the potential of the N-layer (carrier-stored layer), to reduce the saturation current. Due to the “self-clamping” effect, the high reverse voltage is sustained by the P-layer/N-drift junction, which makes the breakdown voltage (BV) independent of the dose of the N-layer. Then, the N-layer can be heavily doped to reduce VON without sacrificing the BV. TCAD simulation is compared with the CSTBT, which has the same controllability as the IETO and indicates that under the same level of BV, VON of the IETO is reduced by 0.12 V at EOFF ≈ 8.5 mJ/cm2, and the EOFF is 51.1% lower at VON ≈ 1.45 V. Moreover, the saturation current density is also reduced by 12.2%. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high electron mobility transistors (HEMTs) on chemical vapor deposited (CVD) diamond with different gate–drain spacings (Lgd) are fabricated, and off‐state breakdown voltage (BVgd) along with a dynamic specific on‐resistance (Dyn.‐Ron,sp) is measured. Ron,sp is obtained in the range of 0.32–0.98 mΩ cm2 for HEMTs with Lgd of 2–8 μm. The HEMTs exhibit a BVgd of 415 V (Lgd = 8 μm) with a maximum lateral breakdown strength of 0.72 MV cm−1. The power device figure of merit (FOM) of ≈0.18 GW cm−2 is obtained from HEMTs with Lgd of 8 μm. The HEMTs exhibit about 60% of higher FOM when compared with the reported HEMTs on CVD diamond (≈0.11 GW cm−2). This is mainly due to the improvement of Ron,sp through the reduction of contact resistance (Rc) and sheet resistance (Rsh). The Dyn.‐Ron,sp is estimated from pulsed (pulse width/period = 200 ns/1 ms) ID–VD characteristics, which is comparable with the static Ron,sp. These improved results of the fabricated AlGaN/GaN HEMTs on CVD diamond make it a promising candidate for high‐voltage power switching device applications. [ABSTRACT FROM AUTHOR]

In this study, we investigated AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) with single-metal gate (SMG) and dual-metal gate (DMG) structures through experimental measurements and technology computer-aided design simulation. The DMG structure consists of nickel (Ni) in the source-side gate and titanium (Ti) in the drain-side gate metals for the distribution of an electric field. The measurement results demonstrate that the fabricated AlGaN/GaN DMG–MISHEMT produces improved device performances; this includes higher drain current (ID), higher transconductance (gm), and higher breakdown voltage than the SMG–MISHEMT. The improvement is due to the distribution of an electric field. In addition, in terms of current collapse characteristics, the DMG–MISHEMT exhibited a small change rate in ID at various quiescent bias points. These results mean that a DMG structure leads to excellent electrical characteristics. [ABSTRACT FROM AUTHOR]

Herein, a unique device‐design strategy is reported for increasing the breakdown voltage and hence Baliga figure of merit (BFOM) of III‐nitride high electron mobility transistors (HEMTs) by engineering the gate edge toward the drain. The breakdown of such devices with meandering gate‐drain access region (M‐HEMT) are found to be 62% more compared with that of conventional HEMT whereas the on‐resistance suffers by 76%, leading to an overall improvement in the BFOM for by 28%. The 3D technology computer‐aided design simulations show that the decrease in the peak electric field at the gate edge was responsible for increased breakdown voltage. [ABSTRACT FROM AUTHOR]

A novel Lateral Double-Diffused MOSFET (LDMOSFET) with ultra-low resistance is investigated by experiments. The proposed LDMOSFET features an extended gate field plate consisting of two back-to-back diodes. In the ON state, the electron accumulation layer is formed below the gate field plate and greatly reduces the resistance of the drift region. In the OFF state, the field plate assists in depleting the drift region and modulates the electric field distribution of the drift region, which ensures high breakdown voltage (BV). The key fabrication process steps for the proposed device are given. The fabricated prototype device shows specific on-resistance (${R} _{{\text {on},\text {sp}}}$) of 70 $\text{m}\Omega \cdot $ cm2 and BV of 680 V, which is superior performance for reported 600 V-rated lateral devices. The ${R} _{{\text {on},\text {sp}}}$ of the proposed LDMOSFET is decreased by 50% compared with the LDMOSFET without accumulation effect. [ABSTRACT FROM AUTHOR]

A novel edge-termination structure for a SiC trench metal–oxide semiconductor field-effect transistor (MOSFET) power device is proposed. The key feature of the proposed structure is a periodically formed SiC trench with a bottom protection well (BPW) implantation region. The trench can be filled with oxide or gate materials. Indeed, it has almost the same cross-sectional structure as the active region of a SiC trench MOSFET. Therefore, there is little or no additional process loads. A conventional floating field ring (FFR) structure utilizes the spreading of the electric field in the periodically depleted surface region formed between a heavily doped equipotential region. On the other hand, in the trenched ring structure, an additional quasi-equipotential region is provided by the BPW region, which enables deeper and wider field-spreading profiles, and less field crowding at the edge region. The two-dimensional Technology Computer Aided Design (2D-TCAD) simulation results show that the proposed trenched ring-edge termination structures have an improved breakdown voltage compared to the conventional floating field ring structure. [ABSTRACT FROM AUTHOR]

A lateral double diffused metal oxide semiconductor transistor with the semi-superjunction (semi-SJ LDMOS) is optimized based on the normalized current-carrying capability (CC) and experimentally realized in this letter. The device is fabricated based on an optimized equivalent substrate and the semi-SJ is introduced near the source. The semi-SJ increases the local doping concentration in the N regions meanwhile reduces the current path area and carrier mobility, resulting in the variation of CCs before and after the introduction of the semi-SJ. The normalized CC factor $\eta _{\text {C}}$ is proposed to evaluate this variation, with which the minimum specific on-resistance ${R} _ {\text {ON}, \text {sp}}$ is predicted by the condition of $\eta _{\text {C}}= {1}$. The experiments of the semi-SJ LDMOS exhibit a minimum ${R} _ {\text {ON}, \text {sp}}$ of 25.5 $\text{m}\Omega \cdot $ cm2 under a breakdown voltage ${V} _{{\text {B}}}$ of 464.3 V. This represents a reduction in ${R} _ {\text {ON}, \text {sp}}$ by 37.7% when compared with the theoretical ${R} _ {\text {ON}, \text {sp}}$ of triple RESURF devices. [ABSTRACT FROM AUTHOR]

A 600 V-class step patterned gate oxide trench (SPGOT) superjunction vertical device incorporating gate engineering is proposed in this paper. An n + polysilicon gate is segregated into three steps of varied length and oxide thickness. To improve the device performance, the gate oxide in the SPGOT structure is narrow towards the source and wide towards the drain. This modification increases the gate–source capacitance, indicating higher transconductance, and reduces gate–drain capacitance, suggesting lower switching delay. The gate length is optimized to achieve enhanced performance indicators. Electrical performance is investigated and analyzed using 2-D numerical simulations. The optimized results reveal 9.7% and 26.14% reduction in specific resistance ( R on · A ) and gate–drain charge ( Q GD · A ), respectively, without any reduction in breakdown voltage. The engineered gate structure further exhibits a 43% and a 33.2% improvement in switching delay and figure of merit ( R on · A × Q GD · A ), respectively, over a conventional device. [ABSTRACT FROM AUTHOR]

In order to better shield the substrate-assisted depletion (SAD) effect and improve the breakdown voltage of super-junction (SJ) devices, an SJ lateral double-diffusion metal oxide semiconductor device with a gradient charge compensation layer (gradient device) is proposed. The main feature of this structure is to introduce a gradient charge compensation layer between the SJ layer of a conventional device and the substrate. The depth of the gradient charge compensation layer increases gradually from the source to the drain. The charge distribution in the drift region is optimized by reducing the compensation charge on the side near the source and increasing the compensation charge on the side near the drain. Introduction of the layer improves shielding of the SAD effect, and the electric field on the surface of the structure is an approximately rectangular distribution, thus the breakdown voltage is improved. The simulation results show that the gradient device has 409-V breakdown voltage and a 9.5-MW cm−2 figure of merit with a drift region length of 21 μm. Compared with the conventional SJ structure (conventional device) with the same drift length, the breakdown voltage and figure of merit of the gradient device are increased by 57.3% and 137.5%, respectively. [ABSTRACT FROM AUTHOR]