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Massively parallel chip assembly based on multi-interposer block concept is demonstrated for large-area heterogeneous system integration. The chips are aligned in parallel by liquid surface tension and assembled on the Si interposers through oxide-oxide bonding at room temperature without thermocompression. 3-D Cu sidewall interconnects (the width is approximately 20~\mu \textm ) climbing over 100- \mu \textm -thick self-assembled chips are formed with a spin-on thick photoresist by electroplating. In addition, 3-D Cu interconnects with a width of nearly 10~\mu \textm are successfully formed across polyimide slopes formed on the sidewall of self-assembled chips. The electrical properties of the 3-D sidewall interconnects are characterized by the daisy chains, resistance distribution, and characteristic fluctuation of CMOS fabricated on the self-assembled chips. [ABSTRACT FROM AUTHOR]

A new 3-D integration concept based on reconfigured wafer-to-wafer stacking is proposed. Using reconfigured wafer-to-wafer 3-D integration, many known-good dies (KGDs) can be simultaneously and precisely self-assembled by water surface tension onto a carrier wafer, which is called a reconfigured wafer. In addition, the KGDs on the reconfigured wafer can be transferred and bonded to another target wafer at the wafer level. The alignment accuracy is within 1 \mum when 3\,\times\,3-, 5\,\times\,5-, 4\,\times\,9,- or 10\,\times\,10-mm^2 chips are employed. To 3-D stack many KGDs in a batch process, we developed and employed a self-assembly multichip bonder. KGDs with 20-\mum-pitch Cu–SnAg microbumps covered with a nonconductive film as a preapplied underfill material on their top surface were self-assembled right-side up, and then transferred to the corresponding target interposer wafer upside down. The resulting daisy chain with 500 Cu–SnAg microbumps exhibited ohmic contacts, and the resistance of \sim40~m\Omega/bump was sufficiently low for 3-D large-scale integration application. [ABSTRACT FROM AUTHOR]

Self-assembly of multichips with metal microbump electrodes is demonstrated by using water surface tension to increase the stacking throughput/yield and chip alignment accuracy of conventional chip-to-wafer 3-D integration. Three-dimensional microbump interconnects are formed by self-assembly with thermal compression at 200 ^\circ\C. Chips with In–Au microbumps with pitches of 10 and 20 \mu\m are tightly bonded to Si wafers after the flip-chip self-assembly process, resulting in high alignment accuracies of 0.8 and 0.2 \mu\m in the x- and y-directions, respectively. Selective hydrophilization by 172-nm excimer lamp irradiation gives a high wettability contrast between hydrophilic chip bonding areas and hydrophobic surrounding areas on the wafers. This assists high-precision multichip self-assembly. A 2500-In–Au-microbump daisy chain is formed with a yield of 100% by flip-chip self-assembly, and it exhibits ohmic contact. The resistance is sufficiently low for 3-D large-scale integration application, being comparable to that obtained by conventional mechanical chip alignment. [ABSTRACT FROM PUBLISHER]

An advanced die-to-wafer 3-D integration using a surface-tension–driven multichip self-assembly technology was proposed to 3-D stack a large number of known good dies (KGDs) in batch processing. The parallel self-assembly with a unique multichip pick-up tool was newly applied to die-to-wafer 3-D integration to overcome throughput and yield problems in conventional 3-D integration approaches. In addition, novel batch transfer of chips self-assembled on a carrier wafer to the corresponding target wafer was demonstrated. By using the multichip self-assembly, many KGDs can be precisely aligned and temporarily placed on a carrier wafer all at once, and then, the self-assembled KGDs can be simultaneously transferred to another target wafer in a face-to-face bonding manner at the wafer level. Average alignment accuracy was found to be approximately 400 nm when a hundred 3-mm-square chips were self-assembled on carrier wafers with small droplets of an aqueous solution. The alignment accuracy was experimentally proven to be fairly dependent on liquid surface tension as a self-assembly parameter. The liquid wettability contrast between the chip assembly areas and the surrounding areas formed on carrier wafers was another key parameter for alignment accuracy. The former and the latter areas were rendered high hydrophilic and hydrophobic. These areas, respectively, showed water contact angles less than 5^\circ and 115^\circ. Therefore, various sizes of chips (3\,\times\,3 mm, 5\,\times\,5 mm, 4\,\times\,9 mm, and 10\,\times\,10 mm) were self-assembled on a carrier wafer with high alignment accuracy, and further, the self-assembled chips were successfully transferred to the other faced target wafer in a batch. [ABSTRACT FROM PUBLISHER]