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This article presents a throughput/area accelerator for elliptic-curve point multiplication over GF(2571). To optimize the throughput, we proposed an efficient hardware accelerator architecture for a fully recursive Karatsuba multiplier to perform polynomial multiplications in one clock cycle. To minimize the hardware resources, we have utilized the proposed Karatsuba multiplier for modular square implementations. Moreover, the Itoh-Tsujii algorithm for modular inverse computation is operated using multiplier resources. These strategies permit us to reduce the hardware resources of our implemented accelerator over a large field size of 571 bits. A controller is implemented to provide control functionalities. Our throughput/area accelerator is implemented in Verilog HDL using the Vivado IDE tool. The results after the place-and-route are given on Xilinx Virtex-6 and Virtex-7 devices. The utilized slices on Virtex-6 and Virtex-7 devices are 6107 and 5683, respectively. For the same FPGA devices, our accelerator can operate at a maximum of 319 MHz and 361 MHz. The latency values for Virtex-6 and Virtex-7 devices are 28.73 μs and 25.38 μs. The comparison to the state-of-the-art shows that the proposed architecture outperforms in throughput/area values. Thus, our accelerator architecture is suitable for cryptographic applications that demand a throughput and area simultaneously.

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

This work presents a scalable digit-parallel finite field polynomial multiplier architecture with a digit size of 32 bits for NIST-standardized binary elliptic fields. First, a dedicated digit-parallel architecture is proposed for each binary field recommended by NIST, i.e., 163, 233, 283, 409 and 571. Then, a scalable architecture having support for all variants of binary fields of elliptic curves is proposed. For performance investigation, we have compared dedicated multiplier architectures with scalable design. After this, the dedicated and scalable architectures are compared with the most relevant state-of-the-art multipliers. All multiplier architectures are implemented in Verilog HDL using the Vivado IDE tool. The implementation results are reported on a 28 nm Virtex-7 FPGA technology. The dedicated multipliers utilize slices of 1182 (for m=163), 1451 (for m=233), 1589 (for m=283), 2093 (for m=409) and 3451 (for m=571). Moreover, our dedicated designs can operate at a maximum frequency of 500, 476, 465, 451 and 443 MHz. Similarly, for all supported binary fields, our scalable architecture (i) utilizes 3753 slices, (ii) achieves 305 MHz clock frequency, (iii) takes 0.013 μs for one finite field multiplication and (iv) consumes 3.905 W power. The proposed scalable digit-parallel architecture is more area-efficient than most recent state-of-the-art multipliers. Consequently, the reported results and comparison to the state of the art reveal that the proposed architectures are well suited for cryptographic applications.