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The reliability issues in silicon carbide (SiC)-based devices with gate dielectric formed through heat oxidation are significant factors limiting their application in power devices. Aluminum oxide (Al2O3) was chosen as a high-k material to form the gate oxide layer on top of a SiC substrate. Atomic layer deposition (ALD) was used to fabricate an Al2O3/4H-SiC heterostructure, and the quality of the ALD Al2O3 layer was examined by XPS and electrical experiments. The XPS analysis suggests that the created heterojunction is a type-I heterojunction with ΔEC = 1.89 eV and ΔEV = 1.83 eV. Metal-insulated semiconductor structures with upper and lower Al electrodes were prepared for investigating leakage current and breakdown voltage characteristics. The leakage current density and breakdown electric field of an MOS capacitor structure with an Al2O3/4H-SiC heterojunction are ∼10−10 A/cm2 and 9.3 MV/cm, respectively. The interfacial defect density (Dit) near the conduction band of the MOS capacitive structure with the SiC substrate is 1.44 × 1012 eV−1 cm−2, while the interface charge (Neff) of the oxide layer of this sample can also be controlled at a level of 1011 cm−2. The Al2O3/SiC structure fabricated in this work exhibits superior electrical performance compared to the heterostructure based on the Si substrate and other relevant heterostructures documented in previous studies. [ABSTRACT FROM AUTHOR]

In this study, we investigated the crystallographic and electrical properties of ZrO2 thin films prepared by an ozone-based atomic layer deposition process. Cyclopentadienyl tris(dimethylamino) zirconium [CpZr(NMe2)3] was used as the Zr precursor, and O3 was used as the reactant. ZrO2 films were produced using O3 in various concentrations from 100 to 400 g/m3. These thin films were used to fabricate metal–oxide–semiconductor capacitors, whose electrical properties were evaluated and correlated with crystallographic analysis. As the O3 concentration increased, the tetragonal phase of the ZrO2 film stabilized and the dielectric constant improved. However, the leakage current density characteristics concurrently deteriorated due to the high concentration of O3, increasing the number of grain boundaries in the ZrO2 film by increasing crystallinity. Thus, the concentration of O3 can control the number of OH groups of the ZrO2 film, affecting the device characteristics. [ABSTRACT FROM AUTHOR]

Ferroelectric negative capacitance transistors (Fe‐NCFETs) have emerged as a promising technology for low‐power electronics and have the potential to continue Moore's law. However, the existing 2D ferroelectric materials are predominantly sulfides or halides, which are susceptible to oxidation or hydrolysis, thereby hindering their commercial production due to concerns related to performance and stability. To address these obstacles, the authors have optimized the Fe‐NCFETs composed of 2D ferroelectric CuInP2S6 and semiconductor WS2 using high‐k Al2O3 passivation and dual‐gate modulation strategy. With atomic layer deposition (ALD) of Al2O3, all‐2D Fe‐NCFETs, operated at a low driven voltage of 0.3 V, achieve much improvement in stability and performance with a high ON/OFF ratio of 109 and minimum subthreshold swing (SS) of 14 mV dec−1, which is attributed to the negative capacitance effect of CuInP2S6 and passivation effect of ALD‐Al2O3. The dual‐gate modulation approach is also implemented to maintain the device stability and enable the improved ON/OFF ratio from 105 to 108, minimum SS of 10 mV dec−1, and an average SS of ≈60 mV dec−1 covering more than five orders of magnitude of current. This work provides a facile and effective strategy for designing all‐2D Fe‐NCFETs with ultra‐steep SS and high stability, showing exciting potential for future low‐power electronic applications. [ABSTRACT FROM AUTHOR]

Self-aligned metal-oxide-semiconductor (MOS) capacitors are studied with several low-temperature, wet chemical silicon dioxide (SiO2) interlayers to understand their impact on electrical performance. Self-aligned MOS capacitors are fabricated with a bottom-up patterning technique that uses a poly(methyl methacrylate) brush and dopant-selective KOH etch combined with area-selective atomic layer deposition of hafnium dioxide (HfO2) and Pt. The wet chemical pretreatments used to form the SiO2 interlayer include hydrofluoric acid (HF) etch, 80 °C H2O, and SC-2. Capacitance-voltage measurements of these area-selective capacitors exhibit a HfO2 dielectric constant of ∼19, irrespective of pretreatment. After a forming gas anneal, the average interface state density decreased between 1.8 and 7.5 times. The minimum observed Dit is 1 × 1011 eV−1 cm−2 for the HF-last treatment. X-ray photoelectron spectroscopy shows an increase in stoichiometric SiO2 in the interfacial layer after the anneal. Additional carbon is also observed; however, comparison with capacitors fabricated in a nonselective process reveals minimal impact on performance. [ABSTRACT FROM AUTHOR]

Metal-oxide-semiconductor (MOS) capacitors with Al2O3 as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al2O3 is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO2 interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al2O3/SiO2 stacks show lower negative shifts of the flat band voltage VFB (in the range of about −3 V) compared with the conventional single SiO2 layer (in the range of −9 V). This lower negative shift is due to the combined effect of the Al2O3 higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO2. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al2O3 layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al2O3 sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al2O3 obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps. [ABSTRACT FROM AUTHOR]

Super-high dielectric constant (k) AlOx/TiOy nanolaminates (ATO NLs) are deposited by an atomic layer deposition technique for application in next-generation electronics. Individual multilayers with uniform thicknesses are formed for the ATO NLs. With an increase in AlOx content in each ATO sublayer, the shape of the Raman spectrum has a tendency to approach that of a single AlOx layer. The effects of ATO NL deposition conditions on the electrical properties of the metal/ATO NL/metal capacitors were investigated. A lower deposition temperature, thicker ATO NL, and lower TiOy content in each ATO sublayer can lead to a lower leakage current and smaller loss tangent at 1 kHz for the capacitors. A higher deposition temperature, larger number of ATO interfaces, and higher TiOy content in each ATO sublayer are important for obtaining higher k values for the ATO NLs. With an increase in resistance in the capacitors, the ATO NLs vary from semiconductors to insulators and their k values have a tendency to decrease. For most of the capacitors, the capacitances reduce with increments in absolute measurement voltage. There are semi-circular shapes for the impedance spectra of the capacitors. By fitting them with the equivalent circuit, it is observed that with the increase in absolute voltage, both parallel resistance and capacitance decrease. The variation in the capacitance is explained well by a novel double-Schottky electrode contact model. The formation of super-high k values for the semiconducting ATO NLs is possibly attributed to the accumulation of charges. [ABSTRACT FROM AUTHOR]

Gallium oxide (β-Ga2O3) is becoming a popular material for high power electronic devices due to its wide bandgap and ease of processing. In this work, β-Ga2O3 substrates received various annealing treatments before atomic layer deposition of HfO2 and subsequent fabrication of metal–oxide–semiconductor (MOS) capacitors. Annealing of β-Ga2O3 with forming gas or nitrogen produced degraded capacitance–voltage (C–V) behavior compared to a β-Ga2O3 control sample with no annealing. A sample annealed with pure oxygen had improved C–V characteristics relative to the control sample, with a higher maximum capacitance and smaller flat-band voltage shift, indicating that oxygen annealing improved the C–V behavior. X-ray photoelectron spectroscopy also suggested a reduction in the oxygen vacancy concentration after O2 annealing at 450 °C, which supports the improved C–V characteristics and indicates that O2 annealing of β-Ga2O3 may lead to better MOS device performance. [ABSTRACT FROM AUTHOR]

Metal oxide semiconductor capacitors were fabricated using p - type oxygen-terminated (001) diamond and Al2O3 deposited by atomic layer deposition at two different temperatures 250 °C and 380 °C. Current voltage I(V), capacitance voltage C(V), and capacitance frequency C(f) measurements were performed and analyzed for frequencies ranging from 1 Hz to 1 MHz and temperatures from 160 K to 360 K. A complete model for the Metal-Oxide-Semiconductor Capacitors electrostatics, leakage current mechanisms through the oxide into the semiconductor and small a.c. signal equivalent circuit of the device is proposed and discussed. Interface states densities are then evaluated in the range of 10 12 eV − 1 cm − 2 . The strong Fermi level pinning is demonstrated to be induced by the combined effects of the leakage current through the oxide and the presence of diamond/oxide interface states. [ABSTRACT FROM AUTHOR]

Embedded three-dimensional (3-D) metal-insulator-metal (MIM) decoupling capacitors with high-κ dielectric films of high capacitance and long-life time are increasingly needed on integrated chips. Towards achieving better electrical performance, there is a need for investigation into the influence of the variation in atomic layer deposition (ALD) parameters used for thin high-κ dielectric films (10 nm) made of Al2O3-doped ZrO2. This variation should always be related to the structural uniformity, the electrical characteristics, and the electrical reliability of the capacitors. This paper discusses the influence of different Zr precursor pulse times per ALD cycle and deposition temperatures (283 °C/556 K and 303 °C/576 K) with respect to the capacitance density (C-V), voltage linearity and leakage current density (I-V). Moreover, the dielectric breakdown and TDDB characteristics are evaluated under a wide range of temperatures (223–423 K). [ABSTRACT FROM AUTHOR]

The carbon clusters and oxygen vacancies-induced interface traps and near-interface-oxide traps (NIOTs) at the dielectric oxide/SiC heterojunction severely degenerate the electrical properties and reliability of SiC devices. In this work, plasma-enhanced atomic layer deposition (PEALD) is performed to deposit Al2O3 dielectrics on 4H-SiC substrate to minimize the carbon cluster formation and in situ NH3-plasma pre-treatment is utilized to further improve the interfacial properties. Significantly enhanced electrical properties of the 4H-SiC/Al2O3 heterojunction is obtained with a reduced C–V hysteresis (from 0.411 V to 0.103 V) and leakage current density (from 10–3 to 10–6 A/cm2), lowered interface states (from (5.97–8.63) × 1011 to (4.10–7.56) × 1011 eV−1 cm−2) and NIOTs (from (6.15–6.82) × 1012 to (4.26–4.53) × 1011 eV−1 cm−2) and improved dielectric breakdown electric field (from 7.68 to 8.75 MV/cm). This demonstrates that in situ NH3-plasma pre-treatment associated with high-κ dielectrics is a promising technique for future high-power device applications. [ABSTRACT FROM AUTHOR]

As β-Ga2O3 becomes a popular semiconductor material for high-power electronic devices, researchers are presenting innovative device structures and fabrication processes to achieve high performance and enhanced reliability of these devices. In many cases, these fabrication processes involve the formation of mesas, trenches, and other structures by plasma etching of β-Ga2O3 with Cl2 and/or BCl3. This paper looks at the effects of photoresist patterning and BCl3 plasma etching prior to atomic layer deposition of HfO2 dielectric to form metal–oxide–semiconductor capacitors. The β-Ga2O3/HfO2 interface is critical for controlling device characteristics such as flat-band voltage and maximum capacitance under accumulation and can be greatly affected by roughness and chemical residues. Capacitance-voltage data and atomic force microscope (AFM) scans indicate that photoresist and BCl3 residues are not adequately removed with acetone/IPA/DIW cleaning but are removed using piranha (H2O2/H2SO4) cleaning before deposition of the dielectric. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) of Y 2 O 3 thin films was performed on Si substrate by pulsing an unconventional heteroleptic yttrium precursor Y(MeCp) 2 (Me 2 Pz) and H 2 O alternatively. The thin film grew 0.26–0.28 Å per cycle at relatively low temperature of 195–225 °C in a self-limiting manner with negligible nucleation delay, and is close to stoichiometric (O/Y = 1.48, C, 2.56 at%; N, 1.81 at%) in as-deposited form. Integration of the post-annealed ALD Y 2 O 3 film in a metal oxide semiconductor (MOS) capacitor structure exhibits representative electrical properties including a high dielectric constant k of 11.4, high electrical breakdown field of 6.1 MV cm−1 and low leakage current density of 9.1 × 10−8 A cm−2 at − 2 MV cm−1. • A reliable ALD process of Y 2 O 3 in thermal mode could be achieved using a heteroleptic yttrium precursor. • The crystalline Y 2 O 3 thin films grew 0.26-0.28 Å/cycle in temperature region of 195-225°C. • The ALD Y 2 O 3 film exhibits k value of 11.4, electrical breakdown fields of 6.1 MV cm-1 and leakage current density of 9.1×10-8 A cm-2 at -2 MV cm-1. [ABSTRACT FROM AUTHOR]

This study presents the construction and dielectric properties investigation of atomic-layer-deposition Al2O3/TiO2/HfO2 dielectric-film-based metal–insulator–metal (MIM) capacitors. The influence of the dielectric layer material and thickness on the performance of MIM capacitors are also systematically investigated. The morphology and surface roughness of dielectric films for different materials and thicknesses are analyzed via atomic force microscopy (AFM). Among them, the 25 nm Al2O3-based dielectric capacitor exhibits superior comprehensive electrical performance, including a high capacitance density of 7.89 fF·µm−2, desirable breakdown voltage and leakage current of about 12 V and 1.4 × 10−10 A·cm−2, and quadratic voltage coefficient of 303.6 ppm·V−2. Simultaneously, the fabricated capacitor indicates desirable stability in terms of frequency and bias voltage (at 1 MHz), with the corresponding slight capacitance density variation of about 0.52 fF·µm−2 and 0.25 fF·µm−2. Furthermore, the mechanism of the variation in capacitance density and leakage current might be attributed to the Poole–Frenkel emission and charge-trapping effect of the high-k materials. All these results indicate potential applications in integrated passive devices. [ABSTRACT FROM AUTHOR]

The metal-insulator-metal (MIM) is being used as the potential device in the research interest of modern materials for nanoelectronics applications in semiconductor industries. In this context, the chemical, structural and electrical properties of plasma-enhance atomic layer deposition (PEALD) deposited ZrO2/La2O3/ZrO2 (ZLZ) nanolaminates at low substrate temperature have been studied and compared with, 300 °C, 400 °C, and 500 °C annealed ZLZ nanolaminates. The Tetrakis-(ethylmethylamido) zirconium-IV and Tris-(cyclopentadienyl) lanthanum-III were used as precursors for the zirconium and lanthanum whereas, O2 plasma was utilized as the oxidizing agent in each PEALD cycle. Root-mean-square (RMS) surface roughness was determined using atomic force microscopy. The x-ray photoelectron spectroscopy and x-ray diffraction measurements were used to investigate the effect of post-deposition annealing on the phase change of ZLZ nanolaminates. The film annealed at 400 °C in an atmospheric environment gives the stable phase formation of the pyrochlore phase of La2Zr2O7. This stable phase formation of 400 °C annealed Al/ZLZ/Al MIM capacitor provides the lowest leakage current density of 6.20 × 10− 7 A/cm2 at 1 V compared to the as-deposited films. The barrier height of 0.42 eV for this MIM capacitor was extracted from the Fowler-Northeim (FN) tunneling model. The obtained results of PEALD nanolaminated high-k MIM capacitors having a controlled phase indicate the potential use for nanoelectronics applications. [ABSTRACT FROM AUTHOR]

We compare the electrical properties of HfO2/Al2O3 nano-laminates with those of the ternary HfxAlyO compound in metal oxide semiconductor (MOS) capacitors. The dielectrics were deposited by atomic layer deposition on InGaAs. Water, ozone, and oxygen plasma were tested as oxygen precursors, and best results were obtained using water. The total dielectric thickness was kept constant in our experiments. It was found that the effective dielectric constant increased and the leakage current decreased with the number of periods. Best results were obtained for the ternary compound. The effect of the sublayer thicknesses on the electrical properties of the interface was carefully investigated, as well as the role of post-metallization annealing. Possible explanations for the observed trends are provided. We conclude that the ternary HfxAlyO compound is more favorable than the nano-laminates approach for InGaAs based MOS transistor applications. [ABSTRACT FROM AUTHOR]

Al2O3 films were grown in situ by metalorganic chemical vapor deposition at 900 °C on GaN of both Ga- and N-face polarities. High-resolution transmission electron microscopy revealed that the Al2O3 films were crystalline and primarily γ-phase. The Al2O3/Ga-GaN and Al2O3/N-GaN interfaces were both atomically sharp, and the latter further exhibited a biatomic step feature. The corresponding current-voltage (J-V) characteristics were measured on a metal-Al2O3-semiconductor capacitor (MOSCAP) structure. The leakage current was very high when the Al2O3 thickness was comparable with the size of the crystalline defects, but was suppressed to the order of 1 × 10–8 A/cm2 with larger Al2O3 thicknesses. The interface states densities (Dit) were measured on the same MOSCAPs by using combined ultraviolet (UV)-assisted capacitance-voltage (C-V), constant capacitance deep level transient spectroscopy (CC-DLTS), and constant capacitance deep level optical spectroscopy (CC-DLOS) techniques. The average Dit measured by CC-DLTS and CC-DLOS were 6.6 × 1012 and 8.8 × 1012 cm–2 eV–1 for Al2O3/Ga-GaN and 8.6 × 1012 and 8.6 × 1012cm–2 eV–1 for Al2O3/N-GaN, respectively. The possible origins of the positive (negative) polarization compensation charges in Al2O3/Ga-GaN (Al2O3/N-GaN), including the filling of interface states and the existence of structure defects and impurities in the Al2O3 layer, were discussed in accordance with the experimental results and relevant studies in the literature. [ABSTRACT FROM AUTHOR]

High quality dielectric‐semiconductor interfaces are critical for reliable high‐performance transistors. This paper reports the in situ metal–organic chemical vapor deposition of Al2O3 on β‐Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD). The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β‐Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet‐assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1. This in situ Al2O3 dielectric on β‐Ga2O3 with improved dielectric properties can enable Ga2O3‐based high‐performance devices. [ABSTRACT FROM AUTHOR]

A metal–oxide–semiconductor (MOS) gate stack that is self-aligned with the underlying silicon doping profile is demonstrated. We combine a new hybrid bottom-up patterning technique with atomic layer deposition (ALD) to selectively deposit a platinum-hafnium dioxide-silicon MOS gate stack. A poly(methyl methacrylate) (PMMA) brush is blanket grown from a Si(100) surface and selectively removed from the lightly doped (∼1018 cm−3) regions using a doping-selective KOH etch. The PMMA brush that remains on the heavily doped (∼1020 cm−3) regions effectively blocks the ALD of both HfO2 and platinum. MOS capacitors exhibit promising capacitance-voltage characteristics with a HfO2 dielectric constant of ∼25 and an average interface state density of 2.1 × 1011 eV−1 cm−2 following forming gas anneal. [ABSTRACT FROM AUTHOR]

In this work, we present the terrace etching technique to obtain excessive thickness series of atomic layer deposition (ALD) grown Al2O3 and HfO2 on GaN-cap/AlGaN/GaN heterostructures allowing for the detailed study of oxide charge distribution and its impact of the metal-insulator-semiconductor high electron mobility transistor (MISHEMT) threshold voltage. By modeling the experimental plot of threshold voltage versus oxide thickness on the basis of experimentally determined two-dimensional electron gas charge density in AlGaN/GaN MISHEMTs, we separated the interface and bulk charge components and determined the oxide-metal barrier height for the investigated gate dielectrics. In both Al2O3 and HfO2 gate dielectrics, the oxide charges are mainly located at the oxide/GaN interface. Determining the interface trap charges from comparison of the pulsed capacitance-voltage (CV) technique with very fast voltage sweep to the modulation type CV method with slow DC voltage ramp, we extracted positive fixed charges of NOx = 2.7 × 1012 cm–2 for Al2O3 and NOx = 7.8 × 1012 cm–2 for HfO2. We found a strong Vth shift of opposite direction for both high-k materials, corresponding to negatively charged up trap states at the HfO2/GaN interface and positively charged up trap states at the Al2O3/GaN interface. The evaluation of the metal-oxide barrier height in dependence of the metal work function followed the trend of the Schottky model, whereas HfO2 showed less Fermi level pinning compared to Al2O3 indicating the presence of an increased number of interface states in Al2O3 on GaN. [ABSTRACT FROM AUTHOR]

We investigated the suitability of aluminum nitride (AlN) for surface passivation and protection of gallium arsenide (GaAs), using a low-temperature passivation method. By varying the plasma power (100, 200 W) during etching, we found that 200 W produced better passivation. Using X-ray photoelectron spectroscopy, we quantitatively demonstrate that etching the GaAs at 200 W almost removed the GaAs oxide layer. To further study the surface passivation of GaAs, we deposited an AlN film by plasma-enhanced atomic layer deposition using trimethylaluminum and ammonia precursors at 250 °C. AlN passivation did not effectively smooth the GaAs surface, but did increase its photoluminescence intensity. This study shows that AlN coating by plasma-enhanced atomic layer deposition is a promising low-temperature method for GaAs surface passivation. [ABSTRACT FROM AUTHOR]

This study investigates methods to modulate the effective work function (EWF) and control the multiple threshold voltages (V THs) of metal-oxide-semiconductor (MOS) devices by applying metal electrodes with different work function materials (WFMs), including a single layer of n-type (TaAlC) and p-type (TaAlN) as well as their stacked structures, through atomic layer deposition (ALD). Dual-Work-Function-Metal (DWFM) gate is a crucial aspect of confirming the feasibility of metal gate stacks in MOS devices for a complementary metal-oxide-semiconductor (CMOS) integration scheme. The gate stack structure of p-Si/IL (Inter layer)/HfO 2 /DWFM (p/n-type compatible metal stack)/W exhibits good adhesion and even chemical composition distribution, as evidenced by transmission electron microscope (TEM) and energy dispersive spectrometer (EDS) analysis. By fabricating MOS capacitors using this WFM structure and extracting EWF from the measured capacitance-voltage (C–V) characteristics, EWF values of 4.62 eV and 4.99 eV were identified both before and after annealing using forming gas, indicating pWFM-like properties. These properties are attributed to the strengthened Al–O bonds and reduced C O peaks seen in x-ray photoelectron spectroscopy (XPS) analysis. The use of different Ta precursor from Tris(diethylamido)(tert-butylimido)tantalum(V) (TBTDET) as well as TaCl 5 resulted in the increase of the EWF following the unique p -WFM like feature. As candidates for WFM electrode in metal-oxide-semiconductor field effect transistor (MOSFET) with the DWFMs (n/p stacks) were evaluated, resulting in a V TH of 0.84 V that places in the middle of the V TH shift range from 0.6 V (nWFM) to 1.16 V (pWFM), approximately. The DWFMs allow for modulation of the EWF, which in turn reduces ambiguity in addressing replacement metal gate (RMG) challenges and opens up new avenues for achieving multi-V TH solutions in CMOS integration schemes. [Display omitted] [ABSTRACT FROM AUTHOR]

The characteristics of HfO 2 thin films obtained with and without ultraviolet (UV) exposure post-treatment are discussed. First, 30-nm-thick HfO 2 thin films are deposited on silicon wafer substrates using atomic layer deposition followed by a combination of UV exposure and low-temperature thermal post-treatment. Compared with the samples without UV treatment, the HfO 2 samples with post-treatment showed a smaller suboxide bond proportion of 2.59%, along with increased crystallinity. The use of a UV-treated gate dielectric HfO 2 film in a MOS capacitor device results in lower interface trap and fixed charge densities. Furthermore, the dielectric constant of the HfO 2 thin film with the treatment is 22.03, which is higher than that of the film without the treatment, that is, 14.98. In addition, the device capacitance was improved by 56% with the treatment. These results demonstrate the significant potential of the proposed post-treatment process in improving the quality of HfO 2 thin films for semiconductor devices. [ABSTRACT FROM AUTHOR]

Electrical properties of Al2O3/hydrogenated-diamond (H-diamond) metal-oxide-semiconductor (MOS) capacitors are investigated and discussed in this study. Al2O3 gate dielectrics are deposited at 120, 200, and 300 °C by an atomic layer deposition technique. For the H-diamond MOS capacitors with Al2O3 deposited at 120, 200, and 300 °C, leakage current densities at an electric field of 3.0 MV cm−1 are 8.4 × 10−4, 7.1 × 10−6, and 7.5 × 10−5 A cm−2, respectively. A small decrease in the maximum capacitance of the Al2O3 (120 °C)/H-diamond MOS capacitor is observed when the measurement frequency is increased from 1 kHz to 100 kHz. However, the maximum capacitances of the Al2O3 (200 °C)/H-diamond and Al2O3 (300 °C)/H-diamond MOS capacitors are stable. Experimental flatband voltage in the capacitance–voltage curve of the Al2O3 (120 °C)/H-diamond MOS capacitor shifts to the left with respect to theoretical flatband voltage. However, they shift to the right for the Al2O3 (200 °C)/H-diamond and Al2O3 (300 °C)/H-diamond MOS capacitors. Therefore, when the deposition temperature of Al2O3 is increased from 120 to 300 °C, polarity of the fixed charges in the H-diamond MOS capacitors changes from positive to negative. This phenomenon is explained by the variations of negatively charged acceptors at the Al2O3/H-diamond interface and oxygen vacancies in the Al2O3 film. [ABSTRACT FROM AUTHOR]

In this Letter, the interface state density (Dit) and bulk trap density (nbulk) in post-deposition annealed Al2O3/β-Ga2O3 (001) metal–oxide–semiconductor capacitors (MOSCAPs) are extracted using the deep UV-assisted capacitance–voltage method and an improved physical analytical model. The effects of atomic layer deposition (ALD) temperature and post-deposition annealing (PDA) conditions are also studied. Increasing the deposition temperature and PDA at 500 °C in O2 seems to be an effective way to improve the forward breakdown voltage (BV) and suppress capacitance–voltage hysteresis in Al2O3/β-Ga2O3 (001) MOSCAPs. These results are useful for future high performance Ga2O3-based metal-oxide-semiconductor field effect transistors (MOSFETs) and Fin-FETs. [ABSTRACT FROM AUTHOR]

This paper presents the interface analysis and band offset of Al2O3/AlGaN/GaN metal-oxide-semiconductor (MOS) heterostructures with diffusion-controlled interface oxidation (DCIO) treatment. After conventional surface pre-treatment with wet cleaning and nitridation plasma, 1 nm Al2O3 was prepared with atomic layer deposition, followed by in situ plasma-assisted interface oxidation for 30 minutes. The interface oxidation process is limited by oxidant diffusion through the pre-deposited Al2O3 layer, contributing to the formation of a high quality crystalline interfacial oxide layer. For MOS heterostructures with 24.1 nm Al2O3, a positive threshold voltage shift by 1.8 V was obtained by using the DCIO technique. The energy band structures and band offset at the Al2O3/AlGaN interface was investigated with x-ray photoelectron spectroscopy (XPS). XPS results show that DCIO treatment causes an increase in conduction band offset from 2.29 ± 0.37 eV to 2.92 ± 0.36 eV. There is also a decrease in Al2O3 band slope, indicating a decrease in internal electrical field strength and interface charges. The Al2O3 energy band for these two cases may also cross with each other at a certain point, defining the critical thickness of gate oxide. Generally, the decrease in interface charges by DCIO causes a positive voltage shift, while the voltage shift will change sign with Al2O3 thickness smaller than the critical value. The MOS heterostructures with and without DCIO exhibit very nice relations between threshold voltage and Al2O3 thickness, giving a critical oxide thickness of about 1 nm. DCIO results in a decrease in the slope of linear function by about 0.08 V nm−1, indicating the reduced interface charges by 3.96 × 1012 cm−2. [ABSTRACT FROM AUTHOR]

Metal oxide semiconductor capacitors that incorporate tantalum pentoxide (Ta2O5) thin films as dielectric were fabricated via the atomic layer deposition (ALD) technique and characterized through TEM, XPS, C-V, and I-V measurements. TEM analysis revealed the amorphous phase of Ta2O5 films and the existence of an ultrathin SiOx layer in the Ta2O5/p-Si interface, also evidenced by XPS spectra. XPS analysis verified the stoichiometry of the ALD-deposited Ta2O5 films. Furthermore, XPS results indicate values of 2.5 and 0.7 eV for the conduction and valence band offsets of the Ta2O5/p-Si interface, respectively. I-V measurements, for positive and negative applied bias voltages, reveal that the conduction is governed by Ohmic, trap controlled space charge limited, and Schottky mechanisms depending on the applied voltage and temperature region. Through the analysis of Schottky emission data, the conduction band offset of Ta2O5/p-Si (w?) is calculated to be 0.6 eV, while the valence band offset is 2.6 eV, in very good agreement with the XPS results. The energy band diagram of Ta2O5/p-Si is constructed. [ABSTRACT FROM AUTHOR]

The results of an investigation into the impact of in situ H2 plasma exposure on the electrical properties of the p/n-In0.3 Ga0.7 Sb-Al2O3 interface are presented. Samples were processed using a clustered inductively coupled plasma reactive ion etching and atomic layer deposition tool. Metal oxide semiconductor capacitors were fabricated subsequent to H2 plasma processing and Al2O3 deposition, and the corresponding capacitance-voltage and conductance-voltage measurements were analyzed quantitatively via the simulation of an equivalent circuit model. Interface state ( D it ) and border trap ( N bt ) densities were extracted for samples subjected to the optimal process, with a minimum Dit of 1.73 × 10 12 eV−1 cm−2 located at ∼110 meV below the conduction band edge and peak N bt approximately aligned with the valence and conduction band edges of 3 × 10 19 cm−3 and 6.5 × 10 19 cm−3, respectively. Analysis of the inversion response in terms of the extraction of the activation energy of minority carriers in inversion (p-type) and the observation of characteristics that pertain to minority carriers being supplied from an external inversion region (n-type) unequivocally demonstrate that the Fermi level is unpinned and that genuine surface inversion is observed for both doping polarities. [ABSTRACT FROM AUTHOR]

The Au/Ti/HfO2/ n -GaAs metal/insulating layer/semiconductor structures have been fabricated using standard thermal atomic layer deposition. We experimentally showed whether or not the HfO2 interfacial layer grown on the n -GaAs wafer modifies the barrier height (BH) of the device at the room temperature. Besides, we investigated the measurement based on temperature dependence of the device parameters from the current–voltage (I – V) characteristics of the diode in 60–400 K range with steps of 10 K. The X-ray photoelectron spectroscopy (XPS) have been carried out to characterize the surfaces of both n -GaAs wafer and HfO2 thin films. The series resistance value from the temperature-dependent I – V characteristics decreased with decreasing temperature, which is a desired positive result for the devices developed from the MOS capacitor. The BH value of 0.94 eV (300 K) has been obtained for the device with the HfO2 layer which is a higher value than the value of 0.77 eV (300 K) of the device without HfO2 layer. Therefore, we can say that the HfO2 thin layer at the metal/GaAs interface can also be used for the BH modification as a gate insulator for GaAs MOS capacitor and MOSFETs. When the temperature-dependent I – V characteristics at low temperatures have been considered, it has been observed that the current prefers to flow through the lowest BHs due to the BH inhomogeneities. [ABSTRACT FROM AUTHOR]

The influence of 120 MeV Ag ion irradiation on the structural and electrical properties of HfO 2 (3 nm)/SiON (1 nm)/Si (n-type), grown by atomic layer deposition, has been investigated. X-ray Reflectivity and X-ray Photoelectron Spectroscopy measurements suggested the formation of a mixed interlayer of HfSiON above a critical fluence of 1 × 1012 ions/cm2. The observed irradiation induced changes in the leakage current have been attributed to the defects and structural changes caused by ion irradiation. The influence of various quantum tunneling mechanisms on the leakage current has been investigated as a function of ion fluence. The structural changes, defects dynamics and the consequent effects on leakage current have been explained within the framework of ion induced annealing, creation of defects and intermixing effects. • Electronic excitation-induced intermixing resulted in HfSiON interlayer formation. • Ion-induced annealing is found at low fluences until 1 × 1012 ions/cm2. • After a critical fluence, leakage current increased due to high electronic excitation. • Poole-Frenkel tunneling clearly indicates the increase in the density of defects. [ABSTRACT FROM AUTHOR]

Highlights • A new route to realize rutile-TiO 2 films was proposed without noble-metal-based electrode. • Sn doping in TiO 2 thin films was effective in improving the rutile phase of TiO 2 films. • A rutile phase of TiO 2 was enhanced by the insertion of an ultra-thin SnO 2 interlayer. • The Sn-doped TiO 2 thin film on a SnO 2 interlayer exhibited a high-k value of about 80. Abstract Rutile-TiO 2 thin films have potential for use in high-k applications, such as dynamic random-access memory capacitors; however, they are difficult to realize without using noble-metal-based oxide substrates. Therefore, we proposed a new approach for the preparation of rutile TiO 2 by a small amount of Sn doping and the insertion of ultra-thin SnO 2 to achieve enhanced dielectric performance without using noble-metal-based electrodes. It was confirmed that the crystallinity of rutile TiO 2 was remarkably enhanced in Sn-doped TiO 2 formed on an ultra-thin SnO 2 interlayer. Moreover, 10 nm-thick Sn-doped TiO 2 thin film on a 1-nm SnO 2 interlayer exhibited a high dielectric constant of about 80. [ABSTRACT FROM AUTHOR]

The interfacial properties of AlN/GaN heterostructures with different dielectric layers such as Al2O3, HfO2, and HfO2/Al2O3 prepared by atomic layer deposition were investigated. Interface state density versus energy level plots obtained from the Terman method revealed the peculiar peaks at ∼0.25 eV for the samples with Al2O3 and HfO2/Al2O3 and at ∼0.52 eV for the sample with HfO2, associated with nitrogen vacancy-related defects. According to the parallel conductance method, both the interface and border traps were observed for the sample with Al2O3. However, the border traps were not observed with including an HfO2 layer. The lowest interface trap density and the reverse leakage current were obtained for the sample with an HfO2/Al2O3 bilayer. Analysis of x-ray photoelectron spectroscopy spectra obtained from the HfO2 layers showed the formation of Hf–Al–O bonding for the sample with HfO2 while such formation was not observed for the sample with HfO2/Al2O3. These results indicate the superior interfacial quality of AlN/GaN heterostructures with an HfO2/Al2O3 bilayer. [ABSTRACT FROM AUTHOR]

Flexible metal-oxide-semiconductor capacitors in a vertical structure using the single-crystalline Si nanomembrane (NM) with a HfO2/Al2O3 bilayer gate stack prepared by atomic layer deposition have been fabricated on plastic substrates by flip-transfer printing of Si NM/Ti/Au based trilayer heterostructures (1.3 cm × 0.9 cm × 360 nm). The electrical properties of the bilayer structure exhibit an excellent improved capacitance-voltage (C-V) frequency dispersion feature associated with an inhibited weak inversion hump and significantly larger accumulation capacitance, thus indicating the effectiveness of the passivation utilizing bilayer high-k dielectrics on a Si NM channel compared with monolayer HfO2. A comprehensive electromechanical characterization has been conducted for HfO2/Al2O3 stacked structures to investigate the effect of bending strain on C-V characteristics, leakage current density, and the associated evolution of interface charges. The presented research will be beneficial to realizing high performance thin-film transistors with lower operating voltage and higher driving current required in emerging flexible and stretchable electronics via optimized design of a nanolaminate gate stack and understanding the impact of mechanical strains on the electrical behavior of such MOS devices. [ABSTRACT FROM AUTHOR]

To provide radiation hard device is very critical and when a new technology come into existence it becomes more challenging. In this research paper we have explored the radiation response of hafnium dioxide (HfO2)/silicon (Si) structure based metal oxide semiconductor (MOS) capacitor on p-type substrate, subjected to 2.7 MeV proton irradiation at various fluencies (3.6 × 1012 protons/cm2, 7.2 × 1012 protons/cm2, 1.08 × 1013 protons/cm2, 1.8 × 1013 protons/cm2, 2.16 × 1013 protons/cm2 and 3.6 × 1013 protons/cm2). Through electrical characteristics, radiation hardness of atomic layer deposited HfO2 based MOS capacitor has been investigated. To directly measure interface charge and to evaluate its change with the ionizing doses, capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are taken. To provide an evidence for the change in the device parameters pre and post-irradiation curves are plotted to compare the degradation of the device. Shift in C-V and G-V characteristics were observed in irradiated devices that also indicate a change in flat band voltage, midgap voltage and conductance of devices. Generation of new traps after proton irradiation was also confirmed by these measurements. [ABSTRACT FROM AUTHOR]

Highlights • In-situ NH 3 plasma passivation for Ga-face n-GaN MOS capacitor was done by varying plasma power and exposure time. • Improvement in frequency dispersion, ΔV FB , J g , C ox , and D it. • Residual carbon and sub GaO x are efficiently suppressed and defects are passivated. Abstract The effects of in-situ NH 3 plasma passivation on the interface between atomic layer deposited HfO 2 and Ga-face n-GaN substrate in metal-oxidesemiconductor (MOS) devices were investigated by varying plasma power and exposure time and compared with GaN MOS device without plasma passivation. ALD HfO 2 -GaN device with in-situ NH 3 plasma treatment shows improved electrical characteristics including negligible frequency dispersion at the near flat-band voltage region, lower hysteresis (∼10 mV), suppressed oxide capacitance dispersion in the accumulation (2.2%), lower leakage current density (5.21 × 10−2 A/cm2 at 1 V), and low interface state density (D it) of ∼6.77 × 1011 eV−1 cm−2 at E c -E t = 0.3 eV using an optimized plasma passivation exposure time of 10 min and power of 50 W. These results are attributed that NH 3 plasma treatment could eliminate carbon species and detrimental sub-GaO x as well as passivate the surface and bulk defects on GaN caused by Ga-N dissociation. [ABSTRACT FROM AUTHOR]

To provide radiation hard device is very critical and when a new technology come into existence it becomes more challenging. In this research paper we have explored the radiation response of hafnium dioxide (HfO2)/silicon (Si) structure based metal oxide semiconductor (MOS) capacitor on p-type substrate, subjected to 2.7 MeV proton irradiation at various fluencies (3.6 × 1012 protons/cm2, 7.2 × 1012 protons/cm2, 1.08 × 1013 protons/cm2, 1.8 × 1013 protons/cm2, 2.16 × 1013 protons/cm2 and 3.6 × 1013 protons/cm2). Through electrical characteristics, radiation hardness of atomic layer deposited HfO2 based MOS capacitor has been investigated. To directly measure interface charge and to evaluate its change with the ionizing doses, capacitance-voltage (C-V) and conductance-voltage (G-V) measurements are taken. To provide an evidence for the change in the device parameters pre and post-irradiation curves are plotted to compare the degradation of the device. Shift in C-V and G-V characteristics were observed in irradiated devices that also indicate a change in flat band voltage, midgap voltage and conductance of devices. Generation of new traps after proton irradiation was also confirmed by these measurements. [ABSTRACT FROM AUTHOR]

Electrical characteristics of SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO 2 (ALD-SiO 2 ) gate dielectrics were investigated. Post-metallization annealing (PMA) with W gate electrodes at 950 °C showed a large recovery in the flatband voltage toward the ideal value and the hysteresis was reduced to 36 mV. Interface state density ( D it ) of 3 × 10 11  cm −2 /eV was obtained after the PMA for 5 × 10 3  s. The concentration of the residual carbon atoms in the SiO 2 gate dielectrics has been reduced after annealing, suggesting one of the possible origins of the improvements. [ABSTRACT FROM AUTHOR]

The effect of La-silicate interface layer (IL) on the electrical characteristics of 4H-SiC metal-oxide-semiconductor (MOS) capacitors with atomic-layer-deposited SiO 2 (ALD-SiO 2 ) gate dielectrics was investigated. In addition to a slight reduction in the interface state density ( D it ), the surface potential fluctuation was greatly reduced due to the reduction in the fixed charges ( Q fix ) with La-silicate IL. Moreover, two orders of magnitude reduction in the oxide trap density in the ALD-SiO 2 layer adjacent to the La-silicate IL was confirmed. Physical analysis revealed the reduction in carbon concentration and incorporation of La atoms adjacent to the La-silicate IL. [ABSTRACT FROM AUTHOR]

The deposition of high-quality ZrO2 films has been achieved using both pulsed plasma-enhanced chemical vapor deposition (P-PE-CVD) and plasma-enhanced atomic layer deposition (PE-ALD) with (C5H5)Zr[N(CH3)2]3 as a Zr precursor. The authors compared the growth characteristics, chemical compositions, and electrical properties of P-PE-CVD and PE-ALD ZrO2 prepared under various deposition conditions. The ZrO2 films prepared using both methods showed high purity and good stoichiometry. Electrical characterization of a metal-oxide-semiconductor capacitor utilizing the ZrO2 films showed that PE-ALD films have a relatively lower leakage current than P-PE-CVD films, whereas the dielectric constant, interface trap density, and hysteresis of both films are similar. Applying both methods, the electrical properties of ZrO2 films were also evaluated using In--Ga--Zn--O thin-film transistors (TFTs), which showed a good device performance in terms of high Ion-Ioff ratios (>108) and low off-currents (<10-11 A). In addition, ZrO2-based TFT showed high reliability against a negative Vth shift. Based on the self-limiting growth characteristics and electrical properties of P-PE-CVD, the authors found that the P-PE-CVD process results in electrical properties comparable to those of PE-ALD ZrO2 films. Thus, the authors believe that P-PECVD can be an alternative process to PE-ALD for future electronic device applications, especially for display applications due to its good electrical properties with high throughput. [ABSTRACT FROM AUTHOR]

GaN-based metal-oxide-semiconductor capacitors with ZrO as the dielectric layer have been prepared by atomic layer deposition. The accumulation and depletion regions can be clearly distinguished when the voltage was swept from −4 to 4 V. Post-annealing results suggested that the capacitance in accumulation region went up gradually as the annealing temperature increased from 300 to 500 °C. A minimum leakage current density of 3 × 10 A/cm at 1 V was obtained when O was used for the growth of ZrO. Leakage analysis revealed that Schottky emission and Fowler-Nordheim tunneling were the main leakage mechanisms. [ABSTRACT FROM AUTHOR]

The electrical, structural, and chemical properties of HfO2/Al2O3/GaSb metal-oxide-semiconductor capacitors (MOSCAPs) fabricated on Sb-rich (2 × 5) and Sb-stabilized (1 × 3) surfaces by atomic layer deposition are characterized. A combination of the transmission electron microscopic, x-ray photoelectron spectroscopic, and atomic force microscopic observations shows that the Sb-rich surface, with its excessive Sb atoms and clusters, leads to island deposition of the dielectric materials and results in the high leakage current of the MOSCAPs. For the MOSCAPs fabricated on the Sb-stabilized (1 × 3) surface, a density of interface traps as low as 8.03 × 1011 cm-2eV-1 near the valence band and 1.86 × 1012 cm-2eV-1 at the midgap is obtained as estimated by the conductance method. [ABSTRACT FROM AUTHOR]

Metal Oxide Semiconductor (MOS) capacitors (MOSCAP) have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer), time-temperature cycle and sequence are key parameters influencing the device’s output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application. [ABSTRACT FROM AUTHOR]

In this work the effect of Al deposition process and the subsequent forming gas annealing on the interfacial properties of Al/Al 2 O 3 /p-Ge MOS capacitors is studied. Al 2 O 3 has been deposited by ALD at 300 °C. There is evidence that Al deposition by e-beam evaporation affects the structure and composition of the Al 2 O 3 /Ge interface by decomposing the GeOx interfacial layer and leading to interfacial non-uniformities reflected in conductance measurements. Forming gas annealing is able to passivate interface traps near the valence band edge possibly originating from Al 2 O 3 –Ge dangling bonds during the dielectric deposition. However it is unable to passivate interface traps near the midgap possibly originating from e-beam evaporation radiation damage. [ABSTRACT FROM AUTHOR]

Hafnium oxide (HfO 2 ) is currently considered to be a good candidate to take part as a component in charge-trapping nonvolatile memories. In this work, the electric field and time dependences of the electron trapping/detrapping processes are studied through a constant capacitance voltage transient technique on metal-oxide-semiconductor capacitors with atomic layer deposited HfO 2 as insulating layer. A tunneling-based model is proposed to reproduce the experimental results, obtaining fair agreement between experiments and simulations. From the fitting procedure, a band of defects is identified, located in the first 1.7 nm from the Si/HfO 2 interface at an energy level E t = 1.59 eV below the HfO 2 conduction band edge with density N t = 1.36 × 10 19 cm − 3 . A simplified analytical version of the model is proposed in order to ease the fitting procedure for the low applied voltage case considered in this work. [ABSTRACT FROM AUTHOR]

Amorphous gallium oxide (Ga 2 O 3) thin films were investigated as gate dielectrics for electronic device applications using plasma-enhanced atomic layer deposition. The structural and morphological properties as well as the electrical and dielectric behaviors of Ga 2 O 3 thin films were explored. The surface morphology of the amorphous Ga 2 O 3 thin film was highly smooth with root mean square of 0.55 nm and low defect density, which were visible to atomic force microscopy. The grazing incidence X-ray diffraction pattern showed no discernible peak, indicating that the film was amorphous. The X-ray photoelectron spectroscopy depth-profiling analysis showed that the Ga/O ratio was 0.76, slightly more than the optimum 2/3 ratio (0.67). The temperature-dependent current–voltage characteristics of the Au/Ni/Ga 2 O 3 /p-Si structure revealed that ideality factor and barrier height values decreased and increased with increasing temperature, respectively, demonstrating their high temperature dependency. Regardless of the applied frequency, Ga 2 O 3 thin films exhibited a good dielectric constant of about ∼9 at zero bias voltage. The comprehensive capacitance–voltage analysis showed low trap densities of about 1012 eV−1 cm−2 at the Ga 2 O 3 –p-Si interface. • Amorphous gallium oxide (Ga 2 O 3) thin films were coated using plasma-enhanced atomic layer deposition (PEALD). • The charge-transport mechanisms of this structure were studied via temperature-dependent current-voltage (I–V) measurement. • The dielectric behavior of the fabricated MOS structure was explored using frequency-dependent capacitance-voltage (C–V) and conductance-voltage (G/ω − V) experiments. • The interface trap density (D it) was estimated using the admittance spectroscopy method at room temperature. [ABSTRACT FROM AUTHOR]

Diamond metal-oxide-semiconductor capacitors were prepared using atomic layer deposition at 250 °C of Al2O3 on oxygen-terminated boron doped (001) diamond. Their electrical properties were investigated in terms of capacitance and current versus voltage measurements. Performing X-ray photoelectron spectroscopy based on the measured core level energies and valence band maxima, the interfacial energy band diagram configuration of the Al2O3/O-diamond is established. The band diagram alignment is concluded to be of type I with valence band offset ΔEv of 1.34 ± 0.2 eV and conduction band offset ΔEc of 0.56 ± 0.2 eV considering an Al2O3 energy band gap of 7.4 eV. The agreement with electrical measurement and the ability to perform a MOS transistor are discussed. [ABSTRACT FROM AUTHOR]

The energy band alignment between atomic layer deposited (ALD) SiO2 and β-Ga2O3 (201) is calculated using x-ray photoelectron spectroscopy and electrical measurement of metal-oxide semiconductor capacitor structures. The valence band offset between SiO2 and Ga2O3 is found to be 0.43 eV. The bandgap of ALD SiO2 was determined to be 8.6eV, which gives a large conduction band offset of 3.63 eV between SiO2 and Ga2O3. The large conduction band offset makes SiO2 an attractive gate dielectric for power devices. [ABSTRACT FROM AUTHOR]

Comprehensive and systematic electrical studies were performed on fabrication of high quality SiO2 thin films MOS capacitor using the robust, novel, and simple atomic layer deposition (ALD) technique using highly reactive ozone and tris (dimethylamino) silane (TDMAS) precursors. Ideal capacitance-voltage curve exhibits a very small frequency dispersion and hysteresis behavior of the SiO2 MOS capacitor grown at 1s TDMAS pulse, suggesting excellent interfacial quality and purity of the film as probed using x-ray photoelectron studies. The flat-band voltage of the device shifted from negative toward positive voltage axis with increase of TDMAS pulses from 0.2 to 2 s. Based on an equivalent oxide thickness point of view, all SiO2 films have gate leakage current density of (5.18 × 10-8 A/cm²) as well as high dielectric break down fields of more than (~10 MV/cm), which is better and comparable to that of thermally grown SiO2 at temperatures above 800°C. These appealing electrical properties of ALD grown SiO2 thin films enable its potential applications such as high-quality gate insulators for thin film MOS transistors, as well as insulators for sensor and nanostructures on nonsilicon substrates. [ABSTRACT FROM AUTHOR]

This research focuses on the benefits and properties of TiO2-Al2O3 nanostack thin films deposited on Ga2O3/GaN by plasma-assisted atomic layer deposition (PA-ALD) for gate dielectric development. This combination of materials achieved a high dielectric constant, a low leakage current, and a low interface trap density. Correlations were sought between the films' structure, composition, and electrical properties. The gate dielectrics were approximately 15nm thick and contained 5.1 nm TiO2, 7.1nm Al2O3, and 2nm Ga2O3 as determined by spectroscopic ellipsometry. The interface carbon concentration, as measured by x-ray photoelectron spectroscopy depth profile, was negligible for GaN pretreated by thermal oxidation in O2 for 30 min at 850°C. The RMS roughness slightly increased after thermal oxidation and remained the same after ALD of the nanostack, as determined by atomic force microscopy. The dielectric constant of TiO2-Al2O3 on Ga2O3/GaN was increased to 12.5 compared to that of pure Al2O3 (8-9) on GaN. In addition, the nanostack's capacitance--voltage (C-V) hysteresis was small, with a total trap density of 8.74 x 1011cm-2. The gate leakage current density (J = 22.81 x 10-8 A/cm²) was low at +1V gate bias. These results demonstrate the promising potential of PA-ALD deposited TiO2/Al2O3 for serving as the gate dielectric on Ga2O3/GaN based MOS devices. [ABSTRACT FROM AUTHOR]

Atomic layer deposited (ALD) Al 2 O 3 /Ga-polar GaN(0001) metal–oxide–semiconductor (MOS) capacitors have been prepared with surface pretreatments including ex-situ wet sulfide passivation and in-situ cyclic trimethylaluminum (TMA)/hydrogen plasma exposure. Capacitance–voltage characterization showed that the two-step surface preparation led to reductions in the densities of both interface traps and border traps. The influence of the pretreatments on interfacial bonding was investigated by X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectrometry (SIMS). DFT calculations correlate the electronic properties with the interfacial bonding from the two-step surface preparation. The results are consistent with the surface preparations influencing the nucleation density of the ALD films and, therefore, the defect density of the interface and neighboring oxide. [ABSTRACT FROM AUTHOR]