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Nitrogen-incorporated tetrahedral amorphous carbon (ta-C:N) has electrochemical properties that are comparable to boron-doped diamond (BDD), but can be deposited at low temperatures, and is scalable across substrate areas substantially exceeding what is currently possible for BDD. Most published studies of ta-C:N electrodes focus on films deposited on conductive substrates due to the relatively high resistivity of ta-C:N compared to other carbon and metal-based electrodes. However, some of the most compelling applications of electrochemistry, for example, optically transparent spectroelectrochemical devices, require insulating substrates such as fused silica glass (FSG) or polymers. In this study, we deposited 50 nm of ta-C:N by laser controlled pulsed cathodic vacuum arc (Laser-Arc) onto insulating FSG to investigate the electrochemical response compared to conductive silicon (c-Si) substrates. No oxidation or reduction of potassium ferrocyanide during cyclic voltammetry (CV) could be observed at the FSG electrode. To address this, we introduced a 5 nm chromium (Cr) interlayer deposited by magnetron sputtering between ta-C:N and FSG. This electrode configuration led to clear cathodic and anodic CV peaks of potassium ferro/ferricyanide but with an increased peak separation compared to the c-Si electrode. However, the peak separation could be reduced to values comparable to ta-C:N deposited on c-Si by optimizing Cr sputtering conditions and introducing an argon plasma pretreatment of the FSG surface. Atomic force microscopy revealed that these changes improved the Cr growth homogeneity, which in turn increased the electrical conductivity of the Cr interlayer as determined by 4-point probe measurements. [ABSTRACT FROM AUTHOR]

For single crystal diamond (SCD) to gain practical use in technical applications including solid state electronics, thin (< $1 ~\mu \text{m}$), doped epitaxial SCD layers with very low (<1 nm) surface roughness are required. Conventional SCD chemical mechanical polishing (CMP) processes are insufficient to meet the requirements of such applications because the material removal rate (MRR) is often characterized inappropriately, and the material removal uniformity is seldom considered. In this study, chemical vapor deposition (CVD) growth of two lightly boron doped (p-) epilayers was performed on 3° misoriented (100) high pressure high temperature substrates of 4.5 x $4.5 mm^{2}$ area. A subsequent 8-hour oxidative CMP process utilizing potassium permanganate and a novel self-leveling holder design decreased the average surface roughness from 3.83 nm and 1.57 nm to 0.20 nm and 0.16 nm for the two samples, respectively. MRRs were determined by evaluating five circular wear monitor structures in each sample by atomic force microscopy before and after the CMP process. The average MRRs were found to be 38.6 nm/hr and 37.3 nm/hr for the two samples. The purpose of this study is to demonstrate a CMP process suitable for polishing thin SCD epilayers to meet the needs of solid-state electronics applications. [ABSTRACT FROM AUTHOR]