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Residue Number Systems (RNS) can simultaneously improve computing acceleration, area reduction and power saving. For high-reliability applications like automotive electronics, partition-ability empowers the redundant RNS fault tolerance. However the parallel multiple modular redundancy will take a huge number of converters. This is the first paper to incorporate AN codes to the RRNS applied in high-reliable neural networks. From experimental results, the k-modulus redundancy can be reduced from 2 paths to only one, and the residue-to-binary converters can be saved from (k+2)(k+1) to only k+1 for the external-coding structure, and even to only one for the internal-coding structure in the single residue arithmetic-weight error correcting. From BLER simulations, about 130 times of reliability can be achieved for a 16-bit 47N-coded MAC.

Acceleration and reliability are two critical issues of artificial intelligent circuits and systems. In this paper we propose a novel structure of deep neural network in testing stage that converts the trained weights to optimized ternary-coded binary. Within each shallow layer a constant-shift sub-layer with almostfree cost is inserted to transfer all multipliers to a carry save adder/subtractor. Then the activation functions are simplified to piecewise lines with nice slopes for calculation by an adder only. Since input-side layers tend to have self-healing ability, only output-side layers are equipped by AN codes that can be encoded and decoded almost without extra cost in our structure. From experiments and evaluations, our structure can have a higher resolution with error-correcting capability and a performance similar to the BNN.

Consumer electronics have become versatile for processing a lot of signals in any distribution. This results in that high-speed activating of neural network should fit for any distribution of error functions. In this paper, we propose a set of transistor-level magnitude-comparators. Then we apply them to develop range-addressable memory to design a lightweight-slope lookup table. We then develop an efficient algorithm for constructing a lightweight-slope piecewise line. The proposed techniques are suitable to design any sigmoidal activation functions in neural network. From experiments and comparisons, the proposed LUT can be more efficient effective than previous looking tables. Especially applied in the proposed range-addressable memory, the power-delay product can be reduced by more than 30 folds.

Neural Networks play an important role in modern smart cities full with omnipresent AIoT consumer electronics. However, computing acceleration results in issues in power dissipation, area overhead and reliability. In this paper, an arithmetic-weight minimization algorithm and approximate computing technique are proposed for power reduction and real time saving. From comprehensive evaluations, about 39% of real time and 56% of energy can be saved.

Residue Number Systems can solve several major problems of neural network including acceleration, power consumption, area overhead and fault tolerance. However, two major issues remain in the most recent work: (1) sign detection or magnitude comparison, and (2) long right shifts. In this paper, we develop a systematic approach to design a low power, compact, fast and reliable neural network automatically.

Neural Network suffers four major issues including acceleration, power consumption, area overhead and fault tolerance. In this paper we develop a systematic approach to design a low-power, compact, fast and reliable neural network based on a redundant residue number system. Residue number systems have been applied in designing neural network except the CORDIC-based activation functions including hypertangent, logistic and softmax functions. This issue results in that the entire neural network cannot be totally self-checked and extra operations make the time, power and area reductions wasted. In our systematic approach we propose some design rules for ensuring the checking rate without loss of reductions in time, area and power consumption. From experiments on three neu-ral network with 24-bit fixed-point operations for the MNIST handwritten digit data set, 3, 4, and 5 moduli are separately employed for achieving all balanced improvements in power-saving, area-reduction, speed-acceleration and reliability pro-motion. Experimental results show that all the power, time and area can be reduced to only about one third, and the entire network in any combination of software and hardware can be self-checked in an aliasing rate of only 0.39% and TMR-correctable under the single-residue fault model.

Sigmoidal activation functions play a key role in AI accelerators. They have been usually implemented by hyperbolic sine and cosine functions with a division since the CORDIC algorithm was proposed in 1956 and unified in 1971. From all literature it seems that people have never tried the simple algorithm proposed in this paper, in which only a half-domain exponential function is applied prior to a Booth division. More than one half of iterations and area can be reduced. From experimental results, both the area overhead and the power consumption can be reduced to only 1/3. The acceleration in backpropagation and learning rate can then be highly improved.

Neuromorphic RRAM has become the most promising candidate for AI applications. But it suffers three issues including degradation, defects and errors. To overcome the three issues we proposed a precompensation technique for compensating resistive degradation. A linear-system-based BIST architecture is developed with proposed diagonal sliding march test can effectively and efficiently screen out the uncompensated degradation and permanent defects. Analog Berger codes is proposed for detecting transient errors for variation learning and self-checking for asymmetric errors. From evaluations, the precompensation takes only 5/B time for batch operations of B cycles. Proposed BIST approach and method can reduced 2LN march tests to 6N for L-level RRAMs. The self-healing ability is verified by analog-Berger-code error detection. From experiments using a typical neural network for MNIST handwritten digit dataset the network can be healed with only 2% of accuracy and about 35% of training steps.