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Reduction of the contact resistance at source/drain and metal electrodes is one of the key challenges in the fabrication of high performance CMOS devices. In recent years, several studies have addressed the issue of minimizing the specific contact resistivity (ρ c ) [1] – [5] . Quite low values of ρ c in the sub-10 −9 ohm-cm 2 region have been reported for advanced technologies.

We used Flash Lamp Annealing (FLA) to control dopant diffusion in the nm range in n+/p germanium junctions. The diffusion of phosphorus was slower when co-doping with fluorine at doses below 2×1014 cm−2 compared to a sample without F doping. The diffusion lengths in samples with and without F were 6.7nm and 9.1nm, respectively. In addition, precise diffusion control below 7nm could be achieved without degrading the activation level in the sample with F doping. Owing to the slow rate of diffusion, this has quite a low impact on the deactivation of P. By co-doping F with boron, diffusion in the nm range can be achieved, demonstrating the potential for controlling B diffusion in Ge. Thus, ion implantation and FLA can be usefully applied in Ge CMOS fabrication processes.

Flash Lamp Annealing (FLA) is a well-known technique for millisecond annealing. In forming ultra-shallow junctions, FLA can provide high activation levels with precise diffusion control in the nanometer range. Currently, devices with 3D structures require conformal doping as well as diffusion control. Sol-Gel Coating (SGC / Tokyo Ohka Kogyo Co., Ltd.) has a special feature, in that a very thin film on the nanometer scale can be deposited on a 3D structure. In this work, we used SGC as a dopant source and FLA to demonstrate that highly activated junctions can be formed, and effective doping can be realized. Thus, this doping technique can be applied to advanced 3D devices, such as logic, memory and CMOS image sensor.

We are developing a new flash lamp annealing (FLA) system featuring flash lamps with short duration and high output power for all CMOS technology nodes including advanced devices. With this system, we can realize lower thermal budgets and higher peak temperatures (jump temperature). Our conventional FLA tool has a wide range of annealing conditions, with annealing times from 0.8 to 100 ms. The duration of the FLA conditions of the system we are developing can be extended to deep sub-millisecond levels, making it complementary to our conventional tool. In this report, we present initial data from a new prototype system. The data clearly demonstrate that higher activation can be achieved. Notably, supersaturated activation of 4.6×1020 cm−3 can be achieved with only slight diffusion of 5.8 nm in a p+/n Si junction. In addition, Hall effect measurements revealed higher carrier concentrations of up to 1020 cm−3 in polycrystalline Si (poly-Si). These results show that the new system has the potential for forming highly activated junctions with minimal diffusion in Si and poly-Si and can contribute to the fabrication of high performance devices.

In recent years Solid Source Doping (SSD) has been considered as a viable option in fabricating advanced CMOS devices [1], especially for forming shallow and highly doped junctions for source drain extensions (SDE) while minimizing the damage to the devices [2]. Current scaled devices require diffusion control in the nanometer range in order to form shallow SDEs using SSD. Additionally, high doping concentrations are needed to lower the resistivity (see Fig. 1).

We demonstrated the formation of ultra-shallow n+/p junctions in Si using an arsenic-doped Sol-Gel Coating (SGC) (Tokyo Ohka Kogyo Co., Ltd.) [1] and Flash Lamp Annealing (FLA). A high arsenic dopant concentration of 1.2×1020atoms/cm3 (Xj=9.0nm, Rs= 1203ohms/sq.) with a good junction profile (2.2nm/decade) was realized with 1.4ms FLA. These results indicate that this technique can be used for conformal doping of the Source/Drain Extensions (SDE) in sub-10nm FinFETs fabricated using advanced 3D device engineering.

A new millisecond, flash lamp annealing (FLA) tool has been developed. Building on the current tool's wide range of annealing times and temperatures, the new FLA tool is equipped with an ambient control system that can establish a reduced pressure and/or an NH3 reactive-gas ambient. These features have an advantage in gate stack anneals compared to conventional second order annealing: FLA prevents deactivation of dopants in gate-last processes, further densifies the HfO2 layer and the IL, and enables nitridation of the HfO2 layer while avoiding N diffusion to the Si substrate. Moreover, the electrical properties using MOSCAPs processed by FLA show prominent improvements in the EOT and gate leakage current. A positive Vfb shift is also observed in MOSCAPs using FLA. These results show that FLA using NH3 is a promising process for sub 10nm generation gate stack anneals.

In this paper, we report on the formation of shallow junctions with high activation in both n+/p and p+/n Ge junctions using ion implantation and Flash Lamp Annealing (FLA). The shallowest junction depths formed for the n+/p and p+/n junctions were 9.5 nm and 10.7 nm with sheet resistances of 620 ohms/sq. and 414 ohms/sq., respectively. Additionally, by reducing knocked-on oxygen during ion implantation, the sheet resistance was decreased by 5 to 15%. The lowest sheet resistance was 235 ohms/sq. with a junction depth of 21.5 nm in the n+/p Ge. These results indicate that the potential for forming ultra-shallow n+/p and p+/n junctions in the nanometer range in Ge devices using FLA is very high, leading to realistic monolithically-integrated Ge CMOS devices.

We demonstrate the formation of n+/p ultra-shallow junctions in Ge using Flash Lamp Annealing (FLA). With FLA both shallow junctions and high activation can be achieved, for example, a sheet resistance of 400 ohms/sq with a junction depth of 20 nm. The shallowest junction depth was 17 nm with a sheet resistance of 493 ohms/sq. In addition, by varying the FLA conditions, i.e., the temperature and annealing time in the millisecond range, diffusion lengths of less than 30 nm can be controlled with a precision of 1nm. These results indicate that FLA has great potential for forming ultra-shallow n+/p junctions in Ge devices.

After discovering that the annealing-time dependence of the flatband voltage shifts of a p/sup +/-polysilicon gate MOS diode can be attributed to boron activation in polysilicon instead of boron penetration through gate M/sub 2/, we proposed a boron activation model for polysilicon in which the carrier activation is related to the grain size of the polysilicon. Using this model, we analyzed the characteristics of pMOSFETs with polysilicon gates of different grain sizes and found that they depend on the grain size, as expected. Using the model, we quantitatively identified process windows for p/sup +/-polysilicon gate pMOSFETs, assuming that enough boron is activated in the polysilicon without the boron penetrating through the gate SiO/sub 2/.

We demonstrated that ion-implantation damage in gate SiO2-enhanced boron penetration in p-channel metal–oxide–semiconductor devices, easily enhances boron diffusion in SiO2 by ten times or more. This article describes the effectiveness of using high-temperature annealing above 1000 °C on damaged samples to suppress boron penetration in samples damaged by ion implantation. We also performed an electron spin resonance measurement to examine the damage recovery.

We have demonstrated surface cleaning for Si epitaxy using photoexcited fluorine gas diluted with argon (F 2 /Ar). We found that F 2 /Ar cleaning removed native Si oxide, as well as carbon contaminants. The method lowered the surface preannealing temperature needed to grow single-crystal Si films to 690 o C. This preannealing is equivalent to annealing in a hydrogen ambient in conventional chemical vapor deposition. The temperature is low because the native Si oxide is thinned by F 2 /Ar cleaning

Idea of a very short time annealing technology has evaluated in 1980s. Engineers tried to use Flash lamp, laser or some other lamps [1]. In 1990s, W-halogen lamp annealing replaced furnace annealing in activation and silicidation process. Thermal budget has reduced from minutes to seconds. Eager for Milli-second Annealing (MSA) really came out in 2000s. Since dopant diffusion and an activation ratio have been considered to be more critical obstacle in scaled down microstructure devices, FLA activation technology came into spotlight again [2–9]. A 65nm device was a first product which used Flash Lamp Annealing (FLA) in manufacturing. Today, milli-second process has become an indispensable method in device manufacturing. But device generation keeps proceeding 45nm, 32nm and so on. Furthermore, a new material like high-k/metal is selected as a latest device material. Difficulty in MSA for 32 and 22 generation devices is reported recently.

Millisecond annealing (MSA), such as flash lamp annealing (FLA) and laser spike annealing, is used for dopant activation of ultra-shallow junctions (USJ) in scaled complimentary metal-oxide-semiconductor (CMOS) devices. This is because lower sheet resistance (Rs) and less dopant diffusion are achieved with MSA and these are crucial requirements for minimizing the junction depth (Xj) in state-of-the-art CMOS [1–5]. In FLA the sample is irradiated for a few milliseconds with a Xe-lamp after pre-heating to 500°C or more. The assisted heating is done either using a resistive heater or by irradiation with a halogen lamp. With lamp heating, the assisted temperature (T A ) range is from 500 to 1000°C compared with from 300 to 600°C using a resistive heater. In addition, with lamp assisted heating the temperature profile can be controlled to the second order, similar to spike rapid thermal annealing (sRTA). Thus, we can use higher T A with less dopant diffusion, and higher pre-heat temperatures enable higher peak temperatures during Xe-lamp irradiation. We also used a Flexibly-Shaped-Pulse (FSP) system to control the annealing time and temperature [6–10]. By combining FSP technology with lamp assisted heating, we expect to be able to have control over a wide-range of annealing times and temperatures. In addition, this combination may produce a synergistic effect on device performance. In this report, we examine, first, the effects of high assisted temperatures. Then, we demonstrate the excellent potential of combining FSP technology and lamp assisted heating on device performance.

We have developed a carbon absorber process to reduce the pattern effect. This process consists of deposition of carbon, flash lamp annealing (FLA) in an oxygen ambient and SPM-APM wet cleaning. The feature of this process is that the carbon absorber equalizes the light absorption from flash lamps macroscopically and microscopically on the annealed wafer. As a result, we can suppress the pattern effect such that the uniformity of Rs in a 40mm × 40mm area is improved from 11.4 % to 2.1 %. Additionally this process can achieve higher activation than that without the carbon absorber process. We also demonstrate that a flexibly-shaped-pulse FLA (FSP-FLA) can suppress the pattern effect to give a uniformity of 3.4 %. By combining the carbon-absorber process with FSP-FLA, we can achieve 1.6 %. This Rs uniformity of the pattern effect is comparable to that of sRTA.

We have presented functional annealing data using the FSP-FLA, together with some examples of the multi-functionality. First, we showed that the FSP-FLA can control thermal budget whilst sustaining high dopant activation, recovering crystalline defects, and controlling thermal diffusion length. Secondly, by combining impulses from conventional FLA and the trapezoidal pulse of the FSP-FLA, we can improve BTI lifetime and μeff, without degrading Rs-Xj characteristics. In addition, we showed the FSP-FLA pulse for preheat control. Therefore, we have a high confidence that FLA has evolved to the 2nd generation with the FSP-FLA system and it will be a main-stream annealing method for scaled high-k/metal gated devices in the near future.

We investigated the influence of extremely high doping concentrations on the sheet resistance of ion implants annealed by FLA. As the implant depth was ultra-shallow and the amount of dopant atoms high, the concentration of dopant near the surface was exceedingly high, above the solid solubility limit, resulting in high Rs. The cause of this is mainly due to the formation of clusters, which was confirmed by calculation and experimental data. The clustering was occurred during the preheating process before the Xe-lamp flash irradiation.

We activated boron‐doped polycrystalline Si at 1100°C, and studied the time dependence of the gate resistance with respect to subsequent processing steps at lower temperatures. The resistance does not change over time for a dose of . However, for a higher dose of , it increases with time and finally saturates. For any temperature above 800°C, the onset time for the resistance increase is about 30 s, while for lower temperatures, the time becomes significantly longer. In other words, the sheet resistance obtained at higher temperatures is degraded if the subsequent annealing time is longer than this onset time. © 1999 The Electrochemical Society. All rights reserved.

We investigated Sb diffusion in p - , p + , and n + substrates and determined the diffusion coefficient. We showed that our evaluated diffusion coefficient associated with neutral point defects is lower than the reported values by one order of magnitude, and it provides a better explanation of experimental data over a range of annealing conditions.

We studied dopant (boron) activation using flash lamp annealing (FLA) from a view of depth dependence in silicon substrate. As FLA is an annealing method by which temperatures of surface region only rump up and down rapidly, the dopants in deep region of wafer might be unable to be activated. We confirmed that carrier concentration in deep region activated by FLA was surely low compared with that by spike rapid thermal annealing (sRTA). However, the depth dependence of the carrier activation was resulted from the dopant concentration dependence and the degree of the damage recovery, not from the thermal budget dependence.

This paper describes the applications of cluster ion implantation for beyond 45 nm node novel devices. A) Metal/high-k MOSFET: a flash lamp annealing (FLA) has advantage of dopant diffusion-less characteristics, but it requires suitable angle control for optimum gate overlap length. Cluster boron implantation with tilted SDE implantation for p-FETs has superiority over monomer boron implantation with Ge PAI (pre-amorphous implantation) in terms of VTH roll-off s and ion-ioff s if FLA is used as activation anneal. Full-metal-gate HfSiON transistors whose gate length is less than 50 nm are fabricated with superior electrical characteristics. B) n-MOS stress engineering: Si:C formation with high carbon substitution has been obtained using cluster carbon implantation and msec annealing which leads to higher stress in the channel region. C) Fin-FET: high tilt angle with low energy boron cluster ion implantation is found to improve the retained dose compared to monomer boron. It is suitable for Fin-FET implantation applications.

We have investigated the process of flash lamp annealing (FLA) in a dilute oxygen ambient. The oxide grown during this process protects against wet chemicals and maintains the low sheet resistance (Rs). The influence of several wet chemical cleans after FLA on ultra-shallow junction (USJ) characteristics were evaluated, and it was found that wet chemical cleaning increased the Rs of the doped layer. In the worst case, the advantage (high activation) of FLA was substantially lost. We therefore proposed the formation of a capping oxide by adding oxygen to the ambient during the FLA process to prevent the increase of Rs, and to demonstrate its function in providing a highly-effective protective barrier.

Beyond 45 nm device fabrication, it is recognized that the ultra‐shallow junction (USJ) formation is required, which is achieved by the ultra‐low energy ion implantation and ultra‐low diffusion annealing. For this purpose, Cluster ion implantation (CII) and the Flash lamp annealing (FLA) activation processes have been developed. In this paper, we introduce characteristics of activation using B18Hx+ implantation with FLA, which are applied to a source drain extension (SDE) for pMOSFET in Hgh‐k/metal process. We will prove that the combined process of B18Hx+ and FLA can make the low sheet resistance and the fine crystal recovery for USJ formation such a SDE. Moreover, the combined process of C7Hx+ implantation and FLA can make the high stress region for nMOSFET by the high substitutional Carbon. If both of B18Hx+ implantation and C7Hx+ implantation with FLA are applied to High‐k/metal process, it will give the highest performance. The combination of FLA and cluster ion implanter “CLARIS” which is developed ...

We studied the characteristics of ultra-shallow junctions (USJ) formed by flash lamp annealing (FLA) to reveal the nature of the dopant activation. A pre-amorphized layer is effective in activating dopants in FLA. End-of-range (EOR) defects remain close to amorphous/crystal (a/c) interface. FLA with low lamp power results in the amorphous layer remaining in the surface. Sb is highly activated, compared to As. These phenomena exhibit a correspondence with the activation during solid-phase epitaxial regrowth (SPER), where dopants are activated in a thermal non-equilibrium condition. Therefore, we conclude that FLA is a form of SPER, employing high temperatures and short (mili-second) times. The high temperature in FLA achieves higher dopant activation than obtained in SPER, whilst eliminating shortcomings found with SPER.

We propose here cost-effective gate-first dual-metal/dual-high-k CMOS technology in which Fermi-level pinning is "positively" utilized to reduce threshold voltages for the first time. After systematic investigation on the relation between oxygen vacancies in Hf-based high-k film and electrical characteristics, we concluded that the Fermi-level pinning is unavoidable in principle with a thin EOT, but is a stable phenomenon that should be intentionally utilized. In our proposed method, source of oxygen interstitials (Al) is contained in metal gate material for p-FET, and consequently the flatband voltage is properly modulated by "opposite" Fermi-level pinning due to the oxygen interstitials incorporated into the underlying high-k film after high temperature annealing. It is also noteworthy that this method is simple and cost-effective because the initial high-k films are identical for n-and p-FET but they are automatically converted into dual high-k after the annealing process.

Recently, boron cluster implantation (i.e. decaborane: B10Hx+) is regarded as a promising technology for the formation of P‐type Ultra Shallow Junction (USJ) because of the equivalent high beam current with less beam divergence compared to the conventional B+ or BF2+ implantation. Also as‐implanted and after‐annealing characteristics are different due to the appearance of self‐amorphized layer by the cluster ion bombardment, which suppresses the channeling and enhances the boron activation. However, it is anticipated that the properties caused by this amorphous layer will vary with different implantation conditions or a presence of Pre Amorphization Implantation (PAI) process, which should be understood well to maintain a good process control. From this point of view, we have measured the decaborane implantation characteristics by a couple of different related conditions, for instance, the beam energy and current. Sheet resistance vs junction depth (Rs‐Xj) are also evaluated in different annealing methods...

The x-ray interference technique has been applied to evaluate the structural changes of high temperature grown chemical vapor deposited (CVD) SiO2 film under several post annealing conditions. In annealing above 800 °C in O2 ambient, a thermal oxide growth has been found at the CVD SiO2/Si interface, and its precise thicknesses have been determined. The estimated diffusion coefficient of the oxidant in CVD film was about three times larger compared to that of thermal oxide. A threshold voltage shift in the oxide was found to strongly correlate to the thickness of the thermal oxide rather than to thermal modifications of the CVD SiO2 itself.

We report on the nMISFETs (n-type metal-insulator-semiconductor field effect transistors) characteristics for the atomic layer chemical vapor deposition (ALCVD) HfO/sub 2/ gate stack and the behavior of the HfO/sub 2/ layer during annealing on various oxides.

Nitrided-oxide gate dielectrics have been proposed to suppress boron penetration in deep submicron metal-oxide-semiconductor field effect transistors (MOSFETs). However, few quantitative reports have been released on how nitrided oxides enlarge the permissible thermal budget. We evaluated the diffusivities of a nitrided oxide formed by annealing SiO2 in NO gas and demonstrated that this film enables us to use BF2+ for scaled devices. We also proposed a model depicting boron penetration through the nitrided-oxide layer.

We have clarified the effects of activation annealing temperature on the negative bias temperature instability (NBTI) and time-dependent dielectric breakdown (TDDB) lifetime improvement of HfSiON/TiN gate stack p-type metal–oxide–semiconductor field effect transistors. Higher-temperature annealing is effective for the improvement in NBTI and TDDB lifetime. This is due to the Si substrate oxidation occuring during the high-temperature annealing, resulting in interface defect state reduction. Annealing is also effective for reducing threshold voltage with consequential improvement in device performance.

We discuss scaling the equivalent oxide thickness (EOT) of Hf-based high-k gate dielectrics by post-deposition annealing (PDA). Thin HfON/SiON gate stacks with EOT=0.57 nm were successfully formed by repeating ultra thin (0.6 nm) HfO2 deposition and high-temperature (950 °C) PDA on a previously formed SiON interfacial layer. Physical and electrical analyses revealed that the reduction in EOT was due to crystallization of HfON to the tetragonal phase which has a higher dielectric constant than the amorphous and other crystalline phases. It was also found that Hf diffusion in the SiON interfacial layer was induced by the high-temperature PDA treatment. This also improved the k-value of the interfacial layer and enabled aggressive scaling even when using a SiO2-based interfacial layer. The electron mobility of the gate stack is higher than those in the previous reports, indicating that a high quality interface is realized using this approach. The reduction in EOT together with the excellent interfacial quality demonstrated in the present study shows that this technique is a promising solution for the 22-nm-node and beyond.

We studied the characteristics of ultra-shallow junctions (USJ) formed by flash lamp annealing (FLA) to reveal the nature of the dopant activation. We found that FLA is a form of solid phase epitaxial regrowth(SPER), employing high temperatures and short (mili-second) times. This achieves higher dopant activation than obtained in SPER.

Nitrided-oxide gate dielectrics have been proposed to suppress boron penetration in deep submicron metal-oxide-semiconductor field effect transistors (MOSFETs). However, few quantitative reports have been released on how nitrided oxides enlarge the permissible thermal budget. We evaluated the diffusivities of a nitrided oxide formed by annealing SiO2 in NO gas and demonstrated that this film enables us to use BF2 + for scaled devices. We also proposed a model depicting boron penetration through the nitrided-oxide layer.