Search

The channel mismatches, particularly the gain and the timing skew errors degrade significantly the performance of high-speed Time-Interleaved Analog-to-Digital converters (TIADCs). The error correction using blind calibration methods is difficult because of the correlation between the input signal and the noise signal caused by these channel mismatch errors. In this paper, a new fast convergent algorithm is proposed to correct the gain mismatch and timing skew errors. This new algorithm is based on oversampling and guarantees the independence of the signal and the noise. To estimate noise produced by gain mismatch and timing skew error, a new structure based on modulation concept is developed. The proposed adaptive compensation structure has fast convergence speed using an accurate estimated error signal and a simple cost function. The proposed structure unlike other oversampling-based algorithms is applicable in narrow-band signals by selecting the optimum oversampling ratio. The proposed algorithm is simulated using a four-channel TIADC with 10-bit resolution. Theoretical analysis and simulation results verified the fast convergence speed and the good performance of the proposed algorithm for both narrow-band and wide-band signals. [ABSTRACT FROM AUTHOR]

In this paper, a digital processor is presented for full calibration of pipeline ADCs. The main idea is to find an inverse model of ADC errors by using small number of the measured codes. This approach does not change internal parts of the ADC and most known errors are compensated simultaneously by digital post-processing of the output bits. Some function approximation algorithms are tested and their performances are evaluated. To verify the algorithms, a 12-bit pipelined ADC based on 1.5-bit per stage architecture is simulated with 1%-2% non-ideal factors in the SIMULINK with a 20 MHz sinusoidal input and a 100 MS/s sampling frequency. The selected algorithm has been implemented on a Virtex-4 LX25 FPGA from Xilinx. The designed processor improves the SNDR from 45 to 69 dB and increases the SFDR from 45.5 to 90 dB. The calibration processor also improves the integral nonlinearity of the ADC. [ABSTRACT FROM AUTHOR]