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In this paper, a new lumped-element Class-F3/E and transmission-line (TL) Class-F3/E2 power amplifiers are presented. It is shown that employing the series output filter (inverse Class-E) combined with a third harmonic control circuit (Class-F) leads to the new Class-F/E power amplifier. Compared with other switch-mode Class-E, Class-F/E, and Class-E/F power amplifiers, the proposed circuit has a higher maximum operating frequency (fmax), higher output power capability (Cp), and lower peak drain voltage (Vmax). The capability of the Class-F/E mode with a series filter has been demonstrated by two design examples, one with lumped elements at 100 MHz and the other with transmission lines at 2.21 GHz. Two test boards of power amplifiers were measured, and high-performance results have been obtained. The simulated and measured drain efficiency (DE) of 86.4/85%, output power of 41/40.6 dBm, and gain of 15.9/15.6 dB for the lumped-element Class-F3/E power amplifier have been obtained. On the other hand, the simulated/measured DE of 83/81%, power added efficiency of 79/78%, and output power of about 40/39.8 dBm for Class-F3/E2 power amplifier at an input power of 27 dBm were obtained.

This letter presents the design of a Dual-mode W-band eight-way power-combining power amplifier (PA) implemented in Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS technology ( $f_{t}$ / $f_{{max}}$ : 210 GHz/240 GHz). A configurable parallel-series-based eight-way power combine technique is proposed to achieve high output power with high power efficiency near half of $f_{t}$ . The eight-way power-combiner is consisted of two transformer-based parallel two-way differential combiners and a coupled-line-based series combiner to achieve high passive efficiency and compact layout. The proposed PA achieves a measured peak gain of 30.9 dB with a bandwidth (BW) of 7.5 GHz. The PA has $P_{{sat}}$ of +18 dBm with an 1dB output compression point (OP1dB) of +13.8 dBm and a peak PAE of 15.1% in high-power mode. In the low-power mode (LPM), the measured $P_{{sat}}$ , OP1dB, and peak PAE are +13.6, +9.1 dBm, and 10.3%, respectively. The PAE is enhanced by 3.4% points at a 6-dB back-off in LPM. The core area of the proposed PA is 0.3 mm².

This paper proposes a variable gain power amplifier (VG-PA) with stable linearity for n257/n258 frequency band applications. A switched-capacitor array is proposed in the cascode (CC) circuit to control the gain while maintaining linearity. A compensation inductor is introduced between the common-emitter (CE) and common-base (CB) transistors to suppress the phase variation. For the proof of concept, the VG-PA was fabricated in a 0.13-μm SiGe BiCMOS technology with a core size of 0.59 × 0.46 mm. Measurements show that at 24/26/28/29.5 GHz, over 5.7/5.5/7.0/7.5-dB gain tuning range, the output 1-dB compression point (OP1dB) is better than 14 dBm with OP1dB less than 1.2 dB, the third-order output intercept point (OIP3) is better than 22 dBm with OIP3 less than 3.4 dB, and the phase variation (φ) is from 3 to 9.5∘. To the author’s best knowledge, this work has the lowest linearity variation among Si-based variable gain amplifiers at millimeter-wave frequency band.

This paper introduces a design methodology that reduces the fundamental trade-off between linearity and power added efficiency (PAE) in CMOS power amplifier (PA). In our work, a stacked power block...

This article presents a fully integrated IEEE 802.11aj direct-conversion transceiver system in a 120-nm SiGe:C BiCMOS technology. The system includes a transmitter, a receiver, and two onboard substrates integrated waveguide-fed Yagi-Uda antennas. In the millimeter-wave frequency band, the common-mode (CM) signal in a transformer-based balun is a limiting factor for the linearity of differential devices. In this work, we analyze the cause of the CM effect and provide fast impedance equalization with a passive component compensation method to resolve this problem, which improves the linearity of the transmitter. A T-type second-order harmonic termination method is applied at the power amplifier (PA) output to further improve the linearity of the transmitter. The self-mixing method-based power detector is adopted at the output of the transmitter to have an accurate image signal and local oscillator (LO) leakage calibration. The transmitter reaches an output 1-dB compression point (OP1,dB) of 14.6-16.4 dBm and a conversion gain (CG) higher than 24 dB in the IEEE 802.11aj frequency band, operating from 42.3 to 48.4 GHz. The receiver achieves a 3.8-4.1-dB noise figure, -18.7- to -22-dBm input 1-dB compression point, and a CG better than 43.8 dB in the IEEE 802.11aj frequency band. In the system wireless data transmission test, the transceiver is fully compliant with the error vector magnitude (EVM) requirement of the IEEE 802.11aj standard up to the 64-quadrature amplitude modulation (QAM) operating mode, and the measured transmitter-to-receiver EVM is better than -28.5 dB at a 1-m distance over the IEEE 802.11aj frequency band. Compared to other states of the art, the transmitter's OP1,dB is the highest, and the demonstrated transceiver system delivers the highest performance in the IEEE 802.11aj wireless link.

This article presents an efficient quadrature digital power amplifier (DPA) based on a complex-domain Doherty (CDD) architecture. The proposed CDD architecture allows a PA to achieve high efficiency through Doherty operation in a complex domain using two independent vectors with different amplitudes and phases. It demonstrates high efficiency when two vectors have in-phase components in the complex domain by introducing an additional efficiency peak. The proposed DPA based on a switch-capacitor PA (SCPA) employs the CDD and dual-supply Class-G techniques to enhance system efficiency (SE) and adds three additional efficiency peaks down to 12-dB power back-off (PBO). An additional efficiency peak at 6-dB PBO and two additional efficiency peaks at 2.5- and 12-dB PBOs are associated with CDD and Class-G, respectively. The prototype, fabricated in a 65-nm CMOS process, achieves 27.8-dBm peak output power ( $P_{\mathrm {OUT}}$ ) with a peak SE of 32.1%. It exhibits an error vector magnitude (EVM) of −42.0 dB (−43.3 dB) at a $P_{\mathrm {OUT}}$ of 14.7 dBm (15.4 dBm) for an 802.11ax 40-MHz (20-MHz) 1024-QAM OFDM signal with 13.1-dB (12.4-dB) peak-to-average power ratio (PAPR) at 2.2 GHz. The average SE measured with a 20-MHz single-carrier 1024-QAM signal with 6.8-dB PAPR at a $P_{\mathrm {OUT}}$ of 21 dBm is 18.4%.

A high-efficiency concurrent dual-band GaN power amplifier (PA) is designed and fabricated based on the network parameter extraction (NPE) method, where the expanded optimum load impedance spaces of continuous modes are applied to construct the NPE criteria to facilitate harmonic tuning. A swallow-spit process is proposed to improve the effectiveness of NPE by dynamically changing the criteria. The prototype design process verified that the proposed algorithm is easy to be implemented, which avoids the cumbersome tunings and complex numerical derivations on the parameters of the dual-band output matching networks. Measurement results demonstrate that the fabricated GaN PA achieves saturated output powers of 40.5 dBm ± 0.4 dBm and 41 dBm ± 0.3 dBm over dual bands of 0.6–0.8 GHz and 1.6–1.9 GHz with peak PAEs of 71%–74% and 68%–73%, respectively.

This article presents the design of a dual-mode V-band power amplifier (PA) that enhances the efficiency at power back-off (PBO) using load modulation. The PA utilizes a reconfigurable two-/four-way power combiner to enable two discrete modes of operation–full power and back-off power. The power combiner employs two techniques to further improve the PA efficiency at PBO: 1) usage of transformers with non-uniform turns ratios to reduce the difference in impedance presented to the PA cores between the two modes and 2) utilize a proposed switching scheme to eliminate the leakage inductance associated with the disabled path in back-off power mode (BPM). The two-stage PA achieves a peak gain of 21.4 dB with a fractional BW (fBW) of 22.6% (51–64 GHz). At 65 GHz, the PA has a Psat of +17.9 dBm with an OP1 dB of +13.5 dBm and a peak power added efficiency (PAE) of 26.5% in full-power mode. In BPM, the measured Psat, OP1 dB, and peak PAE are +13.8 dBm, +9.6 dBm, and 18.4%, respectively. The PAE is enhanced by 6% points at a 4.5-dB back-off. The PA is capable of amplifying a 6 Gb/s 16-QAM modulated signal with an EVMrms of −20.7 dB at an average Pout/PAE of +13 dBm/13.6%, respectively. This PA was implemented in 16-nm FinFET, occupies a core area of 0.107 mm2, and operates under a 0.95-V supply.

In this brief, A two-stage power amplifier (PA) with a four-way series-parallel power combiner is presented for Ka-band applications. A compact power stage with optimized cascode transistors is proposed to minimize the parasitic effects and boost the amplifier output power at the mm-wave frequencies. The output network employs two spiral transformers and a transmission-line combiner to realize low-loss power matching and broadband series-parallel combining. The PA is fabricated in a 130-nm SiGe BiCMOS technology and it occupies a core area of 0.48 mm2. The PA achieves a peak gain of 25.3 dB with the 3-dB bandwidth of 30-to-41 GHz. At the frequency of 35 GHz, the measured saturated output power (PSAT), 1-dB compressed power (OP1dB), and power-added efficiency (PAE) are 22.8 dBm, 22.6 dBm, and 27%, respectively.

This letter proposes a high output power 250-GHz power amplifier adopting dual-shunt elements in the implementation of maximum achievable gain ( $G_{\mathrm {max}}$ ) core. By the adoption of the dual-shunt-element-based $G_{\mathrm {max}}$ -core, the output transistor size can be increased, which leads to higher output power. Implemented in a 65-nm CMOS, the measurement results show a peak gain of 12.6 dB, $P_{\mathrm {sat}}$ of 3/3.8 dBm, OP1 dB of 1.4/2.3 dBm, and peak power-added efficiency (PAE) of 4.8/3.2% at 248.6 GHz while dissipating 40/62.4 mW from a 1/1.2-V supply, respectively.

This article presents a wideband millimeter-wave (mmWave) receiver front-end that covers the frequency range from 43 to 97 GHz, supporting the operation in the major parts of the V-, E-, and W-bands. The front-end incorporates a passive mixer-first topology to achieve high linearity and wideband performance. The front-end adopts I/Q generation at the RF port, using a coupled-line coupler (CLC), rather than at the local oscillator (LO) port to mitigate the crosstalk of the overlapping I/Q LO signals especially present at high frequencies. The CLC at the RF input facilitates ultrawide band input matching. The front-end implements the multi-gate gm3 cancellation technique at the IF amplifiers to preserve the linearity and provide gain at the IF section. Image rejection capabilities using a current mode transformer-based IF 90° coupler are implemented on chip and demonstrated with measurements. The front-end prototype is fabricated on the GlobalFoundries 22-nm FD-SOI CMOS process and it demonstrates an ultra-wideband performance across the frequency range 43–97 GHz (2.25:1 bandwidth) with image rejection of up to 32 dB, IIP3 of 1.6–5.2 dBm, and gain of 15 dB. The implementation used is low-IF topology with 3.8-GHz IF frequency and 1-GHz bandwidth. Furthermore, the measurement results show that the front-end supports high-speed modulated signals of up to 6-Gbps 64QAM modulation data.

Purpose The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE). Design/methodology/approach The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (gm3) to be canceled with the main PA’s fixed negative gm3. The gm3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity. Findings For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc. Originality/value In this study, a novel cascaded gm3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

This paper presents a new design methodology for broadband Doherty architecture using the three-port input and output networks technique. The proposed topology was developed to overcome the Doherty power amplifier (DPA) bandwidth limitations. The output three-port network performs the impedance matching from any load impedance to the optimum loads for both main and peaking transistors and also combines the power delivered from the two devices at any power ratio. On the other hand, the input-splitting network is proposed for matching the input impedances of the two transistors to the source impedance. The freedom in choosing the power division ratio of the input network enables us to achieve a tradeoff between efficiency and linearity. Also, it provides a way to accomplish the phase compensation using an arbitrary phase difference between the two branches of the Doherty power amplifier and thus, helps obviate the need of the highly bandwidth limiting offset lines found in the Doherty design. A two-stage broadband Doherty power amplifier is implemented using 0.25-um GaN HEMT MMIC process to validate the proposed topology. The fabricated DPA was measured under both continuous wave (CW) and modulated signal at different operating frequencies. Across 3.3–3.7 GHz, the implemented DPA delivers a maximum output power exceeding 42 dBm, power added efficiency (PAE) over 52 % at the peak power and over 38 % in the back-off state over the operating 400 MHz bandwidth. The fully integrated circuit has a chip-size of 4.4 mm $\times\,\,3.5$ mm.

This letter presents a fully integrated three-stage single-ended $D$ -band power amplifier (PA) designed in 0.13- $\mu \text{m}$ silicon–germanium (SiGe) BiCMOS technology. Several bandwidth extension techniques and matching networks are mutually exploited to maximize Bandwidth (BW) performance while assuring unconditional stability. Its measured 3-dB bandwidth covers the entire $D$ -band (110–170 GHz). The PA has a small-signal peak gain of 21 dB at 151 GHz. Its saturated output power ( $P_{\mathrm{ sat}}$ ) in the $D$ -band varies from 11.8 to 13.9 dBm and its output referred 1-dB compression point (OP1 dB) from 9.2 to 12.5 dBm within the $D$ -band. The presented amplifier occupies $0.65\times 0.47$ mm2 (including pads) and draws a current of 115 mA from a 3.3-V supply. To the best of our knowledge, these performances represent the state of the art in silicon technology with a minimum ( $P_{\mathrm{ sat}}$ ) of 11.8 dBm and (OP1 dB) of 9.2 dBm covering the entire $D$ -band.

The demonstration of a 75–305-GHz power amplifier (PA) monolithic microwave integrated circuit (MMIC) is presented in this letter. The PA is based on an eight-cell traveling-wave unit amplifier (UA). Each cell contains an RF cascode with two two-finger transistors with a gate width of 20 $\mu \text{m}$ each. In the output stage, a balanced configuration combines two UAs with Lange couplers. In front, a third UA is used as a driver amplifier. The PA MMIC is fabricated in a 35-nm gate-length metamorphic high-electron-mobility transistor technology. From 75 to 305 GHz, the PA yields a minimum output power of 10 dBm with an average value of 12.8 dBm. At 200 GHz, a peak output power and PAE of 14.9 dBm and 6.6% is achieved, respectively. To the best of the authors’ knowledge, this is the first PA MMIC with an octave-bandwidth that provides an output power of 10 dBm at 300 GHz.

A novel architecture for the On Off Keying (OOK) modulator with high gain and high data rate power amplifier (PA) operating at 11.6 GHz IBM 0.18-µm RF CMOS technology is presented for a X-band passive RFID tag. Currently used low frequency switching techniques such as multiplexers were not functioning in the high frequency X-band architectures. In this novel approach OOK modulator with power amplifier, a CMOS switch was used to transmit ‘1’ and ‘0’ coming from the digital signal unlike in the existing low frequency architectures. Both the load and driver in this proposed PA were class A operation supplied by a single ended 1.83V source. The important design considerations include output power, 1 dB compression point and linearity. The fabricated results of the amplifier have a 1 dB compression point of 1.2 dBm and input power of 5.19 dBm at 9.2 GHz.

This article presents a dual-band millimeter-wave front end in 45-nm CMOS silicon-on-insulator (SOI) for 5G applications. The front end is composed of a low-noise amplifier (LNA), power amplifier (PA), and a single-pole double-throw (SPDT) switch. A double-tuned PA is used and is based on a two-stage stacked amplifier with a reconfigurable load using SOI switches, so as to achieve an optimal load for both 28- and 39-GHz 5G NR bands. A wideband series-shunt switch is also developed with high power handling (P1dB >22 dBm) and $P_{\mathrm {sat}}$ is > 18.8 dBm and the peak PAE is 18% at 24–30 GHz and includes the switch loss and compression. For high-band operation, the gain at 36–40 GHz is 13.6 ± 1.5 dB with $P_{\mathrm {sat}} > 18$ dBm. To the best of our knowledge, this is the first front end that covers both the 24–28- and 37–40-GHz 5G bands with high output power and low-NF. Application areas are in multistandard base stations and small cells.

A 35-GHz transmitter (TX) and receiver (RX) front end in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers are presented in this article. While typical FMCW phased-array radar transceivers use RF-path phase-shifting scheme for both TX and RX front ends, the Ka-band TX and RX front ends presented in this article are designed for TX-analog and RX-digital beamforming phased-array radar system. The link budget for the Ka-band phased-array radar transceiver is investigated. In order to improve the TX output power level, a power amplifier (PA) with a four-way power splitter/combiner is introduced. The detailed analyses and design considerations of the PA are investigated. The proposed TX and RX front ends are implemented and fabricated in a 1P9M 65-nm CMOS technology. The measured TX output power is 19 dBm. To the best of authors’ knowledge, it is the highest output power FMCW module at the Ka-band using CMOS technology reported so far. The RX achieves a conversion gain of 29.6 dB. The TX occupies 1.42 mm2 and consumes 588 mW. The RX occupies 0.59 mm2 and consumes 72 mW.

We propose a digitally intensive, reconfigurable RF transmitter with an integrated, tunable Class-E power amplifier (PA) which can be configured to operate from 0.75 to 2.5 GHz in discrete bands, while delivering an output power of 11.5 dBm up to 1.5 GHz and 6.5 dBm up to 2.5 GHz. Digital signal processing is exploited to suppress sampling spurs up to the harmonics of the carrier, thus eliminating the need for sharp RF filters. The proposed techniques make the transmitter adaptable to signals of different bandwidths and to different carrier frequencies with minimal overhead in power and area when compared to other digital transmitter designs. Digital predistortion is used to linearize the PA. The transmitter also includes clock correction circuitry for correcting duty cycle and quadrature errors. A generic design methodology is mathematically developed for a reconfigurable Class-E PA with a fixed series inductor. This transmitter scales well with technology and can be potentially used for spectrum sharing (SS) applications in fifth generation (5G) radios. Implemented in a 130-nm CMOS technology, the proposed transmitter occupies an area of 1 mm2. A maximum output power of 13.7 dBm with a maximum efficiency of 27% is obtained at 1 GHz.

This article presents an analytical and coherent design method for the generalized high-efficiency broadband parallel-circuit (PC) Class-E/F 3 power amplifier (PA). By importing the initial phase shift of the third harmonic and adding series reactive element to the load network, a free design parameter can be defined and the design space of the load network parameters are expanded. The design equations of the idealized waveforms and the optimum values of the load network components are derived in detail, and the performance of the peak drain voltage, maximum operating frequency, and power output capability can be improved. In addition, with the expanding space of load network, the generalized PC Class-E/F 3 structure exhibits broadband capability. A matching method with the real frequency technique (RFT) and the de-embedding technique is presented to design the optimal broadband matching network. To verify the validity of the proposed method, a broadband high-efficiency PA working from 1.7 to 2.6 GHz (fractional bandwidth of 42%) is designed. The experimental results of the fabricated PA present high-efficiency characteristics of 68.5%-81% drain efficiency and 62%-75.8% power-added efficiency with 38.8-40.5 dBm output power over the whole operation bandwidth.

This paper presents a 60 GHz highly efficient singlestage differential stacked Class-AB power amplifier (PA) with second harmonic control (HC) for short range applications using mm-wave radar. The circuit is realized in a 45nm partially depleted sillicon-on-insulator (PD-SOI) CMOS technology. Measurement results show that the power amplifier achieves a saturated output power (Psat) of 16.4dBm with a competitive maximum power-added efficiency (PAEmax) of 32% at 60 GHz. The output-referred 1-dB compression point (OP1dB) is 9.5 dBm. Furthermore, the circuit draws 40mA from a single 1.8V supply and the chip core size is 0.36mm $\times\,\,0.35$ mm.

A novel class-E power amplifier (PA) using a current-injection (CI) technique is presented in this letter. An auxiliary current source, which injects the current into the load during each turn-off period of switching transistors, is introduced into the conventional class-E PA. Without the need of impedance transforming or increasing of the supply voltage, the proposed PA provides a new method to increase the output power. The proposed circuit is fabricated in a Taiwan Semiconductor Manufacturing Company’s (TSMC’s) 65-nm low power (LP) CMOS process. Measurement results show that the output power of the injected circuit reaches up to 14.12 dBm with a drain efficiency of 41% at 1.8 GHz. The output power improves more than 3 dB compared to the conventional class-E PA without CI.

In this article, we report the test strategy and the results obtained from measurements of a CMOS integrated power amplifier. The power amplifier was designed to optimally-drive an inductive link u...

This article presents a novel architecture of load-modulated balanced amplifier (LMBA) with a unique load-modulation characteristic different from any existing LMBAs and Doherty power amplifiers (DPAs), which is named pseudo-Doherty LMBA (PD-LMBA). Based on a special combination of control amplifier (carrier) and balanced amplifier (peaking) together with proper phase and amplitude controls, an optimal load-modulation behavior can be achieved for PD-LMBA, leading to maximized efficiency over extended power back-off range. More importantly, the efficiency optimization can be achieved with only a static setting of phase offset at a given frequency, which greatly simplifies the complexity for phase control. Furthermore, the cooperations of the carrier and peaking amplifiers in PD-LMBA are fully decoupled, thus lifting the fundamental bandwidth barrier imposed on the Doherty-based active load modulation. Upon theoretical proof of these discoveries, a wideband RF-input PD-LMBA is physically developed using the GaN technology for experimental demonstration. The prototype achieves a highly efficient performance from 1.5 to 2.7 GHz, e.g., 58%–72% of efficiency at 42.5-dBm peak power and 47%–58% at 10-dB output back-off (OBO). When stimulated by a 10-MHz long term evolution (LTE) signal with a 9.5-dB peak-to-average power ratio (PAPR), the developed PD-LMBA achieves an efficiency of 44%–53% over the entire bandwidth at an average output power of around 33 dBm.

A radio frequency (RF) 3-bit digital power amplifier (DPA) is described in this paper. It consists of three RF amplifiers connected at their outputs with a transmission line (TL) network. The three amplifiers are designed for different output powers (POUT). The TL network allows them to load-pull one other to achieve eight different amplitude states by alternatively enabling and disabling the amplifiers via their gate bias. A prototype was designed in the National Instruments' Microwave Office (MWO) for 500 MHz with the aid of a genetic algorithm to optimize the TL network for all seven active (on-) states. The optimizer efficiencies goals were based on data derived from load-pull simulation. The POUT goals were based on a 1 Vrms step-size. In simulation, ≥50% efficiency was achieved at all on-states with 29.7 dBm peak POUT. A practical prototype based on the simulation achieved an efficiency of ≥40% over all seven on-states. A peak POUT of 28.9 dBm was achieved, with the lowest state at 22.4 dBm.

A balanced-to-Doherty (B2D) mode-reconfigurable power amplifier (PA) is presented in this article, which is endowed with a unique capability of maintaining high linearity and high efficiency against load mismatch. The Doherty operation of this PA is based on a new Doherty PA (DPA) architecture configured from an ideal balanced amplifier, named quasi-balanced DPA (QB-DPA). This article, for the first time, analytically proves that the QB-DPA is functionally equivalent to a standard DPA. Most importantly, this new discovery enables PA reconfiguration between the Doherty and balanced modes. With the tunability implemented using a silicon-on-insulator (SOI)-based single-pole-double-throw (SPDT) switch, a reconfigurable B2D PA prototype using GaN technology is demonstrated at 3.5 GHz, exhibiting the state-of-the-art linear DPA performance in the nominal 50- $\Omega $ load condition. Specifically, the Doherty mode achieves a continuous-wave measurement efficiency of 70% and 54.5% at the maximum output power of 41.9 dBm and 6-dB power back-off, respectively. In the modulated long-term evolution (LTE) evaluation, the DPA exhibits −37-dB adjacent channel power leakage (ACPR) and 2.36% error vector magnitude (EVM) at the maximum rated power of 34.5 dBm while achieving a 42.4% efficiency. It is experimentally demonstrated that the Doherty (QB-DPA) mode is well resistant to load mismatch with high efficiency across a majority portion of the 2: 1 voltage standing wave ratio (VSWR) circle, while the combination of Doherty and balanced modes can ensure a constantly linear performance of the B2D PA (e.g., 2.2%-5% of EVM) under the entire mismatch condition.

A high efficiency multi-mode class-E outphasing RF power amplifier (PA) with a passive combining circuit is presented. The multi-mode PA combines multiple class-E amplifier branches and can work in different configurations. The PA improves efficiency at lower power levels by switching ‘on’ and ‘off’ individual branches in a static or dynamic manner and using Efficiency Enhancement Circuit (EEC). The proposed power amplifier is designed in 45nm CMOS technology. The PA delivers 31.6 dBm peak output power at 2.4 GHz with 49.2% drain efficiency in high power single level mode. With 64-QAM long-term evolution (LTE) signal with 10 MHz and 20 MHz bandwidth, −57 dBc and −53 dBc adjacent channel power ratio (ACPR) are obtained in single level outphasing (SLO) mode after digital pre-distortion (DPD). 25% and 33% average drain efficiency are achieved with LTE signal with 6 dB peak-to-average power ratio (PAPR) in single level outphasing and asymmetric multilevel outphasing (AMO) mode, respectively. The PA satisfies the spectral mask requirement of 802.11g WLAN signal with high margin. Error vector magnitude (EVM) of 1.1% (−39.36 dB) is obtained from the PA in single level outphasing high power mode after DPD with 64-QAM LTE signal with 10 MHz bandwidth.

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

In this paper, in-band continuous mode transferring (CMT) method is presented for designing broadband Doherty power amplifier (DPA). Specifically, transferable continuous mode, transferring between class-J continuum to class-F-1 continuum, is introduced into DPA at output back-off (OBO) power level for improving bandwidth and efficiency. For validation, a broadband DPA with operation mode transferring from continuous class-J to continuous class-F-1 is designed, fabricated and measured. Experimental results show the drain efficiencies (DEs) of the fabricated DPA are 46.3%-57.7% and 58.4%-69.1% at 6 dB OBO and peaking power levels over 1.7-2.6 GHz. The saturation power of this DPA is 43.1-45.2 dBm with a gain of 9.1-11.2 dB in the interested band. Furthermore, when the fabricated DPA is stimulated by a 20 MHz wideband signal with a peak-to-average power ratio (PAPR) of 7.05 dB at 2.4 GHz, the measured average power is 36.5 dBm with an average DE of 45.7%, and the measured adjacent channel leakage ratios (ACLRs) are -31.9 dBc and -50.4 dBc before and after DPD technique, respectively.

Unlike conventional conception that power amplifier and filter are regarded as two separate components and designed separately, this paper presents a high efficiency power amplifier with filtering capability, which is called filtering power amplifier. The proposed power amplifier integrates a bandpass filter as output matching network so that entire size is reduced to some extent. The filter will play the role of filtering and impedance matching simultaneously, and thus high-order harmonics are suppressed for output of the filtering power amplifier. For demonstration, an example of filtering power amplifier was designed, fabricated and measured. The measurement shows that it is featured by highly-selective bandpass response and good out-of-band performance. As high as 46.2 dB suppression can be achieved and extended over the forth-order harmonic. The example also retains the advantages of high efficiency and output power. The maximum output power can reach 40.5 dBm, and the maximum power-added efficiency is as high as 62%.

This letter presents a novel compact power amplifier (PA) using the transformer-based quadrature coupler as the power splitter and combiner to achieve a large output power and high gain for automotive radar application. Compared with conventional transmission-line-based power splitter and combiner, the transformer-based quadrature coupler offers a low loss, wide bandwidth, and compact footprint. As a proof of concept, a 77-GHz PA is designed and implemented in a 65-nm CMOS technology. The measured small-signal power gain is 26.4 dB with a 8.5-GHz 3-dB bandwidth from 74 to 82.5 GHz. The measured $P_{\text {sat}}$ , OP1 dB, and peak power added efficiency (PAE) are 15.82, 11.5 dBm, and 15.9%, respectively. In addition, the saturated output power at 77 GHz is 16.5 dBm at −40 °C and still remains as high as 13.5 dBm at 130 °C, which enables the automotive application. The proposed PA occupies a core area of $270\,\,\mu \text{m}\,\,\times 530\,\,\mu \text{m}$ and the total dc power consumption is 240 mW.

A low power consumption linear power amplifier (PA) for Internet of Things (IoT) application is presented. An analog pre-distorter (APD) is integrated to the PA, which consists of an active inducto...

This article proposes a unified theory on power combining with a continuum of load modulation (LM) ratios. Two well-known power amplifier (PA) techniques, Doherty and traveling-wave amplifiers, are the two extreme examples within this continuum, yielding full and zero LMs, respectively. Based on this theory, a power-combining technique is proposed, which optimizes efficiency and bandwidth at a certain power backoff (BO) level, which is often in between the two well-known architectures. As a demonstration, a PA with an LM ratio of 1.4 is designed. It achieves a peak output power of 49.3±0.5 dBm and 47%–60% drain efficiency at 8-dB power BO over 2.6–3.8 GHz. The linearizability and practical usefulness of this PA are demonstrated through linearized-modulated measurements.

This paper presents a 30-to-40 GHz 2-stage power amplifier (PA) for 5G applications. Transformers are used to achieve a broad input, output and interstage matching while occupying a compact size. The neutralization technique is used to boost the power gain and improve stability of PA. According to the simulation results, the power amplifier achieves an output 1dB compression point (OP1dB) of 14.9 dBm and a saturated output power of 17.4 dBm with a peak power added efficiency (PAE) of 39% at 35 GHz. The gain is larger than 30 dB from 30–40 GHz. Implemented in a 0.13-µm SiGe BiCMOS process, the overall chip size is 0.46 mm2 including all RF and DC pads.

In this paper, a dual-band power amplifier (PA) fabricated in 0.15-μm GaAs pHEMT process is presented. The concept of the optimal matching contour is used in the matching network design to minimize the loss in both operating frequency bands. Thus, this PA achieves good power performance in both frequency bands. The measured results of small-signal gain are 20/12 dB at 28/39 GHz, respectively. The saturated output power (P sat ) is 21.9/22.7 dBm, the peak power-added efficiency (PAE max ) is 28.9/32.6%, and the OP 1dB and corresponding PAE (PAE 1dB ) are 21.8/22.6 dBm and 28/32% at 28/39 GHz, respectively.

This paper introduces a Ka-band power amplifier with 14.2-dBm Power. Multiple transformer-based matching networks are introduced to realize broadband matching and high power output. A 26–35GHz power amplifier is realized in a standard 65 nm CMOS process. The amplifier achieves 16.8 dB small signal gain, 14.2-dBm output 3-dB compression point (P3dB), and 11.8-dBm output 1-dB compression point (P1dB). The simulated input and output return losses within the operation band are −6dB and −9dB in the worst case, respectively.

A 28-GHz power amplifier (PA) with adaptive cross feedback (ACF) is presented. The ACF is employed by an adaptively controllable RC-feedback circuit from the source to the opposite drain nodes of the common-gate (CG) stages in a differential cascode amplifier. The proposed ACF makes the PA stable even with large power transistors. It also linearizes the PA by decreasing the feedback adaptively at high powers which improves amplitude distortion (AM-AM) and power-added efficiency (PAE) as well as the saturation power (P Sat ). The proposed PA is implemented with a 28-nm bulk CMOS process with a 0.144 um2core chip area. It is shown that the ACF increases P Sat , peak PAE, and output 1-dB gain compression point (OP 1dB ) from 20.1 dBm to 20.4 dBm, 34% to 37.2%, and 17.4 dBm to 18.2 dBm, respectively at 28.5 GHz. The proposed PA shows a 28-dB peak gain at 28.6 GHz with 26.8 GHz to 30.8 GHz (14.0%) 3-dB gain bandwidth, which is the highest P Sat and gain among the reported Ka-band bulk CMOS PAs.

International audience; In order to improve amplifiers’ power gain for a close to fmax operation, a methodology to size the embedding of any active two port is described and then applied to the design of a single-stage amplifier as a proof of concept. The 184 GHz measured 28 nm FD-SOI CMOS amplifier presents a power gain of 7.6 dB, a bandwidth of 20 GHz, a Psat of -3.7 dBm and a peak PAE of 4.2 % for a power consumption of 5.1 mW.

In this paper, new parallel plate coupler based Doherty power amplifier design for 5G NR handset applications is proposed. Based on simplified output network, the proposed Doherty power amplifier is analyzed. The proposed Doherty power amplifier is demonstrated experimentally with GaAs-HBT. A PAE of 42.0% and a NR ACLR of −38.8 dBc at an average output power of 27.8 dBm are measured at 3.75 GHz under 5G NR 100 MHz, DFT-s-OFDM, QPSK operation, and the efficiency improvement from Class AB operation achieves 11%. Moreover, the proposed Doherty power amplifier maintains more than 35.0% efficiency with a NR ACLR of below −35.2 dBc from 3.35 GHz to 4.15 GHz, corresponding to 5G NR Band n77.

This paper presents a switchless bidirectional power amplifier-low noise amplifier (PA-LNA) in 90-nm CMOS process for millimeter-wave (mm-wave) phased-array front-end chip. This PA-LNA uses current-type transformer (TF) as a bidirectional matching network for PA and LNA inputs/outputs without using lossy T/R switches. As a side benefit, avoiding the use of the T/R switches not only saves the chip area, but also prevents performance degradation in PA and LNA modes. The proposed PA-LNA achieves peak small-signal gain of 18.3 dB and 17.6 dB in PA and LNA mode, respectively. In the PA mode, it achieves the measured peak saturated output power (Psat) of 15.1 dBm with 29 % peak power-added efficiency (PAE MAX ) and 13.3 dBm peak 1-dB output power (OP 1dB ) at 33 GHz, while LNA mode achieves minimum noise figure (NF) of 4.7 dB at 36 GHz. The reverse isolation in both modes is better than 43 dB. The core size without pads is 0.21 mm2.

This paper presents a D-band linear power amplifier (PA) with high gain, high output power and high efficiency using CMOS 45nm RFSOI process. An 8-way (4-way differential) power-combining technique is implemented to increase the power amplifier linearity and output power. To decrease the loss of the output combiner, the first stage output power combiner is designed as part of the power matching network. The PA achieves a small-signal gain of 22.2-24 dB with 1-1.2 V supply at 140 GHz, respectively. The measured P1dB and Psat are 14.2 dBm and 17.5 dBm with 1.2 V supply, at 140 GHz. The maximum PAE is 13.4%. The 140 GHz PA operates from 130 to 150 GHz with an OP1dB > 13 dBm, which is ideal for high-speed wireless communication systems.

A low-loss compact-size edge-coupled 4-way balun that simultaneously converts a single-ended signal to two pairs of differential signals is proposed. A 2-way combined differential power amplifier (PA) operating at 60 GHz is designed with the proposed 4-way balun in 0.18 µm SiGe technology. It consists of two identical 3-stage differential unit PA cells, which is internally transformer-coupled and capacitive-neutralized. The designed PA achieves a small signal 3-dB bandwidth from 43 to 67 GHz, with a peak gain of 20 dB. The 1 dB power compression point (P1dB) is 21.6 dBm and saturated output power (P SAT ) is 22.7 dBm, with power added efficiency of 23.5% at PldB and 27.7% at PSAT. The modulation test shows that the PA can deliver 18.1 / 15.2 dBm average output power with −14.5 / −21.8 dB error-vector magnitude when operating with IEEE 802.11ad modulation coding schemes (MCS) 9 / IEEE 802.11ad MCS 12 signals.

This paper presents optimal carrier and peaking drain voltages to preserve the output power capability and back-off level of Doherty power amplifiers (PAs) operating for non-optimal loads. These voltages are theoretically obtained from back-off and full power conditions. A performance comparison between simulations of a conventional Doherty and the proposed load insensitive version is presented, showing that the introduced theory can be very advantageous for operation under load varying scenarios. A 3.6 GHz load insensitive Doherty PA was designed, implemented and measured for loads distributed inside a 2.0 voltage standing wave ratio circle. These measurements validated the introduced theory, showing an almost constant maximum output power (42.9 – 43.2 dBm), and a back-off level varying between 5.0 dB and 6.2 dB. The 6-dB output power back-off efficiency varies between 42 % and 53 %, in which the highest degradation corresponds to loads with high imaginary parts.

In this paper, we present a GaN-based f T -doubler topology using a novel integrated layout. This compact approach allows for minimizing the layout-induced parasitic effects and, as a result, enables operation at millimeter-wave frequencies. In order to demonstrate the broadband potential of the f T -doubler topology employing the novel integrated layout approach, a 3-stage amplifier is reported. It can provide more than 10 dB of small-signal gain over a 28-90-GHz band, which is equivalent to a fractional operating bandwidth of 105 % (1.68 octaves). In large-signal operation, this MMIC can deliver from 14.5 dBm to 20.6 dBm of output power over a 30-90-GHz band. This circuit is able to provide a full coverage of the Q-band (33–50 GHz), U-band (40–60 GHz), V-band (50–75 GHz), E-band (60–90 GHz), and almost the entire Ka-band (26.5-40 GHz). To the best of our knowledge, this is the first demonstration of an FET-based integrated f T -doubler circuit operating at such high frequencies.

This paper presents the design of a single-chip, 25-Gb/s optical receiver comprising of a front-end amplifier, a clock and data recovery (CDR), and a 1:4 demultiplexer. Incorporating with an integrating-type receiver front end, a new baud-rate CDR is proposed to achieve both high sensitivity and highly energy-efficient operations. Compared to conventional 2 $\times $ oversampling CDRs that require edge samples for timing adjustment, the baud rate CDR reduces the number of sampling phases by half to save both area and power consumption. In addition, a hybrid loop filter consisting of analog decimation and digital postprocessing is proposed. It greatly relaxes the speed requirement of an all-digital loop filter while keeping the flexibility of a programmable loop bandwidth. By applying a pseudo random bit sequence (PRBS) 231−1 test pattern and using a photo detector whose responsivity is 0.53 A/W, the input sensitivities of the optical receiver at 20 and 25 Gb/s operations are about −13.8 and −8.7 dBm respectively, for a bit error rate (BER) of less than 10−12. The recovered data jitter at the demultiplexer output is about 1.7-ps rms. The measured jitter tolerance (JTOL) exceeds the mask defined by the IEEE 802.3ba standard. Implemented in a 40-nm CMOS process, the chip area is only 0.09 mm2. The energy efficiency of the entire receiver is 2.1 pJ/bit at 25-Gb/s operation.

Outphasing Class-E power amplifiers (OEPAs) using isolating power combiners and an inverse cosine signal component separator are inherently linear but suffer from low efficiency at power back-off. For high efficiency both at maximum output power and at power back-off, non-isolating power combiners are required. In this brief the linearity of OEPAs using non-isolating power combiners is studied theoretically and validated by measurement of a 1.8 GHz 20 dBm OEPA implemented in a standard 65-nm CMOS technology using an off-chip transmission-line-based combiner. The developed theoretical model for the linearity is then employed to define digital pre-distortion (DPD) parameters for the implemented OEPA. Using this theory-based DPD and without any AM/AM and AM/PM characterizations, –31 dB RMS EVM level and below –30 dB ACLR were measured for a 13.1 dBm 6.25 MHz 30 Mbit/s 7 dB PAPR 64QAM signal with 41.8% drain efficiency and 33.6% power added efficiency.

The conventional Doherty output combiner limits the bandwidth of operation in the asymmetric Doherty power amplifiers (DPAs). In this study, an output combiner that is designed using a harmonic-tuned continuum mode active load modulation technique is proposed with the main target of extending the bandwidth of operation in the asymmetric DPAs. Through this methodology, design equations are derived and multiple harmonic impedance solutions are provided. This offers greater freedom for designing the output combiner of the asymmetric DPA which consists of the impedance inverting network and the impedance transforming network. Moreover, enhancements in the efficiencies at back-off and saturation power levels are made possible. The efficacy of the design strategy is demonstrated by the realised broadband asymmetric DPA prototype working within the band of 1.4-2.45 GHz. The experimental results have shown 54.55% bandwidth of operation, accounting for about 0.95-12.55% increment in bandwidth as compared with some recently published DPAs in the literature. Substantially, drain efficiencies within 35.5-52% at 6 dB output power back-off level and 47.5-64.2% at peaking power level are also recorded from the experiments. The maximum output power and gain are recorded at 43.52 dBm and 13.03 dB, respectively.

This paper presents the design and optimization of an $E$ -band power amplifier (PA) implemented in Intel’s 22FFL FinFET process. Layout optimization and characterization of the PA unit cell yielding optimal millimeter-wave (mmW) performance of the active device are described. A holistic optimization methodology is also presented which co-optimizes efficiency of the active devices and passive networks by incorporating passive losses earlier in the design process. The measured PA achieves a peak gain of 18.6 dB with a 3-dB bandwidth of 62–86 GHz (24 GHz). At 75 GHz, the measured $P_{\mathrm {sat}}$ , OP1dB, and peak power added efficiency (PAE) are +12.6 dBm, +5.7 dBm, and 26.3%, respectively. The PA can amplify a 6-Gb/s 16-QAM signal at an average $P_{\mathrm {out}}$ of +5 dBm with a PAE of 10% and −26-dB EVM(rms) and a 9-Gb/s 64-QAM signal at an average $P_{\mathrm {out}}$ of +1.3 dBm with a PAE of 5% and −28.3-dB EVM(rms). The compact layout of the PA yields a core area of 0.054 mm2, enabling compact integration.

In this paper, a new digitally driven two input continuous mode Doherty power amplifier (DPA) architecture is proposed along with an analytical-based generic output combiner network design methodology. The load combiner provides the designer a choice to meet the optimum performance for any arbitrary back-off as well as for saturation. The PA's performance is further optimized with digital input splitting. To verify the proposed theory, a 20-W symmetrical continuous mode DPA is designed using 10-W GaN HEMTs. The proposed amplifier shows a drain efficiency between 56.0% and 75.4% at 41.4-44.6 dBm saturation power and between 45% and 56.5% at 35.7-38.5 dBm output power corresponding to 6-dB back-off. This performance is achieved over the band from 1.25 to 2.3 GHz that corresponds to 59.15% fractional bandwidth. The proposed hybrid analog/digital continuous mode DPA prototype is implemented using field-programmable gate array (FPGA)/DSP platform and qualifies the spectral mask when excited by a modulated long term evolution signal along with digital predistortion.