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Start Over Descriptor "Large designs" Topic algorithms
2 results on '"Large designs"'

1. Graph based isomorph-free generation of two-level regular fractional factorial designs

Author

Shrivastava, Abhishek K. and Ding, Yu

Subjects
*ISOMORPHISM (Mathematics), *FACTORIAL experiment designs, *AUTOMORPHISMS, *BIPARTITE graphs, *SUBGROUP growth, *ALGORITHMS
Abstract

Abstract: We provide a new necessary and sufficient check for testing the isomorphism of two 2-level regular fractional factorial designs. The approach is based on modeling fractional factorial designs as bipartite graphs. We employ an efficient canonical graph labeling approach to compare two designs for isomorphism. We then improve upon the existing non-isomorphic fractional factorial design generation algorithm by reducing the number of candidate designs from which isomorphs need to be removed. Not only does our method generate non-isomorphic designs much faster, it is also able to generate designs with run sizes of 2048 and 4096 runs, which were not generated by the existing methods. [Copyright &y& Elsevier]

Published
2010
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2. XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests

Author

Trinadh, A.S., Potluri, S., Balachandran, S., Babu, Ch.S., Kamakoti, V.

Subjects
Algorithms, Design for testability, Filling, Flip flop circuits, Integrated circuit testing, Testing, Capture-power reductions, Large designs, Peak capture-power, Peak power minimizations, Scan-based testing, Test power reduction, Test vector ordering, Timing failures, Electric losses
Abstract

Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failures. Since test power dissipation is typically higher than functional power, test peak power minimization becomes very important in order to avoid test induced timing failures. Test cubes for large designs are usually dominated by don't care bits, making X-leveraging algorithms promising for test power reduction. In this paper, we show that X-bit statistics can be used to reorder test vectors on scan based architectures realized using toggle-masking flip flops. Based on this, the paper also presents an algorithm namely balanced X-filling that when applied to ITC'99 circuits, reduced the peak capture power by 7.4% on the average and 40.3% in the best case. Additionally XStat improved the running time for Test Vector Ordering and X-filling phases compared to the best known techniques. Copyright � 2014 American Scientific Publishers

Published
2014

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