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Loss-less data compression becomes the need of the hour for effective data compression and computation in VLSI test vector generation and testing in addition to hardware AI/ML computations. Golomb code is one of the effective technique for lossless data compression and it becomes valid only when the divisor can be expressed as power of two. This work aims to increase compression ratio by further encoding the unary part of the Golomb Rice (GR) code so as to decrease the amount of bits used, it mainly focuses on optimizing the hardware for encoding side. The algorithm was developed and coded in Verilog and simulated using Modelsim. This code was then synthesised in Cadence Encounter RTL Synthesiser. The modifications carried out show around 6% to 19% reduction in bits used for a linearly distributed data set. Worst-case delays have been reduced by 3% to 8%. Area reduction varies from 22% to 36% for different methods. Simulation for Power consumption shows nearly 7% reduction in switching power. This ideally suggest the usage of Golomb Rice coding technique for test vector compression and data computation for multiple data types, which should ideally have a geometrical distribution., Competing Interests: The authors have declared that no competing interests exist., (Copyright: © 2024 Sakthivel et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.)

The paper proposes a nonlinear controller called dual super-twisting sliding mode command (DSTSMC) for controlling and regulating the rotor side converter (RSC) of multi-rotor wind power systems that use doubly-fed induction generators. It was proposed that this controller be developed as an alternative to the direct power control (DPC), which makes use of a pulse width modulation (PWM) strategy to regulate the RSC's functioning. Overcoming the power/current quality issue with the proposed technique (DPC-DSTSMC-PWM) is characterized by great robustness and excellent performance. The designed strategy was contrasted with the standard method of control and other methods already in use. So, the unique proposed control strategy's robustness, performance, efficiency, and efficacy in enhancing system characteristics were tested and validated in Matlab/Simulink. In both tests, the proposed method resulted in significant improvements, reducing active power ripples by 83.33%, 57.14%, and 48.57% in the proposed tests. When compared with the traditional regulation method, the reduction rates of reactive power ripples are 64.06%, 52.47%, and 68.7% in the tests. However, in contrast to the conventional method, the proposed tests showed a decrease of between 72.46%, 50%, and 76.22% in the value of total harmonic distortion (THD) of the provided currents. These ratios show how effective the proposed plan is in ameliorating and enhancing aspects of the energy system. [ABSTRACT FROM AUTHOR]

Advanced power converters are being developed due to the latest developments in power electronics switches. The matrix converter (MC) assessment is the product of this drastic growth. MC is a bidirectional power flow device with a single-step energy conversion mechanism that operates at variable voltage and frequency. The main drawback of MC is the presence of harmonics due to power electronic device switching. A lot of research has been done to decrease the harmonics content present in the MC, but it is restricted to a certain level only. To overcome this limit, the harmonics are minimized in the MC by incorporating soft computing controllers. This article presents particle swarm optimization (PSO), modified PSO (MPSO), and modified hybrid PSO (MHPSO) based controllers for different loads. The proposed MC with a soft computing controller reduces the harmonics by selecting suitable switching pulses for every sample. The simulations are made using the MATLAB/Simulink environment. The results of the proposed MHPSO controller reduce the THD value from 8.654 with a PSO approach to 7.536 in the presence of nonlinear loads. [ABSTRACT FROM AUTHOR]

The voltage quality (VQ) index has become a significant measure of recent power system stability. The integration of photovoltaic (PV) systems plus smart home loads (SHLs) at low voltage levels (LVLs) has resulted in various issues such as harmonics rise and voltage instabilities as a result of faults and systems nonlinearity. In this work, a dynamic voltage resistor (DVR) is implemented to enhance VQ, and its dynamic performance hinges on its control system ability. To enhance the DVR's control system, for surpassing nonstandard voltage with a quick response and harmonics reduction at LVL under harsh operating events, an optimal controller design using the Harris Hawks algorithm (HHA) is proposed. To verify the value of the suggested solution, the hard operating events (voltage sag, voltage swell, fluctuating voltage, and imbalanced voltage) are examined and assessed. To show the effectiveness of the HHA technique, a comparison of the % total harmonic distortion (THD) reductions achieved by the suggested and conventional controllers of DVR is conducted for the scenarios under study. Moreover, the suggested controller stability is analyzed and assessed using Lyapunov's function. The benefits of the optimized controller system are inferred from the results, including their robustness, simplicity, efficient harmonic rejection, minimal tracking error, quick response, and sinusoidal reference track. The results of the simulation show that the DVR's optimized controller is efficient and effective in maintaining a voltage at the needed level with low THD, safeguarding the sensitive load as expected, and showing a noticeable improvement in voltage waveforms. The mathematical modeling of HHA, PV system, DVR, and SHLs are all verified using MATLAB\Simulink. [ABSTRACT FROM AUTHOR]

This paper proposes the use of two recent optimization techniques, called the Local Unimodal Sampling (LUS) and the Spotted Hyena Optimizer (SHO), to optimally tune cascaded PID controller designed while controlling the speed and reducing the torque ripples of the switched reluctance motor. The proposed implementation of these algorithms has the advantage of better convergence and lower computational efforts when compared to other optimization techniques. To demonstrate the effectiveness of the proposed cascaded PID controller using LUS and SHO, they are compared to other controller designs present in previous literature, specifically the cascaded fractional-order PID (FOPID) controller. Results show that the PID controller is more superior to the FOPID controller and that the SHO-based cascaded PID controller leads to less current and torque ripples with better speed response. The study is implemented at different loading conditions. The results are presented in the form of a time-domain simulation conducted via MATLAB/SIMULINK. [ABSTRACT FROM AUTHOR]