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High-speed data communication is becoming essential for many applications, including satellite communication. The security algorithms associated with the communication of information are also required to have high-speed for coping up with the communication speed. Moreover, the Authenticated Encryption (AE) algorithms provide high-speed communication and security services include data encryption, authentication, and integrity. The AE algorithms are available with serial and parallel architectures; among them, the Galois Counter Mode (GCM) algorithm has a parallel architecture. The Synthetic Initialization Vector (SIV) mode in the AES-GCM-SIV algorithm provides the nonce misuse protection using the GCM algorithm. Besides, reduced data throughput is provided using the AES-GCM-SIV algorithm as compared to the AES-GCM algorithm. This work introduced a parallel algorithm with re-keying and randomization of the initialization vector for high data throughput, nonce misuse protection, and side-channel attack protection. The implementation of the proposed algorithm is performed on Field Programmable Gate Array (FPGA) and it’s compared with the FPGA implementations of AES-GCM, AES-GCM-SIV, and recently introduced algorithms. The optimization of the proposed algorithm and security analysis is presented for space application using different optimizations and a combination of optimizations.

The increase in the flow of information and high-speed communication has compelled researchers to use satellite networks for different applications. The satellite networks comprise different satellites in different orbits that require the data security algorithms for the providing security and privacy of consumers' information. The data security primarily consists of data confidentiality service, which is provided by data encryption algorithms. The data encryption algorithm for example AES algorithm is utilized in many applications, including the satellites. The challenges for AES algorithm utilization in satellite applications are high-speed computation, lightweight implementation, and catering the radiations in the space environment. In this work, optimizations are proposed for coping with the challenges in a data encryption algorithm for the space environment. Also, the high-throughput optimization for the AES algorithm is realized on FPGA, and it equated with previous work. Moreover, the recent security attacks, for instance the nonce misuse attack is challenging for the security of encryption algorithms. The high-throughput optimized encryption algorithm protects against the recent attacks by the modifications in the AES algorithm. Moreover, the security analysis is provided against the latest attacks for the validation of high-throughput optimizations.

Authenticity and integrity of data are two primary and critical information security services, which are generally provided together through data authentication algorithms in many of the modern-day communication applications. Cipher based Message Authentication Code (CMAC) is one of the widely used authentication algorithms and also recommended for space applications. Besides, CMAC has some limitations, such as security vulnerabilities and serial architecture. On the other hand, due to the advent and growth of Space Information Network (SIN) and the trend of miniaturization of satellites, lightweight, fast, high data rate supported algorithms are desired nowadays for satellite applications. This paper presents a new lightweight authentication algorithm which removes the shortcomings of the CMAC algorithm to provide more efficient and secure data authentication. Experimental results validate the performance superiority of the proposed algorithm over the CMAC algorithm.

The need for high-speed communication has led the research towards designing parallel architectural algorithms for data security. The utilization of the Advanced Encryption Standard in Counter mode (AES-CTR) in cipher-based Authenticated Encryption (AE) algorithms has realized the importance of a unique Initialization Vector (IV) for data security. The Synthetic Initialization Vector (SIV) is an improvement of a generic IV used in the AES-CTR algorithm for nonce misuse and key wrapping attacks. In this work, we have proposed a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code with SIV Algorithm (PCMAC-SIV). The PCMAC-SIV AE algorithm is consists of an AES-CTR algorithm and parallel implementation of the Cipher-based Message Authentication Code (CMAC) algorithm with SIV algorithm for avoiding nonce misuse. The proposed algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the proposed algorithm implementation with the AES-GCM -SIV algorithm. The experimental results show that the throughput of the proposed algorithm show higher throughput of 1.629 Gbps for single plaintext and 13.06 Gbps for eight plaintexts.

Advance Encryption Standard (AES) is an algorithm widely used for encryption, authentication, authenticated encryption as well as in security protocols for providing security services in many modern-day applications. The primary reasons for the extensive use of AES are its stronger security and faster speed than its competitors. In the AES algorithm, different keys derived from the main key are used in encryption rounds, to provide strength to the security of the algorithm. However, in standard AES key expansion algorithm, the sub-keys are derived sequentially, that is one after other. This dependence on the previous sub-key has two problems. Firstly, the key generation cannot be parallelized, secondly, if any single sub-key is known to the attacker, all the other sub-keys, including master key, can be extracted. Also, Differential Power Analysis attack is known effective on standard AES key schedule. In this paper, we proposed a new key parallelized expansion algorithm for AES. The proposed algorithm removes the dependence on other sub-keys to provide faster speed and enhanced security. The proposed algorithm has been implemented in MATLAB software and on FPGA. The results of implementation validate that the computational efficiency of the proposed algorithm is superior to standard AES Key expansion.

The growing number of threats and attacks on communication systems has encouraged researchers to identify methods for providing security for data communication. Besides the encryption and authentication algorithms provide data security services for communication systems. However, the recent attacks on communication systems reveal that the attacks utilize the analysis of plaintext/ciphertext to breach the security of communication systems. Therefore, the plaintext should be randomized to prevent correlation between ciphertext. In this work, an algorithm is proposed for increasing ciphertext randomness in Parallel Cipher-based Message Authentication Code (PCMAC) Algorithm. The proposed algorithm utilizes the high throughput of PCMAC authenticated encryption algorithm for providing high throughput and more randomized ciphertext. The proposed algorithm is implemented for generation of Initialization Vector (IV) using the GEFFE generator and right shift operation for creating randomness in the ciphertext. The comparisons result show that the proposed implementation is more randomized as compared to the previous implementation.

In the present, the use of communication systems is not a luxury but a necessity. The growing reliance on technology and its uses in all walk of life have realized the need for robust security systems for communication. The Advanced Encryption Standard (AES) in Counter (CTR) mode support high-speed operations due to parallel architecture and having no feedback or chaining mode. The AES-CTR algorithm involves encryption of Initialization Vector (IV) with a secret key for generation of ciphertext. A unique IV is required in the AES-CTR algorithm for maintaining the secrecy of data and generation of unique ciphertext. Previously, the researchers utilized the GEFFE generator for generation of IV as well as right-shift and increment operation were used for IV generation. The combination of these two algorithms can provide an increase in ciphertext randomness as compared to using it individually. In this work, we have proposed an IV generation algorithm based on the GEFFE generator and right-shift and increment operation for the AES-CTR algorithm. The proposed algorithm generates an increase in randomness for data security. The comparative analysis with other techniques shows that our algorithm has better in performance and security.

The advancements in communication technology have evolved the algorithms used for communication security. Recently, the Authenticated Encryption (AE) algorithms are employed for providing security services for data communication. The Advanced Encryption Standard in Counter mode (AES-CTR) with Cipher-block Chaining Message authentication code (AES-CCM) algorithm is used for providing the data security for various applications. But the AES-CCM algorithm provides limited throughput for data communication. Therefore, in this work, new architecture is proposed for increase in throughput for provision of data security for communication application. The proposed algorithm uses the AES-CTR algorithm with the Cipher-based Message Authentication Code (CMAC) algorithm for providing AE. The proposed AE algorithm is implemented on FPGA and it’s compared with the FPGA implementation of AES-CCM algorithm. The comparison results of the proposed algorithm and the AES-CCM algorithm shows that the proposed algorithm provides improvement in the consumption of the area, processing time, and throughput. The implementation of proposed AES-CMAC AE algorithm on FPGA provides a throughput of 4.30 Gbps.

The evolution in digital communication technology has provoked the need for providing efficient security services for communication. The data security services majorly includes; confidentiality, authenticity, and integrity services. The Authenticated Encryption (AE) algorithm provides all these three services. Initially, AE algorithms were proposed with serial architecture. These AE algorithms are low throughput as compared to parallel architecture algorithms such as Galois Counter Mode (GCM) algorithm. In this work, we have presented a new AE algorithm with parallel architecture named as Parallel Cipher-based Message Authentication Code (PCMAC). The PCMAC AE algorithm is consists of Advanced Encryption Standard (AES) algorithm in Counter mode (CTR) and parallel implementation of the CMAC authentication algorithm. The proposed PCMAC algorithm is implemented on FPGA for showing its utility for high throughput applications. In this work, we compared the PCMAC AE algorithm implementation with the GCM AE algorithm implementation. The experimental results show that the throughput of PCMAC algorithm for pipelined implementation is 41.45 Gbps.

In communication systems, data encryption and authentication algorithms are utilized for secure communication. The utilization of encryption and authentication algorithms depends on the field of application and required level of security. Recently, researchers are working on encryption based authentication algorithms, as both services of encryption and authentication are utilized in highly secure systems such as satellite communication. The Cipher based Message Authentication Code (CMAC) finds its relevance in many applications. CMAC algorithm has been implemented previously on software and hardware. But by assessment of previous work on hardware implementation it seems that competence could be enhanced by efficiently utilizing hardware resources. In this paper, an improved and efficient hardware implementation of CMAC algorithm on FPGA is proposed for satellites application. Our results showed improvement in consumption of FPGA area and time utilization as compared to previous implementations.

In this era of information technology, information security is a major concern. To address the challenges of data security, cryptography is used for storage as well as for the communication of data. A cryptographic algorithm has two main performance characteristics: the ability to secure data against different attacks and the processing speed. An algorithm is considered secure if no attack exists to reveal the original contents without knowing the key. The strength of any secure encryption algorithm is, therefore, generally measured based on the difficulty to obtain the encryption key through cyber-attacks such as brute force. It is presumed that the bigger the key size, the more difficult it is for the attacker to compute the key. Consequently, increasing the key size generally increases the computational complexity and processing time of algorithms. As a result, an established assumption is the existence of a tradeoff and computational complexity. In this paper, we are presenting an alternate symmetric key encryption algorithm, which can easily avoid long and complex computation of conventional popular symmetric key encryption algorithms such as the Data Encryption Standards and the Advance Encryption Standard. We have shown that despite providing a higher level of security, one simplest software implementation of our algorithm is faster than some previously implemented conventional algorithms. Additionally, our algorithm also provides other advantages such as inherent data compression option and flexibility of choosing different complexity levels according to the need for different applications.