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With a goal of delay and power reduction in global buses, an air-gap technology for upper-layer interconnect is introduced. The fabrication process is discussed, utilizing ${h}$ -BN as an air-gap capping layer to enable large voids. The suitability of an air-gap technology for integration into the upper-layer back-end-of-line (BEOL) interconnect is evaluated in terms of the void ratio to the adjacent-line spacing. Electrical measurements show that adjacent-line capacitance is reduced by 50%. Mechanical reliability is ensured by Young’s modulus above BEOL requirement. Moisture uptake into air gaps is prevented using a hydrophobic capping layer. The integration of air gaps in global buses results in a 41% and 60% reduction in delay and crosstalk in the worst case switching scenario, based on parameters in the 14-nm technology node. It allows a 72% reduction in the energy-delay product with optimally designed repeaters. For the same delay, power consumption in an air-gapped global bus is reduced by requiring $4\times $ fewer repeaters. [ABSTRACT FROM AUTHOR]

To allow air-gaps with a large void size within a metal spacing, we propose the use of h-BN as an air-gap capping layer, which suspends the inter-metal dielectric in a CMOS back-end-of-line (BEOL) process. The fabrication process, based on the transfer of h-BN to seal air-gap regions, is discussed, including the use of Al2O3 on h-BN film for mechanical stability, and the consequence of thermal expansion coefficient mismatch in the materials introduced. A capacitance reduction of up to 50% is achieved through the large void size in the h-BN-capped air-gap technology. Demonstration of the proposed air-gap technology at $\mu $ m dimension for top-level metalization is presented. The compromise on Young’s modulus for a low effective- $\kappa $ is measured and benchmarked against typical values in low- $\kappa $ technology. [ABSTRACT FROM AUTHOR]