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This work proposes a low-power adaptive successive approximation ADC that operates in 12-bit and 8-bit resolution for data acquisition in biomedical system. A fully differential architecture and an energy-efficient switching scheme are employed. The modified switching operation allows the output voltage of the DAC capacitor array to approach the common mode voltage in order to reduce the offset voltage variation of the comparator. A test chip is implemented using a 0.18-µm CMOS process. The core area is 904×650μm2 The measurement results show that performance integrity and power efficiency are both significantly achieved in 12-bit resolution only. After the test using 1.8-V supply voltage, the SNDR is 65.59dB and ENOB is 10.62 bits. Using 200kS/s sampling rate, the ADC core consumption is 40.24μW and 18.63μW, for 12-bit and 8-bit case, respectively. [ABSTRACT FROM AUTHOR]

A novel scaling algorithm is proposed for the implementation of 2-D image scalar. The algorithm consists of a bilinear interpolation, a clamp filter, and a sharpening spatial filter. The bilinear interpolation algorithm is selected due to its having low complexity and high quality. The clamp and sharpening spatial filters are added as pre-filters to solve the blurring and aliasing effects produced by bilinear interpolation. Furthermore, an adaptive technology is used to enhance the effects of clamp and sharpening spatial filters. To reduce memory buffers and computing resources for the very large scale integration (VLSI) implementation, the clamp filter and sharpening spatial filters both convoluted by a 3\,\times\,3 matrix coefficient kernel are combined into a 5\,\times\,5 combined convolution filter. The bilinear interpolation is simplified by the co-operation and hardware sharing technique to reduce computing resource and hardware costs. The VLSI architecture in this paper can achieve 280 MHz with 9.28-K gate counts, and its chip area is 46 418 \mum^2 synthesized by a 0.13 \mum CMOS process. Compared with previous techniques, this paper not only reduces gate counts by more than 46.6% and power consumptions by 24.2%, but also improves average quality by over 0.42 dB. [ABSTRACT FROM AUTHOR]