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Gang bonding process using TCB (thermo-compression bonder) has been developed in recent years as one of the methods to mount advanced packages fast [1, 2]. In the gang bonding process, we can improve the throughput considerably by post-bonding multi pre-bonded chips at a time. However, when a conventional elastic film was used to reduce the variance of bonding load to each chip, we found that the position shift of the chips occurred by deformation of the film especially in narrow pitch chip bonding. In addition, it is difficult to supply enough heat for the solder joint, because the elastic film generally has low thermal conductivity and low heat resistance. In particular, heat capacity necessary for solder fusion is insufficient in the case of chip on wafer (CoW) using Si substrate. In this presentation, we will report about novel gang bonding head (GBH) that is able to reduce the position shift and has both of high thermal conductivity and low elasticity.

For improvement of the productivity and the cost reduction, FOWLP (fan-out wafer level package) or FOPLP (fan-out panel level package) process using large-sized substrate has been actively developed in recent years. Above all, we will report about the novel TCB (thermal compression bonding) equipment which is even applicable to a 3D-IC stacking process and a fine pitch FOWLP or FOPLP of RDL-first process using large-sized substrate. We made the prototype which was applicable to CoW of 12 inch wafer and evaluated it. The prototype includes a high rigid fixed stage which is designed to the same size as the bonding head, and a substrate handling mechanism which lifts a substrate from the stage and transfers it to other prescribed position every one bonding cycle. By using this equipment, it is possible to thermally press a chip on even large-sized substrate without causing deterioration in bonding accuracy resulting from stage distortion. Also, it does not need to manage UTOS (Underfill time on stage), when the equipment is used for "2 step bonding process" which can improve the throughput of TCB. In this presentation, we will report about the investigation result of the heat influence on adjacent chip and about the temperature difference in the 3D-IC stacking process by using the prototype. In addition, we will present a novel multi-layer collecting bonding process which is applicable to a large-sized substrate effectively, and report about the result of the evaluation of solder connection of the TSV TEG chip.