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The field of neuromorphic computing systems has been through enormous progress in recent years, whereas some issues are still remaining to be solved. One of the biggest challenges in neuromorphic circuit designing is the lack of a robust device with functions comparable to or even better than the metal-oxide-semiconductor field-effect transistor (MOSFET) used in traditional integrated circuits. In this work, we demonstrated a MoS2 neuristor using a dual-gate transistor structure. An ionic top gate is designed to control the migration of ions, while an electronic back gate is used to control electronic migration. By applying different driving signals, the MoS2 neuristor can be programmed as a neuron, a synapse, or an n-type MOSFET, which can be seen as a fundamental building block in the neuromorphic circuit design. The MoS2 neuristor provides viable solutions for future reconfigurable neuromorphic systems and can be a promising candidate for future neuromorphic computing.

Memristive devices based on electrochemical processes are promising candidates for next-generation memory and neuromorphic applications. The redox processes happening at the interfaces are crucial steps for the ionization as well as generation of counter charges, and are thus indispensable for successful resistive switching, but their detailed mechanism has not been fully clarified. Here, we study the interfacial redox reactions in the forming process of memristive devices based on valence change and electrochemical metallization, using high-resolution electron microscopy and electrostatic force microscopy observations. We show direct evidence for the anodic oxidation of oxygen ions and cathodic reduction of moisture in HfO2- and Ta2O5-based valence change cells, which could take place in different horizontal locations. We further found that the anodic reactions always led to more pronounced structural damage to the electrode, indicating the possibility of additional cathodic reactions without producing gaseous products. When an active electrode is present, oxidation of metal atoms takes place at the anodic interface instead. Further investigations on electrochemical metallization cells have identified Cu ionization and moisture reduction as the anodic and cathodic reactions, respectively, and formation of Cu nuclei at the cathodic interface was directly observed. These findings with microscopic evidence could facilitate future development of memristive devices.

Van der Waals heterostructures composed of two-dimensional (2D) transition metal dichalcogenides (TMD) materials have stimulated tremendous research interest in various device applications, especially in energy-efficient future-generation electronics. Such ultra-thin stacks as tunnel junction theoretically present unprecedented possibilities of tunable relative band alignment and pristine interfaces, which enable significant performance enhancement for steep-slope tunneling transistors. In this work, the optimal 2D-2D heterostructure for tunneling transistors is presented and elaborately engineered, taking into consideration both electric properties and material stability. The key challenges, including band alignment and metal-to-2D semiconductor contact resistances, are optimized separately for integration. By using a new dry transfer technique for the vertical stack, the selected WS2/SnS2 heterostructure-based tunneling transistor is fabricated for the first time, and exhibits superior performance with comparable on-state current and steeper subthreshold slope than conventional FET, as well as on-off current ratio over 106 which is among the highest value of 2D-2D tunneling transistors. A visible negative differential resistance feature is also observed. This work shows the great potential of 2D layered semiconductors for new heterostructure devices and can guide possible development of energy-efficient future-generation electronics.

Energy efficiency has become the main concern of IC technology. Tunnel FET (TFET) is recognized to possess the superiority of energy efficiency over MOSFET at ultralow voltage, while variability might limit the voltage reduction and thus the energy saving. Recently, device source doping gradient (SDG) is found to be the dominant variation source in TFET. In this paper, for the first time, with the awareness of SDG variation, the energy efficiency of TFET-based circuits with different activity factors ( $\alpha $ ) is comprehensively reassessed and the device optimization strategy is provided. It is found that the superiority of energy efficiency of TFET will significantly decrease especially for the more active circuit due to the inherent tradeoff between SDG variation and nominal SDG. Based on the quantitative relationship between SDG variation and nominal SDG extracted from the experimental devices, the optimal design of tunnel junction abruptness to maximize the circuit energy efficiency is obtained, leading to significant energy efficiency improvements of TFET-based circuit over MOSFET even for circuit with high $\alpha $ . This paper provides helpful device design guidelines for TFET with device variability awareness from the perspective of circuit energy efficiency.

In this letter, a novel graded-channel heterojunction tunnel field-effect transistor (GCH-TFET) is proposed and studied by simulation. The novel TFET adopts a near broken-gap heterojunction at the source/channel interface to enhance the tunnel efficiency. Besides, it employs a graded component channel which works as an electron barrier to block up the leakage current at the OFF-state and can be removed with the increased gate voltage at the ON-state for high ON/ OFF-current ( ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ) ratio. Such graded channel also allows a sudden turn-on of band-to-band tunneling, resulting in a reduced sub-threshold swing (SS) compared with conventional heterojunction TFETs. The GCH-TFET demonstrates an ${I}_{\scriptscriptstyle\text {ON}}/{I}_{\scriptscriptstyle\text {OFF}}$ ratio of more than seven decades with ${I}_{\scriptscriptstyle\text {ON}}$ up to 225 $\mu \text{A}/\mu \text{m}$ at ${V}_{\textsf {DD}} = \textsf {0.3}$ V, ${I}_{\scriptscriptstyle\text {OFF}}$ more than two decades lower than a near broken-gap heterojunction TFET and SS lower than 30 mV/decade for more than five decades, exhibiting excellent potential for ultra-low power applications.

As one of the important sources of low-frequency noise, random telegraph noise (RTN) in tunnel FET (TFET) has attracted growing attention recently. However, there is still lack of explanation for the high-amplitude RTN, which may cause serious variability and reliability problems to TFET-based ultralow-power circuits. In this paper, we experimentally investigate the RTN amplitude characteristics in TFETs, revealing the mechanism of high-amplitude RTN. It is found that the nonuniform distribution of band-to-band tunneling (BTBT) generation rate along device width direction is responsible for the high-amplitude RTN. Locations with relatively higher BTBT generation rate may act as critical paths dominating the device current. “Lucky” trap located at a critical path can induce the high-amplitude RTN. With device width shrinking, the number of critical paths may be reduced, resulting in much higher maximum RTN amplitude. In addition, the impacts of process parameters on RTN amplitude are discussed. Both higher source doping concentration ( $\text{N}_{\text {S}})$ and higher thermal budget can effectively mitigate the nonuniformity of BTBT generation rate along device width direction, causing suppressed RTN amplitudes. Considering that the higher thermal budget may lead to degraded device performance, the annealing process should compromisingly be designed in terms of both variation and device performance.

Memristors are important building blocks for neuromorphic computing, which can be used to mimic the function of synapse in the human brain, manifesting the significance of the integration technology of the memriator array for building the neuromorphic computing systems. The main achievement of this work is the realization of the nanoscale neuromorphic memristor with low-power consumption and nanosecond respond time by applying electron beam lithography technology, which lays firm foundation for neuromorphic computing chips.

Oxide-based resistive switching devices have tremendous potential in next-generation nonvolatile memory and neuromorphic applications. Here, the emergence of quantized conductance is investigated in resistive switching devices based on Ta 2 O 5 or HfO 2 . By applying sweeping voltages with different current compliances or using consecutive voltage pulses, quantized conductance states including integer and half integer multiples of quantum conductance (G 0 ) were observed, suggesting well-controlled formation of atomic point contacts. Compared with Pt/Ta/Ta 2 O 5 /Pt devices, a larger number of quantized conductance states were obtained in the Pt/Ta/HfO 2 /Pt devices. Such quantized conductance states are inherently discrete and multilevel, which could be promising for applications as multilevel nonvolatile memory and artificial synapses in hardware neural networks.

This article provides a review of current development and challenges in brain-inspired computing with memristors. We review the mechanisms of various memristive devices that can mimic synaptic and neuronal functionalities and survey the progress of memristive spiking and artificial neural networks. Different architectures are compared, including spiking neural networks, fully connected artificial neural networks, convolutional neural networks, and Hopfield recurrent neural networks. Challenges and strategies for nanoelectronic brain-inspired computing systems, including device variations, training, and testing algorithms, are also discussed.

The rapid development of information technology has led to urgent requirements for high efficiency and ultralow power consumption. In the past few decades, neuromorphic computing has drawn extensive attention due to its promising capability in processing massive data with extremely low power consumption. Here, we offer a comprehensive review on emerging artificial neuromorphic devices and their applications. In light of the inner physical processes, we classify the devices into nine major categories and discuss their respective strengths and weaknesses. We will show that anion/cation migration-based memristive devices, phase change, and spintronic synapses have been quite mature and possess excellent stability as a memory device, yet they still suffer from challenges in weight updating linearity and symmetry. Meanwhile, the recently developed electrolyte-gated synaptic transistors have demonstrated outstanding energy efficiency, linearity, and symmetry, but their stability and scalability still need to be optimized. Other emerging synaptic structures, such as ferroelectric, metal–insulator transition based, photonic, and purely electronic devices also have limitations in some aspects, therefore leading to the need for further developing high-performance synaptic devices. Additional efforts are also demanded to enhance the functionality of artificial neurons while maintaining a relatively low cost in area and power, and it will be of significance to explore the intrinsic neuronal stochasticity in computing and optimize their driving capability, etc. Finally, by looking into the correlations between the operation mechanisms, material systems, device structures, and performance, we provide clues to future material selections, device designs, and integrations for artificial synapses and neurons.

Magneto-electronic logic is an innovative approach to performing high-efficiency computations. Additionally, the ultra-large scale integration requirement for computation strongly suggests exploiting magnetoresistance effects in non-magnetic semiconductor materials. Here, we demonstrate the magnetoresistance effect in a silicon nanowire field effect transistor (SNWT) fabricated by complementary metal-oxide-semiconductor (CMOS)-compatible technology. Our experimental results show that the sign and the magnitude of the magnetoresistance in SNWTs can be effectively controlled by the drain-source voltage and the gate-source voltage, respectively, playing the role of a multi-terminal tunable magnetoresistance device. Various current models are established and in good agreement with the experimental results that describe the impact of electrical voltage and magnetic field on magnetoresistance, which provides design feasibility for the high-density magneto-electronic circuit. Such findings will further pave the way for nanoscale silicon-based magneto-electronics logic devices and show a possible path beyond the developmental limits of CMOS logic.

Here we report a device size and structure dependent study on the resisitive switching and synaptic plasticity in HfO2-based memristive devices. We found that the on/off ratio of resistive switching constantly increases as device size decreases, and bilayer Pt/TaO x /HfO 2 /Pt devices generally exhibit more uniform switching characteristics and lower threshold voltages compared with single-layer Pt/HfO 2 /Pt devices. Long-term potentiation and depression behaviors have been emulated using such bilayer devices, suggesting potential applications for neuromorphic hardware.

Neuromorphic computing represents an innovative technology that can perform intelligent and energy-efficient computation, whereas construction of neuromorphic systems requires biorealistic synaptic elements with rich dynamics that can be tuned based on a robust mechanism. Here, an ionic-gating-modulated synaptic transistor based on layered crystals of transitional metal dichalcogenides and phosphorus trichalcogenides is demonstrated, which produce a diversity of short-term and long-term plasticity including excitatory postsynaptic current, paired pulse facilitation, spiking-rate-dependent plasticity, dynamic filtering, etc., with remarkable linearity and ultralow energy consumption of ≈30 fJ per spike. Detailed transmission electron microscopy characterization and ab initio calculation reveal two-stage ionic gating effects, namely, surface adsorption and internal intercalation in the channel medium, causing different poststimulation diffusive dynamics and thus accounting for the observed short-term and long-term plasticity, respectively. The synaptic activity can therefore be effectively manipulated by tailoring the ionic gating and consequent diffusion dynamics with varied thickness and structure of the van der Waals material as well as the number, duration, rate, and polarity of gate stimulations, making the present synaptic transistors intriguing candidates for low-power neuromorphic systems.

Neuromorphic architectures based on memristive neurons and synapses hold great prospect in achieving highly intelligent and efficient computing systems. Here, we show that a Schottky diode based on Cu-Ta/InGaZnO4 (IGZO)/TiN structure can exhibit threshold switching behavior after electroforming and in turn be used to implement an artificial neuron with inherently stochastic dynamics. The threshold switching originates from the Cu filament formation and spontaneous Cu–In–O precipitation in IGZO. The nucleation and precipitation of Cu–In–O phase are stochastic in nature, which leads to the stochasticity of the artificial neuron. It is demonstrated that IGZO based stochastic neurons can be used for global minimum computation with random walk algorithm, making it promising for robust neuromorphic computation.

Neuromorphic engineering offers a promising route toward intelligent and low power computing systems that may find applications in artificial intelligence and the Internet. Construction of neuromorphic systems, however, requires scalable nanodevices that could implement the key functionalities of biological synapses. Here, we demonstrate an artificial synaptic device consisting of a Ti/yttria-stabilized-zirconia (ZrO2:Y)/Pt memristive structure, where the loss microstructure, high oxygen vacancy concentration, and resultant high ionic conductivity in ZrO2:Y facilitate the oxygen vacancy migration and filament evolution in the devices, leading to a bipolar artificial synapse with low forming and operation voltages. As the thickness of ZrO2:Y film increases, a transition from bipolar to unipolar resistive switching was observed, which can be ascribed to the competing vertical and radial ion transport dynamics. The emergence of unipolar switching has in turn allowed the device to exhibit metaplasticity, a history dependent plasticity that is important for memory and learning functions. This work thus demonstrates on-demand manipulation of ionic transport properties for building synaptic elements with rich functionalities.