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“Fail often to succeed sooner” is a common mantra that we are told is the secret to success. When reporting research results, however, scholars rarely write about their failed attempts and only focus on the successful ones. Perhaps the source of this disconnect between what we preach and what we do can be found in the underlying assumption that published work is meant to move the field forward and failed attempts supposedly do not. The goal of the confessions presented in this paper is to show that even failed attempts are genuine and valuable contributions to our field provided that we learn from our mistakes and correct them. The 27 confessions span from planning oversights, digital and analog design errors, misunderstanding of devices, overlooked parasitics, LVS errors, and troubles in testing.

The total economic cost of neurological disorders exceeds £100 billion per annum in the United Kingdom alone, yet pharmaceutical companies continue to cut investments due to failed clinical studies and risk [1]. These challenges motivate an alternative to solely pharmacological treatments. The emerging field of bioelectronics suggests a novel alternative to pharmaceutical intervention that uses electronic hardware to directly stimulate the nervous system with physiologically inspired electrical signals [2]. Given the processing capability of electronics and precise targeting of electrodes, the potential advantages of bioelectronics include specificity in the time, method, and location of treatment, with the ability to iteratively refine and update therapy algorithms in software [3]. A primary disadvantage of the current systems is invasiveness due to surgical implantation of the device.

The introduction of large-scale chemical sensing systems in CMOS which integrate millions of ISFET sensors have allowed applications such as DNA sequencing and fine-pixel chemical imaging systems to be realised. Using CMOS ISFETs provides advantages of digitisation directly at the sensor as well as correcting for non-linearity in its response. However, for this to be beneficial and scale, the readout circuits need to have the minimum possible footprint and power consumption. Within this context, this paper analyses an ISFET based pH-to-time readout using an inverter in the time-domain as a level-crossing detector and presents a 32 × 32 array with in-pixel digitisation for pH sensing. The inverter-based sensing pixel, controlled by a triangular waveform, converts the pH response into a time-domain signal whilst also compensating for sensor offset and thus resulting in an increase in dynamic range. The sensor pixels interface to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast asynchronous conversion whilst using minimal silicon area. Parallel outputs of 32 TDC interfaces are serialised to achieve fast data throughput. This system is implemented in a standard 0.18 $\,\mu$ m CMOS technology, with a pixel size of 26 $\mu$ m × 26 $\mu$ m and a TDC area of 26 $\mu$ m × 180 $\mu$ m. Additionally, we investigate the use of additional offset compensation by having half of the array implemented with the floating gate tied down via a well diode. Measured results demonstrate the system is able to sense reliably with an average pH sensitivity of 30 mV/pH, whilst being able to compensate for sensor offset by up to $\pm$ 7 V. A resolution of 0.013 pH is achieved and noise measurements show an integrated noise of 0.08 pH within 2–500 Hz and SFDR of 42.6 dB. The total power consumption of the system is measured to be 11.286 mW when operating at a high frame rate of 1 KFPS.

The unobtrusive monitoring of vital signals and behaviour can be used to gather intelligence to support the care of people living with dementia. This can provide insights into the person's wellbeing and the neurogenerative process, as well as enable them to continue to live safely at home, thereby improving their quality of life. Within this context, this study investigated the deployability of non-contact respiration rate (RR) measurement based on an Ultra-Wideband (UWB) radar System-on-Chip (SoC). An algorithm was developed to simultaneously and continuously extract the respiration signal, together with the confidence level of the respiration signal and the target position, without needing any prior calibration. The radar-measured RR results were compared to the RR results obtained from a ground truth measure based on the breathing sound, and the error rates were within 8% with a mean value of 2.5%. The target localisation results match to the radar-to-chest distances with a mean error rate of 5.8%. The tested measurement range was up to 5m. The results suggest that the algorithm could perform sufficiently well in non-contact stationary respiration rate detection.

Next generation implantable neural interfaces are targeting devices with mm-scale form factors that are freely floating and completely wireless. Scalability to more recording (or stimulation) channels will be achieved through distributing multiple devices, instead of the current approach that uses a single centralized implant wired to individual electrodes or arrays. In this way, challenges associated with tethers, micromotion, and reliability of wiring is mitigated. This concept is now being applied to both central and peripheral nervous system interfaces. One key requirement, however, is to maximize specific absorption rate (SAR) constrained achievable wireless power transfer efficiency (PTE) of these inductive links with mm-sized receivers. Chip-scale coil structures for microsystem integration that can provide efficient near-field coupling are investigated. We develop near-optimal geometries for three specific coil structures: in-CMOS, above-CMOS (planar coil post-fabricated on a substrate), and around-CMOS (helical wirewound coil around substrate). We develop analytical and simulation models that have been validated in air and biological tissues by fabrications and experimental measurements. Specifically, we prototype structures that are constrained to a 4 mm $ \times$ 4 mm silicon substrate, i.e., the planar in-/above-CMOS coils have outer diameters $ 4 mm, whereas the around-CMOS coil has an inner diameter of 4 mm. The in-CMOS and above-CMOS coils have metal film thicknesses of 3- $\mu$ m aluminium and 25- $\mu$ m gold, respectively, whereas the around-CMOS coil is fabricated by winding a 25- $\mu$ m gold bonding wire around the substrate. The measured quality factors ( Q ) of the mm-scale Rx coils are 10.5 @450.3 MHz (in-CMOS), 24.61 @85 MHz (above-CMOS), and 26.23 @283 MHz (around-CMOS). Also, PTE of 2-coil links based on three types of chip-scale coils is measured in air and tissue environment to demonstrate tissue loss for bio-implants. The SAR-constrained maximum PTE measured (together with resonant frequencies, in tissue) are 1.64% @355.8 MHz (in-CMOS), 2.09% @82.9 MHz (above-CMOS), and 3.05% @318.8 MHz (around-CMOS).

This paper presents a low-power analog-to-time converter (ATC) for integrated bio-sensors. The proposed circuit facilitates the direct conversion of electrode bio-potential recordings into time-encoded digital pulses with high efficiency without prior signal amplification. This approach reduces the circuit complexity for multi-channel instrumentation systems and allows asynchronous digital control to maximize the potential power savings during sensor inactivity. A prototype fabricated using a 65-nm CMOS technology is demonstrated with measured characteristics. Experimental results show an input-referred noise figure of 3.8 $\mu V_{\mathrm{ rms}}$ for a 11-kHz signal bandwidth while dissipating 1.2 $\mu \text{W}$ from a 0.5-V supply and occupying $60\times 80\,\,\mu \text{m}\,\,^{\mathrm{ 2}}$ silicon area. This compact configuration is enabled by the proposed asynchronous readout that shapes the mismatch components arising from the multi-bit quantizer and the use of capacitive feedback.

The instrumentation systems for implantable brain–machine interfaces represent one of the most demanding applications for ultra low-power analogue-to-digital-converters (ADC) to date. To address this challenge, this paper proposes a $\Delta \Sigma $ SAR topology for very large sensor arrays that allows an exceptional reduction in silicon footprint by using a continuous time 0–2MASH topology. This configuration uses a specialized FIR window to decimate the $\Delta \Sigma $ modulator output and reject mismatch errors from the SAR quantizer, which mitigates the overhead from dynamic element matching techniques commonly used to achieve high precision. A fully differential prototype was fabricated using $0.18\,\mu $ m CMOS to demonstrate 10.8 ENOB precision with a 0.016 mm2 silicon footprint. Moreover, a 14fJ/conv figure-of-merit can be achieved, while resolving signals with the maximum input amplitude of ±1.2 Vpp sampled at 200 kS/s. The ADC topology exhibits a number of promising characteristics for both high speed and ultra low-power systems due to the reduced complexity, switching noise, sampling load, and oversampling ratio, which are critical parameters for many sensor applications.

The recent evolution of implantable medical devices from single-unit stimulators to modern implantable microsystems, has driven the need for distributed technologies, in which both the implant system and functions are partitioned across multiple active devices. This multi-module approach is made possible thanks to novel network architectures, allowing for in-body power and data communications to be performed using implantable leads. This paper discusses the challenges in implementing such interfacing system and presents a platform based on one central implant (CI) and multiple peripheral implants (PIs) using a custom 4WiCS communication protocol. This is implemented in PCB technology and tested to demonstrate intrabody communication capabilities and power transfer within the network. Measured results show CI-to-PI power delivery achieves 70 % efficiency in expected load condition, while establishing full-duplex data link with up to 4 PIs simultaneously.

Sleep serves an underlying function in mammals that appears to be essential for life, but despite decades of research, this function and a large part of the neuronal circuitry underlying its control, are little understood. To conduct research in this field, many devices capable of recording neural signals such as LFP and EEG have been developed. However, due to their size and weight, most of these devices are unsuitable for sleep studies in mice, the most commonly used animals. This paper presents a novel 4 channel, compact (2.1cm by 1.7cm) and lightweight (3.6g) neural-logging device that can record for 3 days on just two 0.6g zinc air 312 batteries. Instead of the typical solution of using multiple platforms, the presented device integrates high resolution EEG, EMG and temperature recordings into one platform. The onboard BLE module allows the device to be controlled wirelessly as well as stream data in real time, enabling researchers to check the progress of the recording with minimal animal disturbance. The device is able to accurately record EEG and temperature data through long 24 hour in-vivo recordings conducted. The obtained EEG data could be easily sleep scored and the temperature values were all within the expected physiological range.

Coherent ultra-wideband (UWB) radar-on-chip technology shows great promise for developing portable and low-cost medical imaging and monitoring devices. Particularly monitoring the mechanical functioning of the cardiovascular system is of interest, due to the ability of radar systems to track sub-mm motion inside the body at a high speed. For imaging applications, UWB radar systems are required, but there are still significant challenges with in-body sensing using low-power microwave equipment and wideband signals. Recently it was shown for the first time, on a single subject, that the arterial pulse wave can be measured at various locations in the body, using coherent UWB radar-on-chip technology. The current work provides more substantial evidence, in the form of new measurements and improved methods, to demonstrate that cardiovascular dynamics can be measured using radar-on-chip. Results across four participants were found to be robust and repeatable. Cardiovascular signals were recorded using radar-on-chip systems and electrocardiography (ECG). Through ECG-aligned averaging, the arterial pulse wave could be measured at a number of locations in the body. Pulse arrival time could be determined with high precision, and blood pressure pulse wave propagation through different arteries was demonstrated. In addition, cardiac dynamics were measured from the chest. This work serves as a first step in developing a portable and low-cost device for long-term monitoring of the cardiovascular system, and provides the fundamentals necessary for developing UWB radar-on-chip imaging systems.

This paper presents a novel analogue to digital converter using an oscillator-based loop filter for high-dynamic range bio-sensing applications. This is the first third-order feedforward ΔΣ modulator that strictly uses time domain integration for quantisation noise shaping. Furthermore we propose a new asynchronous extended-phase detection technique that increases the resolution of the 4 bit phase quantiser by another 5 bits to significantly improve both dynamic range and reduce the noise-shaping requirements. Preliminary simulation results show that this type of loop-filter can virtually prevent integrator saturation and achieves a peak 88 dB SNDR for kHz signals. The proposed system has been implemented using a 180 nm CMOS technology occupying 0.102 mm 2 and consumes 13.7 μW of power to digitise the 15 kHz signal bandwidth using a 2 MHz sampling clock.

This paper presents an oscillator based potentiostat with switch-cap feedback for current sensing applications. In this work, a sigma-delta modulator is realized using current as input and charge as the feedback. The current input is integrated at the input capacitance and the voltage difference between the integrated value and reference input is converted to current via a transconductor. This current is then fed into a current controlled ring oscillator and the frequency output drives the switch-cap circuits to compensate the input current. Therefore, the current input can be directly readout as frequency deviation, or can be further converted to digital output via a frequency to digital converter. The proposed system is implemented in a typical 0.18µm CMOS technology, with total area of 80 × 250µm2. A differential structure was implemented to minimize the parasitic and kick back influence, with oscillator base frequency at 491MHz. A counter based frequency to digital converter with an additional CIC filter was implemented to convert the differential frequency signal to digital domains at 16MHz sampling frequency. Simulation results demonstrated that a dynamic range of 52dB was achieved with input range of ±2.5µA.

This paper presents a 17 bit analogue-to-digital converter that incorporates mismatch and quantisation noise-shaping techniques into an energy-saving 10 bit successive approximation quantiser to increase the dynamic range by another 42 dB. We propose a novel fully-capacitive topology which allows for high-speed asynchronous conversion together with a background calibration scheme to reduce the oversampling requirement by 10× compared to prior-art. A 0.18μm CMOS technology is used to demonstrate preliminary simulation results together with analytic measures that optimise parameter and topology selection. The proposed system is able to achieve a FoM S of 183 dB for a maximum signal bandwidth of 15.6 kHz while dissipating 68 μW from a 1.8 V supply. A peak SNDR of 102 dB is demonstrated for this rate with a 0.201 mm2 area requirement.

This paper presents a 32×32 ISFET sensing array with in-pixel digitisation for pH sensing. The in-pixel digitisation is achieved using an inverter-based sensing pixel that is controlled by a triangular waveform. This converts the pH response of the ISFET into a time-domain signal whilst also increasing dynamic range and thus the ability to tolerate sensor offset. The pixels are interfaced to a 15-bit asynchronous column-wise time-to-digital converter (TDC), enabling fast sensor readout whilst using minimal silicon area. Parallel output of 32 TDC interfaces are serialised to achieve fast data though-put. This system is implemented in a standard 0.18 μm standard CMOS technology, with a pixel size of 26 μm × 26 μm and a TDC of 26 μm × 180 μm. Simulation results demonstrate that chemical sampling of up to 5k frames per second can be achieved with a clock frequency of 160 MHz and a TDC resolution of 190 ps. The total power consumption of the overall system is 7.34 mW.

In this paper we report on the fabrication, implementation and experimental characterization of an integrated bidirectional communication System-on-Chip (SoC) for transcutaneous bidirectional optical biotelemetry links. The proposed architecture implements a UWB-inspired pulsed coding technique and contains a transmitter and a receiver to achieve a simultaneous bidirectional link. The transmitter generates sub-nanosecond current pulses to directly drive off-chip pulsed vertical cavity semiconductor lasers by means of a digital data coding subsystem and all the needed bias and driving circuits. On the other hand, the receiver manages off-chip fast Si photodiodes and includes signal conditioning, detection and digital data decoding circuits to support high bit rate and energy efficient communication links. The entire solution designed at transistor level has been fabricated in AMS 0.35µm standard CMOS technology into a compact silicon footprint lower than 0.13mm2 employing only 113 transistors and 1 resistor. A specific PCB has been developed together with a suitable test bench implemented on Xilinx Virtex-6 XC6VLX240T FPGA board to properly evaluate the performances and the main characteristics of the ASIC. Furthermore, a 6 GHz, 20 GS/s LeCroy WaveMaster 8600A digital oscilloscope has been employed to investigate the system time response. Preliminary experimental results validated the correct functionality of the overall integrated system demonstrating also its capability to operate, also in a bidirectional mode, at bit rates up to 250 Mbps with pulse widths up to 1.2ns and a minimum total power efficiency of about 160 pJ/bit in the conditions for which the transmitter and the receiver work simultaneously onto the same chip. These results make the developed solution suitable for high performances bidirectional optical biotelemetry links to be applied, e.g., to implantable neural recording/stimulation transcutaneous platforms that generally require communication channels with high up- e down-link bit rates at extremely low energy levels.

Local field potential (LFP) has gained increasing interest as an alternative input signal for brain-machine interfaces (BMIs) due to its informative features, long-term stability, and low frequency content. However, despite these interesting properties, LFP-based BMIs have been reported to yield low decoding performances compared to spike-based BMIs. In this paper, we propose a new decoder based on long short-term memory (LSTM) network which aims to improve the decoding performance of LFP-based BMIs. We compare offline decoding performance of the proposed LSTM decoder to a commonly used Kalman filter (KF) decoder on hand kinematics prediction tasks from multichannel LFPs. We also benchmark the performance of LFP-driven LSTM decoder against KF decoder driven by two types of spike signals: single-unit activity (SUA) and multi-unit activity (MUA). Our results show that LFP-driven LSTM decoder achieves significantly better decoding performance than LFP-, SUA-, and MUA-driven KF decoders. This suggests that LFPs coupled with LSTM decoder could provide high decoding performance, robust, and low power BMIs., Comment: Accepted for the 9th International IEEE EMBS Conference on Neural Engineering (NER 2019)

This paper presents a novel wireless power transfer (WPT) scheme that consists of a two-tier hierarchy of near-field inductively coupled links. Key aims are to provide efficient power transfer efficiency (PTE) and uniform energy distribution for mm-scale free-positioned neural implants. The top tier facilitates a transcutaneous link from a scalp-worn (em-scale) primary coil to a subcutaneous array of smaller, parallel-connected secondary coils. These are then wired through the skull to a corresponding set of parallel connected primary coils in the lower tier, placed epidurally. These then inductively couple to freely positioned (mm-scale) secondary coils within each subdural implant. This architecture has three key advantages: (1) the opportunity to achieve efficient energy transfer by utilising two short-distance inductive links; (2) good uniformity of the transdural power distribution through the multiple (redundant) coils; and (3) a reduced risk of infection by maintaining the dura protecting the blood-brain barrier. The functionality of this approach has been verified and optimised through HFSS simulations, to demonstrate the robustness against positional and angular misalignment. The average 11.9% PTE and 26.6% power distribution deviation (PDD) have been achieved for the Rx coil in parallel with the epidural coil array. The average PTE and PDD degenerate to 2.6% and 62.8% when the Rx coil is perpendicular to the epidural coil array.

This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding local- field-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-low- power sensors to perform spectroscopy with high-fidelity.

This paper presents a novel chopping method allow- ing suppression of 1/f flicker noise in continuous-time acquisition systems without the need for a fixed-frequency clock, stochasti- cally deriving the chopping signal from the input and hence achieving completely signal-dependent power consumption. The method is analysed, its basis of operation explained and a proof- of-concept implementation presented alongside simulated results demonstrating an increase in achieved SNR of more than 8 dB during acquisition of ECG, EAP and EEG signals.

Single-chip UWB radar systems have enormous potential for the development of portable, low-cost and easy-to-use devices for monitoring the cardiovascular system. Using body coupled antennas, electromagnetic energy can be directed into the body to measure arterial pulsation and cardiac motion, and estimate arterial stiffness as well as blood pressure. In the current study we validate that heart rate signals, obtained using multiple UWB radar-on-chip modules and body coupled antennas, do indeed originate from arterial pulsation. Through ECG-aligned averaging, pulse arrival time at a number of locations in the body could be measured with high precision, and arterial pulse propagation through the femoral and carotid artery was demonstrated. In addition, cardiac dynamics were measured from the chest. Onset and offset of ventricular systole were clearly distinguishable, as well as onset of atrial systole. Although further validation is required, these results show that UWB radar-on-chip is highly suitable for monitoring of vascular health as well as the heart's mechanical functioning.

This paper reports on the implementation and characterisation of a thermally controlled device for in vitro biomedical applications, based on standard Printed Circuit Board (PCB) technology. This is proposed as a low cost alternative to state-of-the-art microfluidic devices and Lab-on-Chip (LoC) platforms, which we refer to as the thermal Lab-on-PCB concept. In total, six different prototype boards have been manufactured to implement as many mini-hotplate arrays. 3D multiphysics software simulations show the thermal response of the modelled mini-hotplate boards to electrical current stimulation, highlight- ing their versatile heating capability. A comparison with the results obtained by the characterisation of the fabricated PCBs demonstrates the dual temperature sensing/heating property of the mini-hotplate, exploitable in a larger range of temperature with respect to the typical operating range of LoC devices. The thermal system is controllable by means of external off-the-shelf circuitry designed and implemented on a single-channel control board prototype.

Neuromodulation technologies are progressing from pacemaking and sensory operations to full closed-loop control. In particular, optogenetics—the genetic modification of light sensitivity into neural tissue allows for simultaneous optical stimulation and electronic recording. This paper presents a neural interface application-specified integrated circuit (ASIC) for intelligent optoelectronic probes. The architecture is designed to enable simultaneous optical neural stimulation and electronic recording. It provides four low noise (2.08 μ V $_{\text{rms}}$ ) recording channels optimized for recording local field potentials (LFPs) (0.1–300 Hz bandwidth, $\pm$ 5 mV range, sampled 10-bit@4 kHz), which are more stable for chronic applications. For stimulation, it provides six independently addressable optical driver circuits, which can provide both intensity (8-bit resolution across a 1.1 mA range) and pulse-width modulation for high-radiance light emitting diodes (LEDs). The system includes a fully digital interface using a serial peripheral interface (SPI) protocol to allow for use with embedded controllers. The SPI interface is embedded within a finite state machine (FSM), which implements a command interpreter that can send out LFP data whilst receiving instructions to control LED emission. The circuit has been implemented in a commercially available 0.35 μ m CMOS technology occupying a 1.95 mm $\times$ 1.10 mm footprint for mounting onto the head of a silicon probe. Measured results are given for a variety of bench-top, in vitro and in vivo experiments, quantifying system performance and also demonstrating concurrent recording and stimulation within relevant experimental models.

Objective Longitudinal observation of single unit neural activity from large numbers of cortical neurons in awake and mobile animals is often a vital step in studying neural network behaviour and towards the prospect of building effective brain-machine interfaces (BMIs). These recordings generate enormous amounts of data for transmission and storage, and typically require offline processing to tease out the behaviour of individual neurons. Our aim was to create a compact system capable of: (1) reducing the data bandwidth by circa 2 to 3 orders of magnitude (greatly improving battery lifetime and enabling low power wireless transmission in future versions); (2) producing real-time, low-latency, spike sorted data; and (3) long term untethered operation. Approach We have developed a headstage that operates in two phases. In the short training phase a computer is attached and classic spike sorting is performed to generate templates. In the second phase the system is untethered and performs template matching to create an event driven spike output that is logged to a micro-SD card. To enable validation the system is capable of logging the high bandwidth raw neural signal data as well as the spike sorted data. Main results The system can successfully record 32 channels of raw neural signal data and/or spike sorted events for well over 24 h at a time and is robust to power dropouts during battery changes as well as SD card replacement. A 24 h initial recording in a non-human primate M1 showed consistent spike shapes with the expected changes in neural activity during awake behaviour and sleep cycles. Significance The presented platform allows neural activity to be unobtrusively monitored and processed in real-time in freely behaving untethered animals-revealing insights that are not attainable through scheduled recording sessions. This system achieves the lowest power per channel to date and provides a robust, low-latency, low-bandwidth and verifiable output suitable for BMIs, closed loop neuromodulation, wireless transmission and long term data logging.

This paper investigates continuous-time (CT) signal acquisition as an activity-dependent and nonuniform sampling alternative to conventional fixed-rate digitisation. We demonstrate the applicability to biosignal representation by quantifying the achievable bandwidth saving by nonuniform quantisation to commonly recorded biological signal fragments allowing a compression ratio of $\approx$ 5 and 26 when applied to electrocardiogram and extracellular action potential signals, respectively. We describe several desirable properties of CT sampling, including bandwidth reduction, elimination/reduction of quantisation error, and describe its impact on aliasing. This is followed by demonstration of a resource-efficient hardware implementation. We propose a novel circuit topology for a charge-based CT analogue-to-digital converter that has been optimized for the acquisition of neural signals. This has been implemented in a commercially available 0.35 $\mu \text{m}$ CMOS technology occupying a compact footprint of 0.12 mm2. Silicon verified measurements demonstrate an 8-bit resolution and a 4 kHz bandwidth with static power consumption of 3.75 $\mu$ W from a 1.5 V supply. The dynamic power dissipation is completely activity-dependent, requiring 1.39 pJ energy per conversion.

Next generation brain machine interfaces fundamentally need to improve the information transfer rate and chronic consistency when observing neural activity over a long period of time. Towards this aim, this paper presents a novel System-on-Chip (SoC) for a mm-scale wireless neural recording node that can be implanted in a distributed fashion. The proposed self-regulating architecture allows each implant to operate autonomously and adaptively load the electromagnetic field to extract a precise amount of power for full-system operation. This can allow for a large number of recording sites across multiple implants extending through cortical regions without increased control overhead in the external head-stage. By observing local field potentials (LFPs) only, chronic stability is improved and good coverage is achieved whilst reducing the spatial density of recording sites. The system features a ΔΣ based instrumentation circuit that digitises high fidelity signal features at the sensor interface thereby minimising analogue resource requirements while maintaining exceptional noise efficiency. This has been implemented in a 0.35 μm CMOS technology allowing for wafer-scale post-processing for integration of electrodes, RF coil, electronics and packaging within a 3D structure. The presented configuration will record LFPs from 8 electrodes with a 825 Hz bandwidth and an input referred noise figure of 1.77μVrms. The resulting electronics has a core area of 2.1 mm2 and a power budget of 92 μW

This paper describes an integrated communication system, implementing a UWB-inspired pulsed coding technique, for an optical transcutaneous biotelemetry. The system consists of both a transmitter and a receiver facilitating a bidirectional link. The transmitter includes a digital data coding circuit and is capable of generating sub-nanosecond current pulses and directly driving an off-chip semiconductor laser diode including all bias and drive circuits. The receiver includes an integrated compact PN-junction photodiode together with signal conditioning, de- tection and digital data decoding circuits to enable a high bit rate, energy efficient communication. The proposed solution has been implemented in a commercially available 0.35 μ m CMOS technology provided by AMS. The circuit core occupies a compact silicon footprint of less than 0.13 mm 2 (only 113 transistors and 1 resistor). Post-layout simulations have validated the overall system operation demonstrating the ability to operate at bit rates up to 500 Mbps with pulse widths of 300 ps with a total power efficiency (transmitter + receiver) lower than 74 pJ/bit. This makes the system ideally suited for demanding applications that require high bit rates at extremely low energy levels. One such application is implantable brain machine interfaces requiring high uplink bitrates to transmit recorded data externally through a transcutaneous communication channel.

This paper presents an optical communication system, implementing a UWB-inspired pulsed coding technique, for emerging high throughput bio-applications such as brain machine interfaces. The proposed solution employs sub-nanosecond laser pulses that, compared to the state-of-the-art, allows for high bit rate transmissions and reduced power consumption. The overall architecture consist of a transmitter and receiver that employ a pulsed semiconductor laser and a small sensitive area photodiode. This can allow for CMOS integration into a compact silicon footprint (estimated lower than 1 mm2 in a 0.18 μm technology). The analogue circuits presented herein have been implemented using discrete off-the-shelf components. These provide the bias and drive signals for laser pulse generation, photodiode signal detection and conditioning. Moreover, the digital sub-system for data coding and decoding processes have been implemented on a FPGA board through VHDL description language. Experimental results validate the overall functionality of the proposed system using a diffuser between transmitter and receiver to emulate skin/tissue. This shows the capability of operating at bit rates up to 250 Mbps achieving BER less than 10−9 and power efficiency as low as 24pJ/bit. These results enable, for example, the transmission of a 1000-channel neural recording system sampled at 16kHz with 16-bit resolution.

Next generation brain machine interfaces are targeting millimeter-scale implants that are freely floating and completely wireless. It is essential these systems achieve good power transmission efficiency but are also compatible with microsystem technologies. This paper presents two schemes for implementing mm-scale coils for power delivery by electromagnetic coupling — on-chip and wire-wound. A set of on-chip coils have been fabricated using a 0.35 μm CMOS technology with thick top metal option (3 μm aluminium). These achieve a maximum Q-factor of 16.37. The second approach describes wire-wound coils that have been fabricated using bondwire (25 μm gold), achieving a Q-factor of 24.54. This work develops the relevant analytical models, equivalent simulation models, and reports results using both finite element modeling (simulation) and experimental measurement of the fabricated devices. Finally, we compare results and discuss the relative merits of each approach.

Emerging applications for implantable devices are requiring multi-unit systems with intrabody transmission of power and data through wireline interfaces. This paper proposes a novel method for power delivery within such a configuration that makes use of closed loop dynamic regulation. This is implemented for an implantable application requiring a single master and multiple identical slave devices utilising a parallel-connected 4-wire interface. The power regulation is achieved within the master unit through closed loop monitoring of the current consumption to the wired link. Simultaneous power transfer and full-duplex data communication is achieved by superimposing the power carrier and downlink data over two wires and uplink data over a second pair of wires. Measured results using a fully isolated (AC coupled) 4-wire lead, demonstrate this implementation can transmit up to 120 mW of power at 6 V (at the slave device, after eliminating any losses). The master device has a maximum efficiency of 80 % including a dominant dynamic power loss. A 6 V constant supply at the slave device is recovered 1.5 ms after a step of 22 mA.

This paper proposes a novel method for integrating CMOS microelectronics with microwire-based electrodes for next generation implantable brain machine interfaces. There is strong evidence to suggest that microwire-based electrodes outperform micromachined and polymer-based electrodes in terms of signal integrity and chronic viability. Furthermore, it has been shown that the recording of Local Field Potentials (LFPs) is more robust to tissue damage and scar tissue growth when compared to action potentials. This work therefore investigates the suitability of microwire electrodes for LFP recording by studying the electrical properties of key materials. We identify Niobium (Nb) as a candidate material with highly desirable properties. There is however also an inherent incompatibility when it comes to connection of microwire-based electrodes to silicon chips. Here we present a new process flow utilising a recessed glass substrate for mechanical support, silicon interposer for interconnection, and electroplating for contact adhesion. Furthermore, the proposed structure lends itself to hermetic encapsulation towards gas cavity based micropackages.

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth- order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure- of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst addition- ally offering direct integration with digital systems.

This work presents a computationally efficient real-time adaptive clustering algorithm that recognizes and adapts to dynamic changes observed in neural recordings. The algorithm consists of an off-line training phase that determines initial cluster positions and an on-line operation phase that continuously tracks drifts in clusters and periodically verifies acute changes in cluster composition. Analysis of chronic recordings from non-human primates shows that adaptive clustering achieves an improvement of 14% in classification accuracy and demonstrates an ability to recognize acute changes with 78% accuracy, with significantly improved computational efficiency compared to the state-of-the-art. The presented algorithm is suitable for long-term chronic monitoring of neural activity in many applications of neuroscience research and control of neural prosthetics and assistive devices.

This paper presents a hardware realisation of a novel ECG baseline drift removal that preserves the ECG signal integrity. The microcontroller implementation detects the fiducial markers of the ECG signal and the baseline wander estimation is achieved through a weighted piecewise linear interpolation. This estimated drift is then removed to recover a “clean” ECG signal without significantly distorting the ST segment. Experimental results using real data from the MIT-BIH Arrhythmia Database (recording 100 and 101) with added baseline wander (BWM1) from the MIT-BIH Noise Stress Database show an average root mean square error of 34.3 μV (mean), 30.4 μV (median) and 18.4 μV (standard deviation) per heart beat.

This paper presents a 64-bit on-chip identification system featuring low power consumption and randomness compensation for multi-node bio-implantable devices. A sense amplifier based bit-cell is proposed to realize the silicon physical unclonable function, providing a unique value whose probability has a uniform distribution and minimized influence from the temperature and supply variation. The entire system is designed and implemented in a typical 0.35 μm CMOS technology, including an array of 64 bit-cells, readout circuits, and digital controllers for data interfaces. Simulated results show that the proposed bit-cell design achieved a uniformity of 50.24% and a uniqueness of 50.03% for generated IDs. The system achieved an energy consumption of 6.0 pJ per bit with parallel outputs and 17.3 pJ per bit with serial outputs.

The paper presents a novel topology of a continuous-time analogue-to-digital converter (CT-ADC) featuring ultra-low static power consumption, activity-dependent dynamic consumption, and a compact footprint. This is achieved by utilising a novel charge-packet based threshold generation method, that alleviates the requirement for a conventional feedback DAC. The circuit has a static power consumption of 3.75 μW, with dynamic energy of 1.39pJ/conversion level. This type of converter is thus particularly well-suited for biosignals that are generally sparse in nature. The circuit has been optimised for neural spike recording by capturing a 3 kHz bandwidth with 8-bit resolution. For a typical extracellular neural recording the average power consumption is in the order of ∼4 μW. The circuit has been implemented in a commercially available 0.35 μm CMOS technology with core occupying a footprint of 0.12 mm2.

This paper describes a novel system for recovering power and providing full-duplex communication over an AC-coupled 4-wire lead between active implantable devices. The target application requires a single Chest Device be connected to a Brain Implant consisting of multiple identical optrodes that record neural activity and provide closed loop optical stimulation. The interface is integrated within each optrode SoC allowing full-duplex and fully-differential communication based on Manchester encoding. The system features a head-to-chest uplink data rate (1.6 Mbps) that is higher than that of the chest-to-head downlink (100kbps) superimposed on a power carrier. On-chip power management provides an unregulated 5 V DC supply with up to 2.5 mA output current for stimulation, and a regulated 3.3 V with 60 dB PSRR for recording and logic circuits. The circuit has been implemented in a 0.35 μm CMOS technology, occupying 1.4 mm 2 silicon area, and requiring a 62.2 μA average current consumption.

This paper presents a novel oscillator based filter structure for processing time-domain signals with linear dynamics that extensively uses digital logic by construction. Such a mixed signal topology is a key component for allowing efficient processing of asynchronous time encoded signals that does not necessitate external clocking. A miniaturized primitive is introduced as analogue time-domain memory that can be modelled, synthesized, and incorporated in closed loop mixed signal accelerators to realize more complex linear or non-linear computational systems. This is contextualized by demonstrating a compact low power filter operating at 0.45 V in 65 nm CMOS. Simulation results are presented showing an excess of 50 dB dynamic range with a FOM of 7fJ/pole which promises an order of magnitude improvement on state-of-the-art filters in nanometre CMOS.

This paper reports on a pulsed coding technique based on optical Ultra-wideband (UWB) modulation for wireless implantable biotelemetry systems allowing for high data rate link whilst enabling significant power reduction compared to the state-of-the-art. This optical data coding approach is suitable for emerging biomedical applications like transcutaneous neural wireless communication systems. The overall architecture implementing this optical modulation technique employs sub-nanosecond pulsed laser as the data transmitter and small sensitive area photodiode as the data receiver. Moreover, it includes coding and decoding digital systems, biasing and driving analogue circuits for laser pulse generation and photodiode signal conditioning. The complete system has been implemented on Field-Programmable Gate Array (FPGA) and prototype Printed Circuit Board (PCB) with discrete off-the-shelf components. By inserting a diffuser between the transmitter and the receiver to emulate skin/tissue, the system is capable to achieve a 128 Mbps data rate with a bit error rate less than 10−9 and an estimated total power consumption of about 5 mW corresponding to a power efficiency of 35.9 pJ/bit. These results could allow, for example, the transmission of an 800-channel neural recording interface sampled at 16 kHz with 10-bit resolution.

This paper proposes a self-diagnostic subsystem for a new generation of brain implants with active electronics. The primary objective of such probes is to deliver optical pulses to optogenetic tissue and record the subsequent activity, but lifetime is currently unknown. Our proposed circuits aim to increase the safety of implanting active electronic probes into human brain tissue. Therefore, prolonging the lifetime of the implant and reducing the risks to the patient. The self-diagnostic circuit will examine the optical emitter against any abnormality or malfunctioning. The fracture sensor examines the optrode against any rapture or insertion breakage. The optrode including our diagnostic subsystem and fracture sensor has been designed and successfully simulated at 350nm AMS technology node and sent for manufacture.

This paper presents a novel method for improving the performance of template matching in neural spike sorting for similar shaped spikes, without increasing computational complexity. Mean templates for similar shaped spikes are enhanced to emphasise distinguishing features. Template optimisation is based on the separation and variance of sample distributions. Improved spike sorting performance is demonstrated on simulated neural recordings with two and three neuron spike shapes. The method is designed for implementation on a Next Generation Neural Interface (NGNI) device at Imperial College London.

This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.

Microwave imaging is a promising technique for non-invasive imaging of brain activity. A multistatic array of body coupled antennas and single chip pulsed ultra-wideband radars should be capable of detecting local changes in cerebral blood volume, a known indicator for neural activity. As an initial verification that small changes in the cerebrovascular system can indeed be measured inside the skull, we recorded the heart rate intracranially using a single radar module and two body coupled antennas. The obtained heart rate was found to correspond to ECG measurements. To confirm that the measured signal was indeed from within the skull, we performed simulations to predict the time-of-flight of radar pulses passing through different anatomical structures of the head. Simulated time-of-flight through the brain corresponded to the measured delay of heart rate modulation in the radar signal. The detection of intracranial heart rate using microwave techniques has not previously been reported, and serves as a first proof that functional neuroimaging using radar could lie within reach.

This paper presents a novel 64-channel ultra-low power/low noise neural recording System-on-Chip (SoC) featuring a highly reconfigurable Analogue Front-End (AFE) and block-selectable data-driven output. This allows a tunable bandwidth/sampling rate for extracting Local Field Potentials (LFPs) and/or Extracellular Action Potentials (EAPs). Realtime spike detection utilises a dual polarity simple threshold to enable an event driven output for neural spikes (16-sample window). The 64-channels are organised into 16 sets of 4-channel recording blocks, with each block having a dedicated 10-bit SAR ADC that is time division multiplexed among the 4 channels. Each channel can be individually powered down and configured for bandwidth, gain and detection threshold. The output can thus combine continuous-streaming and event-driven data packets with the system configured as SPI slave. The SoC is implemented in a commercially-available 0.35 μm CMOS technology occupying a silicon area of 19.1 mm2 (0.3 mm2 gross per channel) and requiring 32 μW/channel power consumption (AFE only).

This paper presents a novel 32-channel bidirectional neural interface, capable of high voltage stimulation and low power, low-noise neural recording. Current-controlled biphasic pulses are output with a voltage compliance of 9.25V, user configurable amplitude (max. 315 uA) & phase duration (max. 2 ms). The low-voltage recording amplifiers consume 23 uW per channel with programmable gain between 225 - 4725. Signals are 10-bit sampled at 16 kHz. Data rates are reduced by granular control of active recording channels, spike detection and event-driven communication, and repeatable multi-pulse stimulation configurations.

This paper presents a scalable architecture in 0.18 μm CMOS for implantable brain machine interfaces (BMI) that enables micro controller flexibility for data analysis at the sensor interface. By introducing more generic computational capabilities the system is capable of high level adaptive function to potentially improve the long term efficacy of invasive implants. This topology features a compact ultra low power distributed processor that supports 64-channel neural recording system on chip (SOC) with a computational efficiency of 2.7 μW/MIPS with a total chip area of 6.2 mm2. This configuration executes 1024 instructions on each core at 20 MHz to consolidate full spectrum high precision recordings from 4 analogue channels for filtering, spike detection, and feature extraction in the digital domain.

This paper presents a novel amplifier architecture intended for low power neural recording applications. By using continuous-time signal representation, the proposed topology predominantly leverages digital topologies taking advantage of efficient techniques used in time domain systems. This includes higher order feedback dynamics that allow direct analogue signal quantization and near ideal integrator structures for noise shaping. The system implemented in 0.18 μ m standard CMOS demonstrates the capability for low noise instrumentation with a bandwidth of 6 kHz and highly linear full dynamic range. Simulation results indicate 1.145 μW budget from 0.5 V supply voltage with an input referred thermal noise of 7.7 μVrms.

This paper describes a new hardware-efficient method and implementation for neural spike sorting based on selection of a channel-specific near-optimal subset of fea- tures given a larger predefined set. For each channel, real- time classification is achieved using a simple decision matrix that considers the features that provide the highest separability determined through off-line training. A 32-channel system for on- line feature extraction and classification has been implemented in an ARM Cortex-M0+ processor. Measured results of the hardware platform consumes 268 W per channel during spike sorting (includes detection). The proposed method provides at least x10 reduction in computational requirements compared to literature, while achieving an average classification error of less than 10% across wide range of datasets and noise levels.

In this paper, we present a new method for neural spike sorting based on Continuous Time (CT) signal processing. A set of CT based features are proposed and extracted from CT sampled pulses, and a complete event-driven spike sorting algorithm that performs classification based on these features is developed. Compared to conventional methods for spike sorting, the hardware implementation of the proposed method does not require any synchronisation clock for logic circuits, and thus its power consumption depend solely on the spike activity. This has been implemented using a variable quantisation step CT analogue to digital converter (ADC) with custom digital logic that is driven by level crossing events. Simulation results using synthetic neural data shows a comparable accuracy compared to template matching (TM) and Principle Components Analysis (PCA) based discrete sampled classification.

We propose an optical UWB modulation based on a new pulsed coding technique for wireless implantable biotelemetry. The solution employs sub-nanosecond laser pulses allowing for both high data rates and reduction of the power consumption compared to the state-of-the-art. Thus, the proposed approach is suitable for upcoming biomedical systems like autonomous implantable neural devices. The developed architecture consists of a transmitter and a receiver employing a pulsed semiconductor laser and a small sensitive area photodiode, respectively, and includes coding and decoding digital systems, biasing and driving analogue circuits for laser pulse generation and photodiode signal conditioning. Experimental findings, obtained by employing discrete components prototype PCBs and FPGA implementations, validate the novel technique showing the capabilities to achieve a BER less than 10 -9 with data rates up to 250Mbps and an estimated power consumption lower than 5mW. These results enable, for example, the transmission of a 1000-channel neural recording system sampled at 16 kHz with 16-bit resolution.

Here we present a method and structures for midinfrared, free-space optical communication using unmodified, commercially available complementary metal-oxide-semiconductor integrated circuits. The modulator is based on the free carrier absorption in parasitic PN junction structures under reverse bias. Measured results demonstrate the proof-of-concept with speeds of 100 b/s (1.55-μm wavelength), but at least two orders of magnitude improvement can be achieved. This technology will enable nongalvanic chip-to-chip and chip-to-package communication as an alternative to wire-bonding in applications that benefit from a planar top chip surface, such as chemical sensing lab-on-chip systems as well as general sensors and midinfrared communication.