1. Evaluating CMPs and their memory architecture
- Author
-
Jesshope, C., Lankamp, M., Zhang, L., Berekovic, M., Müller-Schloer, C., Hochberger, C., Wong, S., and System and Network Engineering (IVI, FNWI)
- Subjects
020203 distributed computing ,Cellular architecture ,Computer science ,CPU cache ,Locality ,Cache-only memory architecture ,Register file ,Uniform memory access ,02 engineering and technology ,Thread (computing) ,Memory map ,020202 computer hardware & architecture ,Microarchitecture ,Non-uniform memory access ,Shared memory ,Computer architecture ,Memory architecture ,0202 electrical engineering, electronic engineering, information engineering ,Interleaved memory ,Memory protection - Abstract
Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CMP architecture that supports automatic mapping and dynamic scheduling of threads leaving the binary code devoid of any explicit communication. The thrust of this approach is to produce binary code that is divorced from implementation parameters, yet, which still gives good performance over future generations of CMPs. A key component of this abstract processor architecture is the memory system. This paper evaluates the memory architectures, which must maintain performance across a range of targets.
- Published
- 2009