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This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip’s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel built-in self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.

In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip's maximum operating frequency (F max ). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation framework to sample a chip's F max and it's OPM result. These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs' result to chip's F max . Finally, we propose a methodology to idenify optimal placement of OPM for predicting F max . The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.

As technology node keeps scaling and design complexity keeps increasing, power distribution networks (PDNs) require more routing resource to meet IR-drop and electro-migration (EM) constraints. This paper presents a design flow to generate a PDN that can result in near-minimal overhead for the routing of the underlying standard cells while satisfying both IR-drop and EM constraints based on a given cell placement. The design flow relies on a machine-learning model to quickly predict the total wire length of global route associated with a given PDN configuration in order to speed up the search process. The experimental results based on various 28 nm industrial block designs have demonstrated the accuracy of the learned model for predicting the routing cost and the effectiveness of the proposed framework for reducing the routing cost of the final PDN.