1. Network-on-Chip for Low Power MAP Decoder Using Folded Technique and CORDIC Algorithm for 5G Network
- Author
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P S Sanjay, K Sathappan, S Shiyamala, and J Vijay Soorya
- Subjects
010302 applied physics ,business.industry ,Computer science ,02 engineering and technology ,01 natural sciences ,020202 computer hardware & architecture ,Power (physics) ,Network on a chip ,0103 physical sciences ,0202 electrical engineering, electronic engineering, information engineering ,CORDIC ,business ,5G ,Computer hardware - Abstract
With different constraint length (K), time scale, and code rate, modified MAP (maximum a posteriori) decoder architecture using folding technique, which has a linear life time chart, is developed, and dedicated turbo codes will be placed in a network-on-chip for various wireless applications. Folded techniques mitigated the number of latches used in interleaving and deinterleaving unit by adopting forward and backward resource utilizing method to M-2, where M is the number of rows and end-to-end delay get reduced to 2M. By replacing conventional full adder by high speed adder using 2 x 1 multiplexer to calculate the forward state metrics and reverse state metrics will minimize the power consumption utilization in an effective manner. In s similar way, CORDIC (Coordinated ROtation DIgital Computer) algorithm is used to calculate the LLR value and confer a highly precise value with less computational complexity by means of only shifting and adding methods.
- Published
- 2021
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