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Nowadays, 5G is playing a significant role in the efficiency of network security and creating more and faster channels for communication. 5G is evolving industries such as healthcare, education, marketing, transportation, and V2X (Vehicle-to-everything). In addition, 5G considers a new radio access technology that is adding new applications like the Internet of Things (IoT), Augmented Reality, Virtual Reality, connected cars, connected people-to-people, smart city, connected homes that are considered using higher bandwidth and low latency. Mainly, this paper is focusing on security challenges faced by the Vehicular ad-hoc network (VANET). VANET faces threats in three different fields; security, safety, and infotainment, which further have numerous attacks. More precisely, this research conducted an in-depth study and proposed a VANET trust model. Therefore the proposed model deals specifically with the “location closeness” parameter. Moreover, the trust model integrated with 5G cloud to support greater coverage, effective network density with respect to network infrastructure and IoT as well. Therefore, in this article, an effort has been put forward to implement the model using case studies to validate the trust model based on the “location closeness” parameter. The results proved the valid implementation of the model by identifying the trusted communication between the vehicles.

The Internet of things (IoT) and advancements of wireless technology have evolved intelligent transport systems to integrate billion of smart objects ready to connect to the Internet. The modern era of the Internet of things (IoT) has brought significant development in vehicular ad hoc networks (VANETs) which transformed the conventional VANET into the Internet of Vehicle (IoV) to improve road safety and diminished road congestion. However, security threats are increasing due to dependency on infrastructure, computing, dynamic nature, and control technologies of VANET. The security threats of VANETs could be addressed comprehensively by increasing trustworthiness on the message received and transmitting node. Conversely, the presence of dishonest vehicles, for instance, Man in the Middle (MiTM) attackers, in the network sharing malicious content could be posed as a severe threat to VANET. Thus, increasing trustworthiness among nodes can lead to increased authenticity, privacy, accuracy, security, and trusted information sharing in the VANET. In this paper, a lightweight trust model is proposed, presented model identifying dishonest nodes and revoking its credential in the MiTM attack scenario. Furthermore, addressing the privacy and security requirement, the pseudonym scheme is used. All nodes in the VANET established trust provided by initially RSU, which is a trusted source in the network. Extensive experiments are conducted based on a variety of network scenarios to evaluate the accuracy and performance of the presented lightweight trust model. In terms of recall, precision, and F-score, our presented model significantly outperformed compared to MARINE. The simulation results have validated that the proposed lightweight model realized a high trust level with 40% of MiTM attackers and in terms of F-score 95%, whereas the MARINE model has 90%, which leads to the model to attain high detection accuracy.

Recent researches have shown that spectral representation provides a significant speed-up in the massive computation workload of convolution operations in the inference (feed-forward) algorithm of Convolutional Neural Networks (CNNs). This approach results in reducing the computational complexity of the classification task, which makes spectral-based CNN suitable for implementation on embedded platform that typically has constrained resources. However, a major challenge in this approach is that the mathematical formulation of a nonlinear activation function in spectral (frequency) domain is currently not available; hence, computation of the activation functions in each layer has to be performed in the spatial domain. This results in several spatial-frequency domain switchings that are computationally very costly, and as such, it would be advantageous to strictly stay in the frequency domain. Hence, in this work, a novel Spectral Rectified Linear Unit (SReLU) for the activation function is proposed, that makes it possible for the computations to remain in the frequency domain, and therefore avoids the multiple compute-intensive domain transformations. To further optimize the classification speed of the network, an efficient spectral-based CNN model is presented that uses only the lower frequency components by way of fusing the convolutional and sub-sampling layers. Additionally, we provide and utilize a frequency domain equivalent of the conventional batch normalization layer that results in improving the accuracy of the network. Experimental results indicate that the proposed spectral-based CNN model achieves up to 17.02 × and 3.45 × faster classification speed (without considerable accuracy loss) on AT&T face recognition and MNIST digit/fashion classification datasets, respectively, as compared to the equivalent models in the spatial domain, hence outperforming conventional approaches significantly.

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.

In recent years, the convolutional neural network (CNN) has found wide acceptance in solving practical computer vision and image recognition problems. Also recently, due to its flexibility, faster development time, and energy efficiency, the field-programmable gate array (FPGA) has become an attractive solution to exploit the inherent parallelism in the feedforward process of the CNN. However, to meet the demands for high accuracy of today's practical recognition applications that typically have massive datasets, the sizes of CNNs have to be larger and deeper. Enlargement of the CNN aggravates the problem of off-chip memory bottleneck in the FPGA platform since there is not enough space to save large datasets on-chip. In this work, we propose a memory system architecture that best matches the off-chip memory traffic with the optimum throughput of the computation engine, while it operates at the maximum allowable frequency. With the help of an extended version of the Roofline model proposed in this work, we can estimate memory bandwidth utilization of the system at different operating frequencies since the proposed model considers operating frequency in addition to bandwidth utilization and throughput. In order to find the optimal solution that has the best energy efficiency, we make a trade-off between energy efficiency and computational throughput. This solution saves 18% of energy utilization with the trade-off having less than 2% reduction in throughput performance. We also propose to use a race-to-halt strategy to further improve the energy efficiency of the designed CNN accelerator. Experimental results show that our CNN accelerator can achieve a peak performance of 52.11 GFLOPS and energy efficiency of 10.02 GFLOPS/W on a ZYNQ ZC706 FPGA board running at 250 MHz, which outperforms most previous approaches.

In recent years, digital image forgery detection has become an active research area due to the advancement of photo editing software. This paper focuses on passive forgery detection on images tampered using copy move technique, better known as Copy Move Forgery Detection (CMFD). A CMFD technique consisting of oriented Features from Accelerated Segment Test and rotated Binary Robust Independent Elementary Features (Oriented FAST and rotated BRIEF) as the feature extraction method and 2 Nearest Neighbour (2NN) with Hierarchical Agglomerative Clustering (HAC) as the feature matching method is proposed. Evaluation of the proposed CMFD technique was performed on images that underwent various geometrical attacks. With the proposed technique, an overall accuracy rate of 84.33% and 82.79% are obtained for evaluation carried out with images from the MICC-F600 and MICC-F2000 databases. Forgery detection achieved True Positive Rate of more than 91% for tampered images with object translation, different degree of rotation and enlargement.

Face recognition in video surveillance is challenging as there is no control on the quality of the face image captured especially under uncooperative situations with head pose variation, occlusion, and low-quality image. These issues create large discrepancy between probe and gallery images which affects the performance of recognition. To overcome these issues, pose correction is proposed to narrow the difference between probe and gallery images and image enhancer to highlight face image details. Face representation is improved by creating an average face image to reduce the effect of non-facial details captured such as background, occlusion and noise. The proposed methods are tested on ChokePoint dataset and resulted in improved face recognition.

The high efficiency video compression standard (HEVC) is the latest video engineering marvel that is designed to launch video coding towards the domain of the 8K. This new standard with all the advanced video coding techniques built into it has an overload of computational complexities, which result to very high latency in the encoding process. Mode decision in this standard is one of the units that constitutes a significant fraction of the complexities. This work utilizes prediction residuals in the inter 2N × 2N part mode, in depths two and three, to prune down decisions over the four asymmetric motion partitions in each of these depths. Experimental results show that this algorithm offers a speedup of 72 % at best when linked with the mode decision scheme implemented in HM14 reference software.

Content-based image retrieval methods use color, texture and shape of an object for indexing and retrieval. Among these features, shape is a basic visual feature that holds significant information of the object. In this paper an alphabetic contour-based shape description method is proposed to facilitate shape classification and retrieval. The proposed method breaks down shape's contour into small segments and assigns unique alphabetic symbol for each segment based on its geometrical features. These symbols are used to create feature string which we call it, an alphabet string. The alphabet strings are compared together using dynamic programming during classification. The proposed method was tested on BROWN dataset that consists of occluded, articulated and missing part shapes. Results show the feasibility of the method and highlight its advantages over some state-of-the art methods.

This paper presents two intra prediction algorithms in High Efficiency Video Coding (HEVC) encoder for reducing the computational complexity and increase the encoding speed. The first algorithm takes advantage of the high spatial correlation among neighboring pixels to substitute the reference samples as the first row or first and second rows of the current block to be predicted, while the pixels intensities in the remaining rows or columns as in the case of horizontal predictions, are extrapolated as usual. Secondly, due to spatial correlations in video block data among adjacent blocks, it has been established that the intra prediction mode of the current block has a high probability of being a member of the most probable mode set or a slight variation of one of the most probable modes. These algorithms are combined and implemented on the HM16 reference software, and show speedup of 23.4% and 22.7% in encoding time using the all-intra-main configuration, with minimal reduction in bitrate of 0.21% and 0.22% respectively.

This paper presents the design space exploration of the hardware-based inverse fixed-point integer transform for High Efficiency Video Coding (HEVC). The designs are specified at high-level using CAL dataflow language and automatically synthesized to HDL for FPGA implementation. Several parallel design alternatives are proposed with trade-off between performance and resource. The HEVC transform consists of several independent components from 4x4 to 32x32 discrete cosine transform and 4x4 discrete sine transform. This work explores the strategies to efficiently compute the transforms by applying data parallelism on the different components. Results show that an intermediate version of parallelism, whereby the 4x4 and 8x8 are merged together, and the 16x16 and 32x32 merged together gives the best trade-off between performance and resource. The results presented in this work also give an insight on how the HEVC transform can be designed efficiently in parallel for hardware implementation.