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International audience; Communication on multi-core chips is a severe bottleneck for computational performance. A potential solution, wireless radiofrequency links between far apart cores, suffers from strong multipath effects within the chip package that cause inter-symbol interference. We propose to empower the on-chip propagation environment with in situ programmability by equipping it with a programmable metasurface. By locally tuning the boundary conditions of the metallic enclosure that the chip package constitutes, the programmable metasurface allows us to tailor the on-chip channel impulse response. Our numerical studies suggest that this approach may overcome the caveat of current wireless interconnects. © 2021 IEEE.

Capacitive touchscreens are increasingly widespread, featuring in mobile phones and tablets, as well as everyday objects such as cars and home appliances. As a result, the interfaces are uniquely placed to provide a means of communication in the era of the Internet of Everything. Here we show that commercial touchscreens can be used as reader interfaces for capacitive coupled data transfer. The transfer of data to the touchscreen is achieved using a 12-bit thin-film capacitive radio frequency identification tag powered by a thin-film battery or a thin-film photovoltaic cell that converts light from the screen. The thin-film integrated circuit has a 0.8 cm2 on-chip monolithic antenna, employs 439 transistors, and dissipates only 31 nW of power at a supply voltage of 600 mV. The chip has an asynchronous data rate of up to 36 bps, which is limited by the touchscreen readout electronics. ispartof: NATURE ELECTRONICS vol:2 issue:12 pages:606-611 ispartof: location:England status: published

A 24 GHz antenna design for miniaturized FMCW radar is presented. The antenna was manufactured with additive manufacturing technology at TNO. The characterization of the polymer material used in the fabrication was carried out and the measurement results of the antenna are presented in this work. A good agreement between simulations and measurements was achieved. © 2018 European Microwave Association.

This paper describes a fractional-N PLL IC with absolute phase control utilizing an on-chip loop-filter. The frequency range is 2.6 to 3.5 GHz, which covers one of the bands for future low-band 5G telecommunication systems. For phased-array operation a compact form-factor is needed as the space available for the complete front-end is limited by the wave-length. The on-chip loop-filter allows to obtain the compact form factor required. The absolute phase-control allows for phased-array operation. The chip has been implemented in a mathbf{0.25}mumathbf{m} BiCMOS process. © 2018 European Microwave Association.

This work proposes to reduce energy by avoiding access to columns of on-chip SRAM arrays whose cell contents are all 1s or all 0s. We refer to this dynamic phenomenon as the Same-Cell-Content-Column (SCC-column). Analysis reveals that SCC-columns occur frequently in several processor arrays, such as tag arrays of L1 caches, TLBs and predictors. An interval based scheme that employs one bit per column is proposed to track whether we have a SCC-column. We explain how a SCC-column can be leveraged to reduce the energy needed for SRAM read and write accesses. Experimental analysis for a specific processor configuration reveals that the proposed scheme detects SCC-columns effectively. The potential energy savings of the proposed approach at 32nm often exceeds 40% for several processor arrays. © 2011 IEEE. 181 186 Conference code: 86471 Cited By :3

As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to design processors featuring hundreds of general-purpose cores. However, though a large number of cores speeds up parallel code sections, Amdahl's law requires speeding up sequential sections too. We argue that it will become possible to dedicate a substantial fraction of the chip area and power budget to achieve high sequential performance. Current general-purpose processors contain a handful of cores designed to be continuously active and run in parallel. This leads to power and thermal constraints that limit the core's performance. We propose removing these constraints with a sequential accelerator (SACC). A SACC consists of several cores designed for ultimate sequential performance. These cores cannot run continuously. A single core is active at any time, the rest of the cores are inactive and power-gated. We migrate the execution periodically to another core to spread heat generation uniformly over the whole SACC area, thus addressing the temperature issue. The SACC will be viable only if it yields significant sequential performance. Migration-induced cache misses may limit performance gains. We propose some solutions to mitigate this problem. We also investigate a migration method using thermal sensors, such that the migration interval depends on the ambient temperature and the migration penalty is negligible under normal thermal conditions. © 2010 ACM. 237 246 Sponsors: ACM SIGMicro Conference code: 80973 Cited By :2