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Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

This paper aims to develop a new efficient framework named Secure Decentralized Training Framework (SDTF) for Privacy Preserving Deep Learning models. The main feature of the proposed framework is its capable of working on a decentralized network setting that does not need a trusted third-party server while simultaneously ensuring the privacy of local data with a low cost of communication bandwidth. Particularly, we first propose a so-called Efficient Secure Sum Protocol (ESSP) that enables a large group of parties to jointly calculate a sum of private inputs. ESSP can work not only with integer number but also with floating point number without any data conversion. We then propose a Secure Model Sharing Protocol that enables a group of parties securely train and share the local models to be aggregated into a global model. Secure Model Sharing Protocol exploits randomization techniques and ESSP to protect local models from any honest-but-curious party even n - 2 of n parties colluding. Eventually, these protocols are employed for collaborative training decentralized deep learning models. We conduct theoretical evaluation of privacy and communication cost as well as empirical experiments on balance class image datasets (MNIST) and an unbalance class text dataset (UCI SMS Spam). These experiments demonstrate the proposed approach can obtain high accuracy (i.e. 97% baseline accuracy in only 10 training rounds with MNIST, 100 training rounds with SMS Spam) and robust to the heterogeneity decentralized network, with non-IID and unbalance data distributions. We also show a reduction in required rounds of training to achieve the accuracy baseline by 5 × as compared to Downpour SGD. It is shown that the proposed approach can achieve both the privacy at the level of cryptographic approaches and efficiency at the level of randomization techniques, while it also retains higher model’s utility than differential privacy approaches.

In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and operating phases, most of the existing methods use a dedicated testing mechanism with long response time and prerequisite interruptions for online testing. This article presents an error correction code (ECC)-based method named “TSV on-communication test” (TSV-OCT) to detect and localize faults without halting the operation of TSV-based 3-D-IC systems. We first propose a statistical detector, a method to detect open and short defects in TSVs that work in parallel with data transactions. Second, we propose an isolation-and-check algorithm to enhance the localization ability of the method. Moreover, the Monte Carlo simulations show that the proposed statistical detector increases $\times 2$ the number of detected faults when compared to conventional ECC-based techniques. With the help of isolation and check, TSV-OCT localizes the number of defects up to $\times 4$ and $\times 5$ higher. In addition, the response time is kept below 65 000 cycles, which could be easily integrated into real-time applications. On the other hand, an implementation of TSV-OCT on a 3-D Network-on-Chip (NoC) router shows no performance degradation for testing while having a reasonable area overhead.

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

This paper deals with the large category of convex optimization problems on the framework of second-order multi-agent systems, where each distinct agent is assigned with a local objective function, and the overall optimization problem is defined as minimizing the sum of all the local objective functions. To solve this problem, two distributed optimization algorithms are proposed, namely, a time-triggered algorithm and an event-triggered algorithm, to make all agents converge to the optimal solution of the optimization problem cooperatively. The main advantage of our algorithms is to remove unnecessary communications, and hence reduce communication costs and energy consumptions in real-time applications. Moreover, in the proposed algorithms, each agent uses only the position information from its neighbors. With the design of the Lyapunov function, the criteria about the controller parameters are derived to ensure the algorithms converge to the optimal solution. Finally, numerical examples are given to illustrate the effectiveness of the proposed algorithms.

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

Nowadays, the Internet of Things (IoT) has been a focus of research that improves and optimizes our daily life based on intelligent sensors and smart objects working together. Thanks to Internet Protocol connectivity, devices can be connected to the Internet, thus allowing them to be read, controlled, and managed at any time and at any place. Security and privacy are the key issues for deploying IoT applications, and still face some enormous challenges; especially, for devices that require high throughput and low latency as IoT cameras, IoT gateways, high-quality video conferencing systems… In this paper, we proposed a 10-cores AES hardware architecture to achieve high throughput. These cores shared KeyExpansion Block so this architecture has high efficiency in term of area and power consumption. Fully parallel, outer round pipeline technique is also used to achieve low latency. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. On the other hand, clock gating technique is used to save power consumption. We use PrimeTime tool (Synopsys) to estimate the power consumption. Implementation results show that the proposed architecture achieves a throughput of 853.8 Gbps at the maximum operating frequency of 667 MHz and clock gating technique allows more power savings.

The Internet of Things (IoT) with the advancements of many technologies opens a wide range of new applications such as smart appliances, smart cities and smart grids. Despite its popularity and usability, it also creates a new attack surface for the hackers especially on highly constrained devices which have limited memory footprints and processing power. These constrained devices often use Authenticated Encryption with Associated Data (AEAD) to secure data stored in the devices and transmitted over the network. In this work, we design a lightweight data encryption core in hardware with the support for AEAD to secure IoT applications on highly constrained devices. The design achieves a low area cost with only 23kGEs in TSMC 65nm technology and an encryption throughput of 123Mbps at 60MHz.

Thermal dissipation is one of the most critical challenges for stacking 3D-ICs, where the heat cannot easily transfer through several layers of silicon. As the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s mode [1], stacking 3D-ICs also confront the reliability threat. Notably, Copper has a higher activation energy than CMOS, which makes Copper Through-Silicon-Vias vulnerable with the thermal-accelerated failure. Therefore, this paper presents a platform where we investigate the thermal distribution, predict the reliability, and propose a method for efficiently insert spare TSVs to ensure lifetime reliability. To demonstrate our platform, we apply a TSV-based 3D-NoC (3D Network-on-Chip) under the PARSEC benchmarks. We also illustrate the thermal-aware TSV redundancies insertion using grid search and genetic algorithm to balance the number of TSVs and the target MTTF.

The aim of this paper is to study the distributed optimization problem for continuous-time multi-agent systems with the existence and the interference of external disturbance, therein each agent is described as double-integrator dynamic. To reject the exogenous disturbance, the distributed algorithm is proposed for each agent based on the internal model principle. The proposed algorithm only utilizes the position information of each agent from its neighbors subject to the undirected graph, which can reduce communication costs and energy consumptions in applications. Moreover, the algorithm only needs the cost functions of the agent itself, which can greatly protect the privacy of other agents. The optimal solution of the problem is thus obtained with the design of Lyapunov function and the help of convex analysis, LaSallel’s Invariance Principle. Finally, two numerical simulation examples and the comparison of proposed algorithm with other previous research are presented to illustrate the persuasive effectiveness of the theoretical result.

The component’s failure in network-on-chips (NoCs) has been a critical factor on the system’s reliability. In order to alleviate the impact of faults, fault tolerance has been investigated in the recent years to enhance NoC’s robustness. Due to the vast selection of fault-tolerance mechanisms and critical design constraints, selecting and configuring an appropriate mechanism to satisfy the fault-tolerance requirements constitute new challenges for designers. Consequently, reliability assessment has become prominent for the early stages of manufacturing process to solve these problems. This paper approaches the fault-tolerance analysis by providing an analytical model to approximate the lifetime reliability and compares it with a system-level simulation. Based on the proposed approach, we measure the fault-tolerance efficiency using a new parameter, named reliability acceleration factor. The goal of this paper is to provide an efficient and accurate reliability assessment to help designers easily understand and evaluate the advantages and drawbacks of their potential fault-tolerance methods.

This paper investigates the distributed optimisation problem for the multi-agent systems (MASs) with the simultaneous presence of external disturbance and the communication delay. To solve this problem, a two-step design scheme is introduced. In the first step, based on the internal model principle, the internal model term is constructed to compensate the disturbance asymptotically. In the second step, a distributed optimisation algorithm is designed to solve the distributed optimisation problem based on the MASs with the simultaneous presence of disturbance and communication delay. Moreover, in the proposed algorithm, each agent interacts with its neighbours through the connected topology and the delay occurs during the information exchange. By utilising Lyapunov–Krasovskii functional, the delay-dependent conditions are derived for both slowly and fast time-varying delay, respectively, to ensure the convergence of the algorithm to the optimal solution of the optimisation problem. Several numerica...

In this study, the distributed optimisation problem is investigated by using the framework of second-order multi-agent systems (MASs) over a directed communication topology. A distributed algorithm is proposed for the MASs to seek the solution of the optimisation problem. The proposed algorithm contains two layers, the cooperative compensator and the local optimiser, where the former layer is to compensate the cooperative errors and the latter will lead the agents to the optimal solution. In the algorithm, each agent only uses the position information from its neighbours in the presence of delay. By utilising the Lyapunov–Krasovskii functional, delay-dependent conditions are derived for the slowly-varying and fast-varying delays, respectively, to guarantee the algorithm converges to the optimal solution. Furthermore, a criterion on solving the optimisation problem through the MASs with discrete-time communication is also proposed directly from the result of the fast-varying delay. Finally, a numerical simulation example is presented to illustrate the persuasive effectiveness of the theoretical results.

This paper aims at studying the factors affecting green banking practices in Vietnam and the role of green banking in sustainable development of the Vietnamese economy. A large scale survey con-ducted with 32 banks and financial organizations in Vietnam to obtain 329 questionnaire forms in the period from May to July 2016 provides evidence for the research. By using EFA analysis and the regression model, we find that understanding the definitions of green banking, the current activities of green banking, the advantages in developing green banking, and the focused sectors have positive relationships with the willingness of Vietnamese banks to adopt green banking practices, whereas the barriers have negative relation-ships with the willingness to utilize green banking services among Vietnamese banks. From the research findings, we suggest some solutions to not only enhance the understanding of the importance of green banking in economic development but also improve the willingness to follow green banking practices among Vietnam’s banking institutions.

LED is an ultra-lightweight block cipher targeting resource-constrained devices. The current hardware architectures of this cipher utilize large logic area, operate in low frequencies and have low throughput. To improve the trade-offs between area utilization and performance, an iterative round-based architecture of LED block cipher is implemented in this paper. LED algorithm is available in 64-bit and 128-bit key sizes. In this paper, the focus is on the 64-bit key with 64-bit block size. This algorithm is implemented on various Field Programmable Gate Array (FPGA) devices. The design is verified on several Altera and Xilinx devices using Altera Quartus II, ModelSim and Xilinx ISE simulators. Both low-cost and high-end FPGA devices were targeted. Tradeoffs between area and performance were considered, with the optimization for performance. The throughput and maximum operating frequency are benchmarked with the existing literature and better performance is achieved. The results show large improvements in maximum operating frequency and throughput as well as reduction in area utilization compared to recent designs of round-based LED block cipher.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.

Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 242kb SRAMs.

Deep Neural Network (DNN) architectures have been recently considered as the big breakthrough for a variety of applications. Because of the high computing capabilities required, DNN has been unsuitable for various embedded applications. Many works have been trying to optimize the key operations, which are multiply-and-add, in hardware for a smaller area, higher throughput, and lower power consumption. One way to optimize these factors is to use the reduced bit accuracy; for examples, Google's TPU used only 8-bit integer operations for DNN inference. Based on the characteristics of different layers in DNN, further bit accuracy can be changed to preserve the hardware area, power consumption, and throughput. In this work, the thesis investigates a hardware implementation of multiply-and-add with variable bit precision which can be adjusted at the computation time. The proposed design can calculate the sum of several products with the bit precision ranging from 1 to 16 bits. The hardware implementation results on Xilinx FPGA Virtex 707 development kit show that our design occupies smaller hardware and can run at a higher frequency of 310 MHz, while the same functionality implemented with and without DSP48 blocks can only run at a frequency of 102 MHz. In addition, to demonstrate that the proposed design is applicable effectively for deep neural network architecture, the paper also integrated the new design in the MNIST network. The simulation and verification results show that the proposed system can achieve the accuracy up of to 88%.

In this paper, we propose a high-throughput and low-latency AES architecture for wideband and real-time applications such as surveillance cameras, video conference, motion detection, IoT gateways, data store encryption… Our design uses an outer round pipeline technique to achieve high throughput. The design has been modelled in RTL VHDL and then synthesized with a 45nm CMOS technology using Synopsys Design Compiler. The implementation results show that the proposed architecture achieves a throughput of 111.3Gbps and a latency of 12.6ns at the maximum operating frequency of 870MHz. With the same 45nm CMOS technology, our design has area efficiency (2.4 times) and energy efficiency (4.7 times) higher than other related works.

In this paper, we present two different approaches to design a driver for high gain Doherty power amplifiers (DPAs): single driver and dual-driver topologies. Detailed analysis and quantitative comparison between the two approaches are proposed. In particular, the single driver topology is preferred when the output Doherty stage has a reasonable gain. On the other hand, when the output stage has low gain, the dual driver approach is required to prevent significant efficiency reduction. Two DPA circuits at two different frequency ranges have been fabricated in a 0.15-μm Gallium Arsenide (GaAs) process to verify the concept. The single driver DPA at 10 GHz achieves at a measured gain of 19.2 dB and the maximum power of 27 dBm. The peak power added efficiency (PAE) and PAE at 6-dB power back-off (PBO) are 43% and 32%, respectively. On the other hand, the dual driver DPA at 28 GHz exhibits 15 dB of gain, 28.2 dBm output power with an associated peak PAE of 37%. To the best of the authors’ knowledge, our DPA prototypes achieve the highest gain of all reported DPAs at similar frequency ranges.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs); however, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are threating TSV-based 3D-ICs. On the other hand, real-time applications demand short response time to the new occurrence faults which make online testing become a critical challenge. In order to solve this problem, this paper presents an online method named TSV-IaS which supports detecting and correcting open and short defect TSVs by isolating and shifting the signals of TSVs then analyzing the output syndromes. Furthermore, we also present an analytical analysis on detectability and response time of the proposal. Results show that with R redundant TSVs in a group, the proposed method can fully correct R defects and detect R+1 defects while keeping a low-cost structure. Monte-Carlo simulations also demonstrate a 100% detection rate with 32-cycles based tests.

A compact wideband Ka-band monolithic microwave/ millimeter-wave integrated circuit (MMIC) power amplifier (PA) is demonstrated using a 0.15-μm pseudomorphic high electron mobility transistor (pHEMT) Gallium Arsenide (GaAs) process. The proposed harmonic load-pull and radial stub matching technique have been employed to achieve wideband and high-efficiency performance. The fabricated PA exhibits a measured output power of 24 dBm, gain of 20 dB and 35% power added efficiency (PAE). The PA has a wideband performance in which the power maintains higher than 23 dBm, and the PAE is higher than 30% over a wide frequency range from 25 to 34 GHz.

The Internet of Things (IoT) is shaping a world where devices are increasingly interconnected, cheaper, and ubiquitous. The more we move toward this world, the more cybersecurity becomes paramount. Nevertheless, we argue that there exists a category of IoT devices which commonly overlooks security, despite dealing with sensitive information. In order to demonstrate this, in this work, we present the results of the security assessments we performed on two IoT devices that we consider emblematic of such category: the Rohs K88h smartwatch and the Sricam SP009 IP camera. The results demonstrate the existence of critical vulnerabilities that could be easily exploited, even by non-expert attackers, for extracting sensitive information and severely impacting on user’s privacy.

Advanced SIMD features on GPUs and Xeon Phis promote efficient long pattern search.A tiled approach to accelerating the Wu-Manber algorithm on GPUs has been proposed.Both the GPU and Xeon Phi yield two orders-of-magnitude speedup over one CPU core.The GPU-based version with tiling runs up to 2.9 × faster than the Xeon Phi version. Approximate pattern matching (APM) targets to find the occurrences of a pattern inside a subject text allowing a limited number of errors. It has been widely used in many application areas such as bioinformatics and information retrieval. Bit-parallel APM takes advantage of the intrinsic parallelism of bitwise operations inside a machine word. This approach typically encodes non-deterministic finite automaton (NFA) states or value differences between adjacent cells of a dynamic programming matrix in the form of bit arrays. Wu-Manber (WM) is a well-known bit-parallel APM algorithm, which simulates an NFA and gains parallel efficiency by performing multiple state updates within a machine word. An important parameter is the machine word size (e.g. 32 or 64?bits for CPUs). Due to increasing vector capabilities, efficient mapping of bit-parallel APM algorithms onto modern high performance computing architectures is an interesting research topic. Prominent examples are Xeon Phi coprocessors and CUDA-enabled GPUs, which provide words of size 512?bits (by means of vector registers) and 1024?bits (by means of warps), respectively. In this paper, we investigate mappings of the WM algorithm onto these two accelerator types. Both architectures are able to achieve around two orders-of-magnitude speedups compared to a single-threaded CPU implementation. Moreover, our tile-based implementation on a GeForce Titan graphics card runs up to 2.9 × faster than our implementation on an Intel Xeon Phi 5110P. Source code is available at http://xbitpar.sourceforge.net.

This paper presents a low energy AES encryption core targeting for hardware security implementation in IoT systems. The proposed AES core architecture employs the improved shared S-box scheme with 32-bit datapath and low switching activity shift-row operation. Consequently, the proposed AES encryption core can provide good tradeoff with the area of 4.3 kgates and the energy consumption of 4 pJ/bit in 32 nm CMOS technology library.

The Network-on-Chip (NoC) paradigm has been emerging as new communication solution for the Ultra Large-Scale Integration System-on-Chips (SoCs). Many real-time embedded SoCs support multi-rate applications that requires the NoC has to offer different Quality-of-Service level. This paper proposes and implements a reconfigurable hybrid router that combines the hybrid switching scheme with the priority-driven arbitration mechanism. The router supports both guaranteed-throughput (GT) service and best-effort (BE) service without reserving resources for GT service. In addition, the proposed solution not only guarantees GT-type QoS, but also enhance the average performance for BE service by using communication resources efficiently. The router has been modelled and then implemented on Xilinx Virtex-7 FPGA technology. The obtained results show that this router can guarantee reliability and enhance significantly the average performance of BE load compared with the generic router while the overheads in terms of area and power consumption are acceptable.

International audience; Connected devices are getting attention because of the lack of security mechanisms in current Internet-of-Thing (IoT) products. The security can be enhanced by using standardized and proven-secure block ciphers as advanced encryption standard (AES) for data encryption and authentication. However, these security functions take a large amount of processing power and power/energy consumption. In this paper, we present our hardware optimization strategies for AES for high-speed ultralow-power ultralow-energy IoT applications with multiple levels of security. Our design supports multiple security levels through different key sizes, power and energy optimization for both datapath and key expansion. The estimated power results show that our implementation may achieve an energy per bit comparable with the lightweight standardized algorithm PRESENT of less than 1 pJ/b at 10 MHz at 0.6 V with throughput of 28 Mb/s in ST FDSOI 28-nm technology. In terms of security evaluation, our proposed datapath, 32-b key out of 128 b cannot be revealed by correlation power analysis attack using less than 20 000 traces.

In this paper, the process of building the controller for an EPS system is investigated based on the fuzzy logic. Unlike the tradition PI controller, the fuzzy controllers have a good control effect for the nonlinear and time-varying systems. Motivated by this observation, this paper designs the fuzzy-PI controller for an EPS system. In proposed control strategy, we establish the fuzzy-PI closed-loop control law, which aims that the actual current of the motor is accurately tracking of motor target current. To obtain this problem, we combine the current deviation and the deviation rate of current change to design the fuzzy controller for adjusting the online of PI parameters. Therefore, our control strategy can overcome the limitation of conventional PI controller with the fixing parameters. In addition, the mathematical model of the column-type EPS system is built through the dynamic analysis. Finally, to demonstrate the advantages for the proposed control method, the simulation model is established according to the Matlab/Simulink with CarSim. The simulation results indicate that the control method proposed in this paper is effective than that of the tradition PI controller.

In this paper, the distributed optimization problem is investigated under a second-order multi-agent system. In the proposed algorithm, each agent solves the optimization via local computation and information exchange with its neighbors through the communication topology. However, in comparison with the existing second-order distributed optimization algorithms, the proposed algorithm is much simpler due to one coupled information exchange among the agents is reduced. To achieve the optimization, the distributed algorithm is proposed based on the consensus method and the gradient algorithm. The optimal solution of the problem is thus obtained with the design of Lyapunov function and the help of LaSallel's Invariance Principle. A numerical simulation example and comparison of proposed algorithm with existing works are presented to illustrate the effectiveness of the theoretical result.

Dynamic Voltage and Frequency Scaling (DVFS) has been known as an efficient technique to reduce the power consumption of a Network-on-Chip (NoC). An important question in DVFS is how to change the voltage and frequency adaptable to the required performance of the system at run-time while reducing the power consumption as much as possible. Another problem is how a tool could quickly and efficiently validate or reject a NoC architecture employing DVFS. By integrating the Orion 2 power model, VNOC 2.0 simulator can be used as either a NoC simulation tool or a platform for implementing and investigating DVFS ideas. In this paper, we focus on developing a new solution for NoC architectures to save energy using fuzzy-logic algorithms. A controller is designed to predict the change of traffic load based on the fuzzy logic algorithm, then adjusts the voltage and frequency correspondingly to minimize the power consumption while keeping the performance of the whole system. An estimation of power consumption has been done by using VNOC 2.0 simulator. The simulation results show that our model can save up to 46% the power consumption of a 8×8 NoC.

This study contributes to the realization of intended nationally determined contributions (INDCs) by analyzing their implications for the energy production system and the economy and determines the role of renewable energies (RE) in reducing the challenge of committing to the INDCs. The Asia-Pacific Integrated Model/Computable General Equilibrium (AIM/CGE) model was used to assess seven scenarios having the same socioeconomic development but different shares of RE in power generation. By comparing different relative reductions caused by the emission constraints vis-a-vis the business-as-usual (BaU) scenario, the mitigation costs can be estimated. Results show that the economic impact could be reduced by around 55% in terms of welfare loss (from 6.0 to 2.7%) and by around 36% in terms of gross domestic product (GDP) loss (from 3.4 to 2.1%) through the incorporation of high levels of renewable energy. Furthermore, the additional double deployment of wind and SPV to 5.4% and 12.0%, respectively, which currently comprise 43.1% of the renewable energies used in electricity generation, could reduce the GDP loss from 2.1 to 1.9% and reduce the welfare loss from 2.7 to 1.5% in order to achieve a 25.0% GHG emissions reduction. These losses are less than those in the pricing-only scenario (2.1% and 2.3%, respectively).

Network-on-Chip (NoC) paradigm allows designers to integrate efficiently more intellectual properties (IPs) into a single chip system. However, the power consumption has become one of the most critical issues for designing such large complex systems. Low power design can be achieved by scaling the voltage and frequency of the target components. The question is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time while reducing as much as possible the power consumption. This paper presents a novel solution for NoC architectures to reduce power consumption using fuzzy-logic algorithms. As the communication traffic is not equally distributed over the network architecture, depending on the communication load, each router in the network will be applied with a corresponding voltage and frequency to minimize the power consumption while keeping necessary communication throughput.

Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.

Quantum neural networks (QNNs) have been explored as one of the best approach for improving the computational efficiency of neural networks. Because of the powerful and fantastic performance of quantum computation, some researchers have begun considering the implications of quantum computation on the field of artificial neural networks (ANNs).The purpose of this paper is to introduce an application of QNNs in construction of cryptography system in which two networks exchange their outputs (in qubits) and the key to be synchronized between two communicating parties. This system is based on multilayer qubit QNNs trained with back-propagation algorithm.

In this paper, distributed optimization problem is investigated under a second-order multi-agent network, in which each agent is described as the double integrator. The multi-agent network is introduced for solving a large scale optimization problem by the cooperation of coupled agents. Based on the interaction over the network, the optimal solution of the problem can be obtained. Since the existing distributed algorithms for second-order multi-agent network enforce each agent to transmit complete information (both state information and derivation information of the independent variable, i.e., corresponded position and velocity information of the agent), this paper is motivated to design the distributed algorithm with only using the position information of neighbors, which reduces the requirement on communication bandwidth. With the help of Lyapunov analysis and LaSallel's Invariance Principle, the optimal solution is derived and the optimization problem is solved via the second-order multi-agent network. Finally, a numerical example is presented to illustrate the theoretical result.

As the rapid advancement in semiconductor technology leads to shrinking of transistor sizes and the integration scale is over one billion transistors, Reconfigurable Network-on-Chips becomes a new methodology providing adaptive infrastructure resources as well as flexible network protocols to adapt to dynamic environment. In this paper, we propose a routing-path tracking and updating mechanism for reconfigurable Network-on-Chips. The hardware architectures used to implement the proposed mechanism such as modified RNoC routers and Network Interfaces are introduced. With this routing-path tracking and updating mechanism, packet transmission delay can be reduced from 4.92% to 33.33% depending on the data structures.

In this paper, we propose a novel AES microarchitecture with 32-bit datapath optimized for low-power and low-energy consumption targeting IoT applications. The proposed design uses simple shift registers for key/data storage and permutation to minimize the area, and the power/energy consumption. These shift registers also minimize the control logics in the key expansion and the encryption path. The proposed architecture is further optimized for area and/or power/energy consumption by selecting a suitable implementation of S-boxes and applying the clock gating technique. The implementation results in TSMC 65nm technology show that our design can save 20% of area or 20% of energy per bit at the same area when compared with the current 32-bit datapath designs. Our design also occupies smaller core area with lower energy per bit and at least 4 times higher in throughput in comparison with other 8-bit designs in the same technology node.

International audience; Text matching with errors is a regular task in computational biology. We present an extension of the bit-parallel Wu-Manber algorithm to combine several searches for a pattern into a collection of fixed-length words. We further present an OpenCL parallelization of a redundant index on massively parallel multicore processors, within a framework of searching for similarities with seed-based heuristics. We successfully implemented and ran our algorithms on GPU and multicore CPU. Some speedups obtained are more than 60x.

Asynchronous design offers an attractive solution to address the problems faced by networks-on-chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market because of a lack of testing methodology and support. This study first presents the design and implementation of a design-for-test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

International audience; VLSI designers recently have adopted micro network-on-chip (or NoC) as an emerged solution to design complex SoC system under stringent constraints pertaining cost, size, power consumption, and short time-to-market. Characterization of on-chip traffics and traffic-performance evaluation are necessary steps bringing comprehensive and effective NoC design. This paper presents an analysis and performance evaluation framework of backtracked routing Network-on-Chip that provides guaranteed and energy-efficient data transfer. Experimental results, under common and application-oriented synthetic traffics, figure out the performance in terms of latency and throughput and suggest a tradeoff to developers to map applications into a proposed NoC platform.

International audience; Asynchronous design offers an attractive solution to overcome the problems faced by Networks-on-Chip (NoC) designers such as timing constraints. Nevertheless, postfabrication testing is a big challenge to bring the asynchronous NoCs to the market due to a lack of testing methodology and support. This paper first presents the design and implementation of a Design-for-Test (DfT) architecture, which improves the testability of an asynchronous NoC architecture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.

9 pages; International audience; The Networks on Chip (NoCs) paradigm has recently emerged as an alternative solution for large complex SoCs' communication. Despite having many attractive attributes, NoCs design has also lots of challenges. One of the challenges is testing network architectures (routers and communication channels) for manufacturing defects, especially, the test of asynchronous NoCs. To improve the testability of asynchronous NoCs, we have developed a scalable and configurable fully asynchronous Design-for-Test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused as a high throughput Test Access Mechanism (TAM). This paper presents the realization and implementation of this DfT architecture. The validation and experimental results are also presented.

International audience; The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANOC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also given

International audience; Thanks to many advantages, asynchronous circuits have been used to solve the interconnect problems faced by system–on–chip (SoC) designers. Some asynchronous Networks–on–Chip (NoCs) architectures are proposed for the communication within SoCs, but lack of methodology and support formanufacture testing to ensure these communication architectures work correctly. In this paper, we present an innovative asynchronous DFT architecture that allows testing the asynchronous communication network architectures, as well as the synchronous computing resources and the asynchronous/synchronous network interfaces on the asynchronous NoC–based SoCs. This asynchronous DFT architecture is implemented in Quasi Delay Insensitive (QDI) asynchronous circuits and uses an area of about 20 8 Kgates in an asynchronous NoC–based SoC of 4.5 Mgates without memories.