1. Tunneling-based CMOS Floating Gate Synapse for Low Power Spike Timing Dependent Plasticity
- Author
-
Fabio Toso, Michele Mastella, Giuseppe Sciortino, Enrico Prati, and Giorgio Ferrari
- Subjects
0209 industrial biotechnology ,Computer science ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,spiking ,STDP ,Synapse ,Synaptic weight ,020901 industrial engineering & automation ,synapse ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,medicine ,Electronic engineering ,Hardware_ARITHMETICANDLOGICSTRUCTURES ,floating gate ,Very-large-scale integration ,Spiking neural network ,Spike-timing-dependent plasticity ,VLSI ,medicine.anatomical_structure ,CMOS ,Logic gate ,Voltage spike ,020201 artificial intelligence & image processing ,Node (circuits) ,Neuron ,Hardware_LOGICDESIGN - Abstract
We propose a CMOS architecture for spiking neural networks with permanent memory and online learning. It uses a three-transistors synapse with a floating node that stores the synaptic weight, programmed by using only Fowler-Nordheim tunneling current in the pA range for ultra-low power operation. A neuron with a conditioning circuit programs the floating gate synapse following the spike timing dependent plasticity rule. Simulations using a standard 150 nm CMOS process show the online learning capabilities of the architecture.
- Published
- 2020