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This article presents the design and efficient hardware implementation of binarized neural networks (BNNs) for brain-implantable neural spike sorting. In contrast to the conventional artificial neural networks (ANNs), in which the weights and activation functions of neurons are represented using real values, the BNNs utilize binarized weights and activation functions to dramatically reduce the memory requirement and computational complexity of the ANNs. The designed BNN is trained using several realistic neural datasets to verify its accuracy for neural spike sorting. The application-specific integrated circuit (ASIC) implementation of the designed BNN in a standard 0.18- $\mu \text{m}$ CMOS process occupies 0.33 mm 2 of silicon area. Power consumption estimation of the ASIC layout shows that the BNN dissipates $2.02~\mu \text{W}$ of power from a 1.8 V supply while operating at 24 kHz. The designed BNN-based spike sorting system is also implemented on a field-programmable gate array and is shown to reduce the required on-chip memory by 89% compared to those of the alternative state-of-the-art spike sorting systems. To the best of our knowledge, this is the first work employing BNNs for real-time in vivo neural spike sorting.

This article presents the design and implementation of an embedded programmable processor with a custom instruction set architecture for efficient realization of artificial neural networks (ANNs). The ANN processor architecture is scalable, supporting an arbitrary number of layers and number of artificial neurons (ANs) per layer. Moreover, the processor supports ANNs with arbitrary interconnect structures among ANs to realize both feed-forward and dynamic recurrent networks. The processor architecture is customizable in which the numerical representation of inputs, outputs, and signals among ANs can be parameterized to an arbitrary fixed-point format. An ASIC implementation of the designed programmable ANN processor for networks with up to 512 ANs and 262,000 interconnects is presented and is estimated to occupy 2.23 mm2 of silicon area and consume 1.25 mW of power from a 1.6 V supply while operating at 74 MHz in a standard 32-nm CMOS technology. In order to assess and compare the efficiency of the designed ANN processor, we have designed and implemented a dedicated reconfigurable hardware architecture for the direct realization of ANNs. Characteristics and implementation results of the designed programmable ANN processor and the dedicated ANN hardware on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented and compared using two benchmarks, the MNIST benchmark using a feed-forward ANN and a movie review sentiment analysis benchmark using a recurrent neural network.

In this paper, we investigate the use of monofacial PV models to simulate the production of bifacial PV systems over different albedos. Analytical and empirical models were evaluated using measured data obtained from three identical bifacial PV arrays: (1) with the backside covered by white plastic, (2) with normal albedo, and (3) with high albedo. The front-and rear-side irradiances were measured in order to integrate bifaciality of the modules into the models. The models showed good performance for non-real-time monitoring, especially under clear skies, and the analytical model was more accurate than the empirical model. The heatmap visualization technique was applied to six months of data in order to investigate the site conditions on the rear side of the modules as well as the accuracy of the models. The heatmap results of the rear- and front-sides irradiances showed that the installation conditions, such as the azimuth angles of the sun and the surrounding obstacles, had a strong impact on the energy received from the back of the modules. The heatmap results of the models validated the performance of the analytical model. The average daily errors for the analytical model were less than 1% and 3% for normal and high albedos, respectively. This work was supported by the SUDOKET SOE2/P1/E0677 project funded by FEDER of the EU under the Interreg-Sudoe program. The research leading to these results received funding from the European Union’s Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement No. 712949 (TECNIOspring PLUS) and from the Agency for Business Competitiveness of the Government of Catalonia.

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

This study presents two hardware architectures for the efficient implementation of fast Fourier transform (FFT) based on the combined Good–Thomas and Winograd Fourier transform algorithms. The combined algorithms require fewer multiplications compared with the other FFT algorithms by eliminating twiddle factor multiplications. Two hardware architectures are presented: one is a fully-pipelined architecture using multi-dimensional Chinese remainder theorem for a high-throughput implementation and the other is a time-multiplexed architecture, which utilises the folding transformation for the compact realisation of short-length Winograd Fourier transforms. Both designs are fully-parameterisable and have been verified against their synthesisable Verilog descriptions. The characteristics and the implementation results of the two hardware architectures on a Xilinx field-programmable gate array are presented. To the best of the authors' knowledge, this study presents the first hardware realisation of FFT based on the combined Good–Thomas and Winograd FFT algorithms. The application of the proposed FFT architectures in the physical layer of the long-term evolution wireless standard is discussed.

Resumen El ambiente térmico en una edificación influye en la salud, el bienestar y la productividad de las personas, así como en el consumo energético. La importancia del confort térmico en las edificaciones se reconoce desde hace décadas, no obstante, este aspecto es aún incipiente en la industria de la construcción colombiana, sobre todo en proyectos de vivienda. En esta investigación se analizó el desempeño térmico de tres tipos de vivienda comunes en la ciudad de Medellín. Para ello se calculó la temperatura operativa, el voto medio estimado (PMV) y el porcentaje estimado de insatisfechos (PPD), de acuerdo con la norma ISO 7730:2005. Los resultados mostraron que la inercia térmica de dos de los tres tipos de vivienda examinados no es suficiente para ofrecer un confort térmico adecuado, a pesar del clima templado del Valle de Aburrá. Estos resultados alertan sobre la vulnerabilidad de la población urbana en Colombia ante fluctuaciones extremas de temperatura. Abstract The indoor thermal environment of buildings influences people's health, well-being and productivity, as well as energy consumption. The importance of thermal comfort in buildings has been recognized for decades. However, this aspect is still incipient in the Colombian construction industry, especially in housing projects. In this research, the thermal performance of three common housing types in the city of Medellin was analyzed. To do this, the operative temperature, the predicted mean vote (PMV) and the predicted percentage of dissatisfied (PPD) were calculated in accordance with ISO 7730:2005. The results showed that the thermal inertia of two of the three types of housing examined was insufficient to offer adequate thermal conditions, despite the temperate climate of the Aburra Valley. These results warn about the vulnerability of urban population in Colombia to extreme temperature fluctuations. Resumo O ambiente térmico em uma construção influencia na saúde, no bem-estar e na produtividade das pessoas, bem como no consumo energético. A importância do conforto térmico nas edificações é reconhecida há décadas, não obstante, esse aspecto ainda é incipiente na indústria da construção colombiana, sobretudo em projetos de habitação. Nesta pesquisa, o desempenho térmico de três tipos de habitação comuns na cidade de Medellín foi analisado. Para isso, calculou-se a temperatura operativa, o voto médio estimado (PMV) e a porcentagem estimada de insatisfeitos (PPD), de acordo com a norma ISO 7730:2005. Os resultados mostraram que a inércia térmica de dois dos três tipos de habitação examinados não é suficiente para oferecer um conforto térmico adequado, apesar do clima ameno do Valle de Aburrá. Esses resultados alertam sobre a vulnerabilidade da população urbana na Colômbia ante oscilações extremas de temperatura.

This article presents an efficient design and implementation of a real-time spike sorting system using unsupervised clustering. We utilize the online sorting (OSort) algorithm and model it first in both floating-point and fixed-point numerical representations to accurately assess the feasibility of our hardware architecture and also reliably analyze the sorting accuracy. For efficient hardware realization of OSort, we propose a modified parallel OSort algorithm. By reducing the number of required memory accesses, the number of computations performed for the management and upkeep of cluster averages and cluster merging is substantially reduced. By limiting the number of supported clusters per channel, the classification/clustering latency is significantly reduced compared to the previously published work, making the designed OSort system applicable for in-vivo spike sorting. The proposed OSort hardware architecture utilizes a novel memory configuration scheme to parallelize the OSort algorithm, which allows us to avoid using relatively large memory queues for storing detected spike waveforms and process them concurrently to the spike cluster management. The characteristics and implementation results of the designed OSort-based spike sorting system on a Xilinx Artix-7 field-programmable gate array (FPGA) are presented. The ASIC implementation of the designed system is estimated to occupy 2.57 mm2 in a standard 32-nm CMOS process. Post-layout power estimation shows that the ASIC will dissipate 2.78 mW, while operating at 24 kHz.

One challenge present in brain-computer interface (BCI) circuits is finding a balance between real-time on-chip processing in-vivo and wireless transmission of neural signals for off-chip in-silico processing. This article presents three potential frameworks for investigating an area- and energy-efficient realization of BCI circuits. The first framework performs spike detection on the filtered neural signal on a brain-implantable chip and only transmits detected spikes wirelessly for offline classification and decoding. The second framework performs in-vivo compression of the on-chip detected spikes prior to wireless transmission for substantially reducing wireless transmission overhead. The third framework performs spike sorting in-vivo on the brain-implantable chip to classify detected spikes on-chip and hence, even further reducing wireless data transmission rate at the expense of more signal processing. To alleviate the on-chip computation of spike sorting and also utilizing a more area- and energy-effective design, this work employs, for the first time, to the best of our knowledge, an artificial neural network (ANN) instead of using relatively computationally-intensive conventional spike sorting algorithms. The ASIC implementation results of the designed frameworks are presented and their feasibility for efficient in-vivo processing of neural signals is discussed. Compared to the previously-published BCI systems, the presented frameworks reduce the area and power consumption of implantable circuits.

This paper presents an efficient hardware architecture for the design and implementation of a spike sorting system using online template matching. Over the past decade, various spike sorting algorithms have been proposed; however, due to their computational complexity, they may not be suitable for implantable devices that have stringent area and power consumption requirements. We first developed a software-based spike sorting system in both floating-point and fixed-point representations. Then, we used our developed software-based spike sorting system for: 1) studying various neural signal processing algorithms and assessing their feasibility for efficient hardware implementations; and 2) offline processing of previously recorded neural data and extracting the threshold data and spike templates for configuring our spike sorting hardware architecture. The characteristics and implementation results of the designed spike sorting system on a Xilinx Artix-7 A200TFBG676-2 field-programmable gate array are presented. The application-specific integrated circuit (ASIC) implementation of the designed spike sorting system is estimated to occupy 0.3 mm2. Postlayout synthesis and simulation shows that the ASIC implementation will dissipate 64 nW from a 0.25-V supply, while operating at a 24-kHz frequency in a standard 45-nm CMOS technology. Compared to the previously published work, our ASIC implementation consumes 96.8% less power, while maintaining a comparable sorting accuracy. Moreover, our design can run at a higher clock frequency and uses fewer hardware resources, while achieving a 168% reduction in output data rate when comparing the raw data sampling rate and the sorted spike output rate and, yet, offers comparable spike sorting accuracy.