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In recent years, tensor computation has become a promising tool for solving big data analysis, machine learning, medical image and EDA problems. To ease the memory and computation intensity of tensor processing, decomposition techniques, especially Tensor-train Decomposition(TTD), are widely adopted to compress the extremely high-dimensional tensor data. Despite TTD’s potential to break the curse of dimensionality, researchers have not yet leveraged its full computational potential, mainly because of two reasons:(1) Executing TTD itself is time-and energy-consuming due to the singular value decomposition(SVD) operation inside each of TTD’s iteration; (2) Additional software/hardware optimizations are often required to process the obtained TT-format data in certain applications such as deep learning inference. In this paper, we address these challenges with two approaches. Firstly, we propose an algorithm-hardware co-design with customized architecture namely TTD Engine to accelerate TTD. We use MRI image compression as a demo application to illustrate the efficacy of the proposed accelerator. Secondly, we present a case study demonstrating the benefit of TT-format data processing and the efficacy of using TTD Engine. In the case study, we use TT approach to realize convolution operation, which is difficult and nontrivial for TT-format data. Experimental results show that, TTD Engine achieves, on average, 14.9×∼36.9× speedup over CPU implementations and 4.1×∼9.9× speedup compared to the GPU baseline. The energy efficiency is also improved by at least 14.4× and 5.4× over CPU and GPU, respectively. Moreover, our hardware-enabled TT-format data processing further leads to more efficient implementations of complicated operations and applications.

In recent years, plenty of metrics have been proposed to identify networks that are free of gradient explosion and vanishing. However, due to the diversity of network components and complex serial-parallel hybrid connections in modern DNNs, the evaluation of existing metrics usually requires strong assumptions, complex statistical analysis, or has limited application fields, which constraints their spread in the community. In this paper, inspired by the Gradient Norm Equality and dynamical isometry, we first propose a novel metric called Block Dynamical Isometry, which measures the change of gradient norm in individual block. Because our Block Dynamical Isometry is norm-based, its evaluation needs weaker assumptions compared with the original dynamical isometry. To mitigate the challenging derivation, we propose a highly modularized statistical framework based on free probability. Our framework includes several key theorems to handle complex serial-parallel hybrid connections and a library to cover the diversity of network components. Besides, several sufficient prerequisites are provided. Powered by our metric and framework, we analyze extensive initialization, normalization, and network structures. We find that Gradient Norm Equality is a universal philosophy behind them. Then, we improve some existing methods based on our analysis, including an activation function selection strategy for initialization techniques, a new configuration for weight normalization, and a depth-aware way to derive coefficients in SeLU. Moreover, we propose a novel normalization technique named second moment normalization, which is theoretically 30% faster than batch normalization without accuracy loss. Last but not least, our conclusions and methods are evidenced by extensive experiments on multiple models over CIFAR10 and ImageNet., Comment: Under review as a regular paper in TPAMI

In this paper, a novel D eep M ulti-view J oint C lustering ( DMJC ) framework is proposed, where multiple deep embedded features, multi-view fusion mechanism, and clustering assignments can be learned simultaneously. Through the joint learning strategy, the clustering-friendly multi-view features and useful multi-view complementary information can be exploited effectively to improve the clustering performance. Under the proposed joint learning framework, we design two ingenious variants of deep multi-view joint clustering models, whose multi-view fusion is implemented by two kinds of simple yet effective schemes. The first model, called DMJC-S, performs multi-view fusion in an implicit way via a novel multi-view soft assignment distribution. The second model, termed DMJC-T, defines a novel multi-view auxiliary target distribution to conduct the multi-view fusion explicitly. Both DMJC-S and DMJC-T are optimized under a KL divergence objective. Experiments on eight challenging image datasets demonstrate the superiority of both DMJC-S and DMJC-T over single/multi-view baselines and the state-of-the-art multi-view clustering methods, which proves the effectiveness of the proposed DMJC framework. To the best of our knowledge, this is the first work to model the multi-view clustering in a deep joint framework, which will provide a meaningful thinking in unsupervised multi-view learning.

The frequent data movement between the processor and the memory has become a severe performance bottleneck for deep neural network (DNN) training workloads in data centers. To solve this off-chip memory access challenge, the 3-D stacking processing-in-memory (3D-PIM) architecture provides a viable solution. However, existing 3D-PIM designs for DNN training suffer from the limited memory bandwidth in the base logic die. To overcome this obstacle, integrating the DNN related logic near each memory bank becomes a promising yet challenging solution, since naively implementing the floating-point (FP) unit and the cache in the memory die incurs a large area overhead. To address these problems, we propose DLUX, a high performance and energy-efficient 3D-PIM accelerator for DNN training using the near-bank architecture. From the hardware perspective, to support the FP multiplier with low area overhead, an in-DRAM lookup table (LUT) mechanism is invented. Then, we propose to use a small scratchpad buffer together with a lightweight transformation engine to exploit the locality and enable flexible data layout without the expensive cache. From the software aspect, we split the mapping/scheduling tasks during DNN training into intralayer and interlayer phases. During the intralayer phase, to maximize data reuse in the LUT buffer and the scratchpad buffer, achieve high concurrency, and reduce data movement among banks, a 3D-PIM customized loop tiling technique is adopted. During the interlayer phase, efficient techniques are invented to ensure the input–output data layout consistency and realize the forward–backward layout transposition. Experiment results show that DLUX can reduce FP32 multiplier area overhead by 60% against the direct implementation. Compared with a Tesla V100 GPU, end-to-end evaluations show that DLUX can provide on average $6.3\times $ speedup and $42\times $ energy efficiency improvement.

The photoisomerization properties of azo derivatives have been widely used in the fields of materials and biology. One serious restriction to the development of functional azo-based materials is the necessity to trigger switching by UV light, which damage the corresponding surfaces and penetrate only partially through the matter. Therefore, developing the visible and near-infrared light activated azo switches can solve this problem. This review provides a summary of molecular design strategies for driving the isomerization of azo derivatives with visible light and near-infrared light: (1) smart design directly excited by visible light, (2) the addition of upconversion nanoparticles, (3) the employment of two-photon absorption, (4) indirect excitation in combination with metal sensitizer.

Deep neural network (DNN) accelerators are widely deployed in computer vision, speech recognition, and machine translation applications, in which attacks on DNNs have become a growing concern. This article focuses on exploring the implications of hardware Trojan attacks on DNNs. Trojans are one of the most challenging threat models in hardware security where adversaries insert malicious modifications to the original integrated circuits (ICs), leading to malfunction once being triggered. Such attacks can be conducted by adversaries because modern ICs commonly include third-party intellectual property (IP) blocks. Previous studies design hardware Trojans to attack DNNs with the assumption that adversaries have full knowledge or manipulation of the DNN systems’ victim model and toolchain in addition to the hardware platforms, yet such a threat model is strict, limiting their practical adoption. In this article, we propose a memory Trojan methodology that implants the malicious logics merely into the memory controllers of DNN systems without the necessity of toolchain manipulation or accessing to the victim model and thus is feasible for practical uses. Specifically, we locate the input image data among the massive volume of memory traffics based on memory access patterns and propose a Trojan trigger mechanism based on detecting the geometric feature in input images. Extensive experiments show that the proposed trigger mechanism is effective even in the presence of environmental noises and preprocessing operations. Furthermore, we design and implement the payload and verify that the proposed Trojan technique can effectively conduct both untargeted and targeted attacks on DNNs.

Tensor network and tensor computation are widely applied in scientific and engineering domains like quantum physics, electronic design automation, and machine learning. As one of the most fundamental operations for tensor networks, a tensor contraction eliminates the sharing orders among tensors and produces a compact sub-network. Different contraction sequence usually yields distinct storage and compute costs, and searching the optimal sequence is known as a hard problem. Prior work have designed heuristic and fast algorithms to solve this problem, however, several issues still remain unsolved. For example, the data format and data structure are not efficient, the constraints during modeling are impractical, the search of the optimal solution might fail, and the search cost is very high. In this paper, we first introduce a $log_k$ order representation and design an adjacency matrix-based data structure to efficiently accelerate the search of the optimal contraction sequence. Then, we propose an outer product pruning method with acceptable overhead to reduce the search space. Finally, we use a multithread optimization in our implementation to further improve the execution performance. We also present in-depth analysis of factors that influence the search time. This work provides a full-stack solution for optimal contraction sequence search from both high-level data structure and search algorithm to low-level execution parallelism, and it will benefit a broad range of tensor-related applications.

We propose P-RT, the first robotic vision runtime framework to efficiently manage dynamic task executions on mobile systems with multiple accelerators as well as on the cloud to achieve better performance and energy savings. With P-RT, we enable a robot to simultaneously perform autonomous navigation.

In order to reduce the computational complexity of convolutional neural networks (CNNs), the local binary convolutional neural network (LBCNN) has been proposed. In the LBCNN, a convolutional layer is divided into two sublayers. Sublayer 1 is a sparse ternary-weighted convolutional layer, and Sublayer 2 is a 1 $\times$ 1 convolutional layer. With the use of two sublayers, the LBCNN has lower computational complexity and uses less memory than the CNN. In this brief, we propose a platform that includes a weight preprocessor and layer accelerator for the LBCNN. The proposed weight preprocessor takes advantage of the sparsity in the LBCNN and encodes the weight offline. The layer accelerator effectively uses the encoded data to reduce computational complexity and memory accesses for an inference. When compared to the state-of-the-art design, the experimental results show that the number of clock cycles are reduced by 76.32%, and memory usage is reduced by 39.41%. The synthesized results show that the clock period is reduced by 4.76%; the cell area is reduced by 46.48%, and the power consumption is reduced by 40.87%. The inference accuracy is the same as that of the state-of-the-art design.

The use of redox-active organic compounds to make rechargeable batteries is a promising strategy for future energy storage especially from a resource and environmental sustainability point of view. While many organic structures have been identified as potential electroactive materials, their direct application in solid-state energy storage is limited. This is due to their high solubility in common organic electrolytes, resulting in poor long-term battery performance. In this work, we overcome this significant problem by synthesizing very low soluble nitroxide radicals with theoretical capacities of 111–131 mAh g−1, equal to or higher than most commonly used nitroxide radical polymers. These new structures consist of TEMPO (i.e. 2,2,6,6-tetramethylpiperidinyl-1-oxy) radicals and triazole ring linkages synthesized by the copper-catalyzed azide-alkyne cycloaddition (CuAAC) ‘click’ reaction. Analysis of electrode morphology and electrochemical performance at increasing mass loading of the nitroxide radicals demonstrate the importance of lower solubility, preventing the shuttle effect observed for common organic electrode materials. The electrodes with the content of active materials up to 80 wt% can still maintain a good interaction with the carbon and conductivity throughout the electrode and deliver a capacity greater than 60 mAh g−1 over 200 cycles.

Although inorganic and metallic materials have demonstrated great success in energy storage, increasing concerns on resource depletion and potential environmental consequences associated with ore mining and processing have driven the search for sustainable and environmental-friendly alternatives. Organic redox molecules exhibiting multi-electron storage and fast electron transfer kinetics are ideal compounds for sustainable high-energy storage devices with high-power output. Nitroxide radical polymers (NRPs) are the representative materials that could achieve these functions. Nevertheless, most NRP batteries only demonstrated one-electron storage via the redox couple (I) NO+/NO˙. Two-electron storage through successive redox couple (I) NO+/NO˙ and (II) NO˙/NO− has been observed rarely only under specific electrode and electrolyte conditions with no mechanism presented. Here, we realize two-electron storage in a NRP/Li battery by using polyether-based NRP gel with a common battery condition from which we unravel electron transfer kinetics and the ion transport process in the battery condition. Electrochemical analysis reveals a ten-fold higher heterogeneous electron transfer rate constant (k0) for the redox couple (I) NO+/NO˙ in comparison to (II) NO˙/NO−, which agree with the value from Ab initio calculations and the Marcus–Hush theory's prediction. We find out that the high reorganization energy and slow diffusion of Li+ for redox couple NO˙/NO− are major causes for its sluggish or absent electron transfer process, which could be improved by altering the chemical composition of NRPs. Our findings imply how the molecular design of polymer electrode materials facilitates high-energy and high-power density storage.

Deep neural networks (DNNs) thrive in recent years, wherein batch normalization (BN) plays an indispensable role. However, it has been observed that BN is costly due to the huge reduction and elementwise operations that are hard to be executed in parallel, which heavily reduces the training speed. To address this issue, in this article, we propose a methodology to alleviate the BN’s cost by using only a few sampled or generated data for mean and variance estimation at each iteration. The key challenge to reach this goal is how to achieve a satisfactory balance between normalization effectiveness and execution efficiency. We identify that the effectiveness expects less data correlation in sampling while the efficiency expects more regular execution patterns. To this end, we design two categories of approach: sampling or creating a few uncorrelated data for statistics’ estimation with certain strategy constraints. The former includes “batch sampling (BS)” that randomly selects a few samples from each batch and “feature sampling (FS)” that randomly selects a small patch from each feature map of all samples, and the latter is “virtual data set normalization (VDN)” that generates a few synthetic random samples to directly create uncorrelated data for statistics’ estimation. Accordingly, multiway strategies are designed to reduce the data correlation for accurate estimation and optimize the execution pattern for running acceleration in the meantime. The proposed methods are comprehensively evaluated on various DNN models, where the loss of model accuracy and the convergence rate are negligible. Without the support of any specialized libraries, $1.98\times $ BN layer acceleration and 23.2% overall training speedup can be practically achieved on modern GPUs. Furthermore, our methods demonstrate powerful performance when solving the well-known “micro-BN” problem in the case of a tiny batch size. This article provides a promising solution for the efficient training of high-performance DNNs.

Over the last decade, artificial intelligence (AI) has found many applications areas in the society. As AI solutions have become more sophistication and the use cases grew, they highlighted the need to address performance and energy efficiency challenges faced during the implementation process. To address these challenges, there has been growing interest in neuromorphic chips. Neuromorphic computing relies on non von Neumann architectures as well as novel devices, circuits and manufacturing technologies to mimic the human brain. Among such technologies, three-dimensional (3D) integration is an important enabler for AI hardware and the continuation of the scaling laws. In this paper, we overview the unique opportunities 3D integration provides in neuromorphic chip design, discuss the emerging opportunities in next generation neuromorphic architectures and review the obstacles. Neuromorphic architectures, which relied on the brain for inspiration and emulation purposes, face grand challenges due to the limited understanding of the functionality and the architecture of the human brain. Yet, high-levels of investments are dedicated to develop neuromorphic chips. We argue that 3D integration not only provides strategic advantages to the cost-effective and flexible design of neuromorphic chips, it may provide design flexibility in incorporating advanced capabilities to further benefit the designs in the future.

In situ cross-linking encapsulation has been demonstrated to be an efficient strategy for enhancing the humidity stability of perovskite solar cells (PSCs). In this study, a novel cross-linkable fullerene derivative, namely 1-(p-benzoate-(p-methylvinylbenzene)-indolino[2,3][60] fullerene (FPPS), was readily synthesized from commercially available building blocks in two steps. This FPPS was employed as an interfacial modifier on perovskite surfaces in inverted planar p–i–n PSCs. Owing to the fast interfacial charge extraction and efficient trap passivation, PSCs based on the cross-linked FPPS (C-FPPS) exhibited excellent performance. The PSCs had a top-performing power conversion efficiency (PCE) of 17.82% with negligible hysteresis, compared to the control devices without C-PFFS (16.99%). Moreover, the strong water resistance of the C-FPPS interfacial layer distinctly enhances the ambient stability of PSC devices, exhibiting a t80 (the time required to reach 80% of the initial PCE) of 300 h under high-humidity conditions. This significantly surpasses the control devices, whose t80 was only 130 h. These results demonstrate that cross-linkable fullerene derivatives can be promising interfacial materials for designing high-efficiency, hysteresis-free, air-stable PSCs.

Multi-chip many-core neural network systems are capable of providing high parallelism benefited from decentralized execution, and they can be scaled to very large systems with reasonable fabrication costs. As multi-chip many-core systems scale up, communication latency related effects will take a more important portion in the system performance. While previous work mainly focuses on the core placement within a single chip, there are two principal issues still unresolved: the communication-related problems caused by the non-uniform, hierarchical on/off-chip communication capability in multi-chip systems, and the scalability of these heuristic-based approaches in a factorially growing search space. To this end, we propose a reinforcement-learning-based method to automatically optimize core placement through deep deterministic policy gradient, taking into account information of the environment by performing a series of trials (i.e., placements) and using convolutional neural networks to extract spatial features of different placements. Experimental results indicate that compared with a naive sequential placement, the proposed method achieves 1.99× increase in throughput and 50.5% reduction in latency; compared with the simulated annealing, an effective technique to approximate the global optima in an extremely large search space, our method improves the throughput by 1.22× and reduces the latency by 18.6%. We further demonstrate that our proposed method is capable to find optimal placements taking advantages of different communication properties caused by different system configurations, and work in a topology-agnostic manner.

Electrets are dielectric materials that have a quasi-permanent dipole polarization. A single-molecule electret is a long-sought-after nanoscale component because it can lead to miniaturized non-volatile memory storage devices. The signature of a single-molecule electret is the switching between two electric dipole states by an external electric field. The existence of these electrets has remained controversial because of the poor electric dipole stability in single molecules. Here we report the observation of a gate-controlled switching between two electronic states in Gd@C82. The encapsulated Gd atom forms a charged centre that sets up two single-electron transport channels. A gate voltage of ±11 V (corresponding to a coercive field of ~50 mV A–1) switches the system between the two transport channels with a ferroelectricity-like hysteresis loop. Using density functional theory, we assign the two states to two different permanent electrical dipole orientations generated from the Gd atom being trapped at two different sites inside the C82 cage. The two dipole states are separated by a transition energy barrier of 11 meV. The conductance switching is then attributed to the electric-field-driven reorientation of the individual dipole, as the coercive field provides the necessary energy to overcome the transition barrier. A Gd@C82 molecule shows electric polarization switching behaviour under a gate bias voltage, thus demonstrating a single-molecule electret device.

Blind separation of sources (BSS) is to recover the source signals from the observed mixture signals with no knowledge on the mixing channel. Recently, there has been more and more attention to underdetermined BSS. In the study of underdetermined BSS, it is a challenging problem to separate the source signals efficiently while without knowing the number of sources. On the one hand, the number of sources is unknown in practice. On the other hand, most traditional blind separation algorithms encounter highly computational complexity leading to poor separation performance. To remedy the shortcomings of traditional algorithms, in this paper, a novel algorithm based on p-norm-like ( l ( 0 p ≤ 1 ) ) diversity measures is proposed to solve the underdetermined BSS problem. First of all, we propose an improved information theory criteria method to detect the number of sources in the underdetermined case. Meanwhile, we use a fourth-order tensor blind identification method for the estimation of the mixing matrix. In the stage of source signal reconstruction, we develop an l ( 0 p ≤ 1 ) -norm diversity measure for better source signal reconstruction and the computational complexity is reduced significantly. Simulation results and experimental measurements demonstrate that the proposed algorithm can obtain better separation performance and achieve fast running speed.

In order to prepare excellent electro-responsive natural hydrogels, in this paper, soluble starch with large amount of hydroxyl groups was selected as raw material. For exploring the enhancement to electro-response of starch hydrogel, starch-Fe(III) composite hydrogels were successfully obtained by a combination of Fe(III) into starch hydrogel in this paper. The composite hydrogels were prepared as A-hydrogels cured in the presence of electric field and B-hydrogels which cured without electric field. The storage modulus of A-hydrogels and B-hydrogels was measured using a dynamic viscoelasticity spectrometer (DMA); the consequent modulus increment (ΔG = GA-GB) and modulus increment sensitivity (ΔG/GB) were analyzed for indicating electro-response of the hydrogels. The physical microstructure of the hydrogels was observed by scanning electron microscopy (SEM). Fourier transform infrared spectroscopy (FT-IR) and thermogravimetric analysis (TGA) were used to study the chemical constitution and structure. The results show that there is a coordinate bond between Fe(III) with –OH of starch which leads to a stronger three-dimensional network structure and higher thermal stability of the starch-Fe(III) hydrogel. What’s more, the electro-response of the hydrogels can be affected according to the Fe3+ concentration. When the Fe3+ concentration is 0.15 ~ 0.25 M under the electric field of 0.8 kV mm−1, the starch-Fe(III) hydrogels have the strongest electro-response, the maximum value of modulus increment (ΔG) is 24 kPa, and the modulus increment sensitivity (∆G/GB) is about 90%, far more than pure starch hydrogel.

Flash memories and semiconductor p-n junctions are two elementary but incompatible building blocks of most electronic and optoelectronic devices. The pressing demand to efficiently transfer massive data between memories and logic circuits, as well as for high data storage capability and device integration density, has fueled the rapid growth of technique and material innovations. Two-dimensional (2D) materials are considered as one of the most promising candidates to solve this challenge. However, a key aspect for 2D materials to build functional devices requires effective and accurate control of the carrier polarity, concentration and spatial distribution in the atomically thin structures. Here, a non-volatile opto-electrical doping approach is demonstrated, which enables reversibly writing spatially resolved doping patterns in the MoTe2 conductance channel through a MoTe2/hexagonal boron nitride (h-BN) heterostructure. Based on the doping effect induced by the combination of electrostatic modulation and ultraviolet light illumination, a 3-bit flash memory and various homojunctions on the same MoTe2/BN heterostructure are successfully developed. The flash memory achieved 8 well distinguished memory states with a maximum on/off ratio over 104. Each state showed negligible decay during the retention time of 2,400 s. The heterostructure also allowed the formation of p-p, n-n, p-n, and n-p homojunctions and the free transition among these states. The MoTe2 p-n homojunction with a rectification ratio of 103 exhibited excellent photodetection and photovoltaic performance. Having the memory device and p-n junction built on the same structure makes it possible to bring memory and computational circuit on the same chip, one step further to realize near-memory computing.

Toward the long-standing dream of artificial intelligence, two successful solution paths have been paved: 1) neuromorphic computing and 2) deep learning. Recently, they tend to interact for simultaneously achieving biological plausibility and powerful accuracy. However, models from these two domains have to run on distinct substrates, i.e., neuromorphic platforms and deep learning accelerators, respectively. This architectural incompatibility greatly compromises the modeling flexibility and hinders promising interdisciplinary research. To address this issue, we build a unified model description framework and a unified processing architecture (Tianjic), which covers the full stack from software to hardware. By implementing a set of integration and transformation operations, Tianjic is able to support spiking neural networks, biological dynamic neural networks, multilayered perceptron, convolutional neural networks, recurrent neural networks, and so on. A compatible routing infrastructure enables homogeneous and heterogeneous scalability on a decentralized many-core network. Several optimization methods are incorporated, such as resource and data sharing, near-memory processing, compute/access skipping, and intra-/inter-core pipeline, to improve performance and efficiency. We further design streaming mapping schemes for efficient network deployment with a flexible tradeoff between execution throughput and resource overhead. A 28-nm prototype chip is fabricated with >610-GB/s internal memory bandwidth. A variety of benchmarks are evaluated and compared with GPUs and several existing specialized platforms. In summary, the fully unfolded mapping can achieve significantly higher throughput and power efficiency; the semi-folded mapping can save 30x resources while still presenting comparable performance on average. Finally, two hybrid-paradigm examples, a multimodal unmanned bicycle and a hybrid neural network, are demonstrated to show the potential of our unified architecture. This article paves a new way to explore neural computing.

Convolutional neural networks (CNNs) have achieved great success in numerous AI applications. To improve inference efficiency of CNNs, researchers have proposed various pruning techniques to reduce both computation intensity and storage overhead. These pruning techniques result in multi-level sparsity irregularities in CNNs. Together with that in activation matrices, which is induced by employment of ReLU activation function, all these sparsity irregularities cause a serious problem of computation resource under-utilization in sparse CNN accelerators. To mitigate this problem, we propose a method of load-balancing based on a workload stealing technique. We demonstrate that this method can be applied to two major inference data-flows, which cover all state-of-the-art sparse CNN accelerators. Based on this method, we present an accelerator, called Crane, which addresses all kinds of sparsity irregularities in CNNs. We perform a fair comparison between Crane and state-of-the-art prior approaches. Experimental results show that Crane improves performance by $27\%\sim 88\%$ 27 % ∼ 88 % and reduces energy consumption by $16\%\sim 48\%$ 16 % ∼ 48 % , respectively, compared to the counterparts.

The structure-dependent thermal stability of fullerene electron transport layers (ETLs) and its impact on device stability have been underrated for years. Based on cocrystallographic understanding, herein, we develop a thermally stable ETL comprising a hybrid layer of [6,6]-phenyl-C

Recently, due to the availability of big data and the rapid growth of computing power, artificial intelligence (AI) has regained tremendous attention and investment. Machine learning (ML) approaches have been successfully applied to solve many problems in academia and in industry. Although the explosion of big data applications is driving the development of ML, it also imposes severe challenges of data processing speed and scalability on conventional computer systems. Computing platforms that are dedicatedly designed for AI applications have been considered, ranging from a complement to von Neumann platforms to a “must-have” and stand-alone technical solution. These platforms, which belong to a larger category named “domain-specific computing,” focus on specific customization for AI. In this article, we focus on summarizing the recent advances in accelerator designs for deep neural networks (DNNs)—that is, DNN accelerators. We discuss various architectures that support DNN executions in terms of computing units, dataflow optimization, targeted network topologies, architectures on emerging technologies, and accelerators for emerging applications. We also provide our visions on the future trend of AI chip designs. Keywords: Deep neural network, Domain-specific architecture, Accelerator

Developing non-precious metal catalysts with high activity is crucial for the extensive applications of the proton exchange membrane fuel cell (PEMFC). Herein, we have prepared cobalt–copper–boron (Co–Cu–B) nanoparticles by a modified chemical reduction route where Ni foam was used as an initiation medium for the efficient hydrolysis of alkaline sodium borohydride (NaBH4) solution. The influence of the synthetic condition (such as Cu2+ concentration, pH value and the concentration of reducing agent) on the catalytic activities has been explored. The catalytic hydrolytic tests reveal that the as-obtained Co–Cu–B nanoparticles with hollow spherical structure shows highly efficient catalytic activity, affording a hydrogen generation rate (HGR) of 3554.2 mL H 2 · g catal . − 1 · min − 1 under room temperature, and a lower activation energy of 52.0 kJ· mol−1, which overtakes the activities of previous reported most non-precious metal catalysts, even some precious catalysts. The kinetics results show that the catalytic hydrolysis process of alkaline NaBH4 solution is a zero-order reaction in view of the amount of Co–Cu–B catalyst, meaning that the reaction rate is independent of the catalyst amount. This study offers us a promising non-precious metal catalyst toward dehydrogenation from the hydrolysis of NaBH4 to further speed up the application steps.

Energy loss within organic solar cells (OSCs) is undesirable as it reduces cell efficiency1–4. In particular, non-radiative recombination loss3 and energetic disorder5, which are closely related to the tail states below the band edge and the overall photon energy loss, need to be minimized to improve cell performance. Here, we report how the use of a small-molecule acceptor with torsion-free molecular conformation can achieve a very low degree of energetic disorder and mitigate energy loss in OSCs. The resulting single-junction OSC has an energy loss due to non-radiative recombination of just 0.17 eV and a high power conversion efficiency of up to 16.54% (certified as 15.89% by the National Renewable Energy Laboratory). The findings take studies of organic photovoltaics deeper into a new regime, beyond the limits of energetic disorder and large energy offset for charge generation. An organic solar cell designed with minimal energetic disorder exhibits very low energy loss due to non-radiative recombination and highly efficient operation.

Charge-trapping memory devices based on two-dimensional (2D) material heterostructures possess an atomically thin structure and excellent charge transport capability, making them promising candidates for next-generation flash memories to achieve miniaturized size, high storage capacity, fast switch speed, and low power consumption. Here, we report a nonvolatile floating-gate memory device based on an ReS2/boron nitride/graphene heterostructure. The implemented ReS2 memory device displays a large memory window exceeding 100 V, leading to an ultrahigh current ratio over 108 between programming and erasing states. The ReS2 memory device also exhibits an ultrafast switch speed of 1 μs. In addition, the device can endure hundreds of switching cycles and shows stable retention characteristics with ∼40% charge remaining after 10 years. More importantly, taking advantage of its anisotropic electrical properties, a single ReS2 flake can achieve direction-sensitive multi-level data storage to enhance the data storage density. On the basis of these characteristics, the proposed ReS2 memory device is potentially able to serve the entire memory device hierarchy, meeting the need for scalability, capacity, speed, retention, and endurance at each level.

This article presents a tensor multi-task model for person re-identification (Re-ID). Due to discrepancy among cameras, our approach regards Re-ID from multiple cameras as different but related classification tasks, each task corresponding to a specific camera. In each task, we distinguish the person identity as a one-vs-all linear classification problem, where one classifier is associated with a specific person. By constructing all classifiers into a task-specific projection matrix, the proposed method could utilize all the matrices to form a tensor structure, and jointly train all the tasks in a uniform tensor space. In this space, by assuming the features of the same person under different cameras are generated from a latent subspace, and different identities under the same perspective share similar patterns, the high-order correlations, not only across different tasks but also within a certain task, can be captured by utilizing a new type of low-rank tensor constraint. Therefore, the learned classifiers transform the original feature vector into the latent space, where feature distributions across cameras can be well-aligned. Moreover, this model can be incorporated into multiple visual features to boost the performance, and easily extended to the unsupervised setting. Extensive experiments and comparisons with recent Re-ID methods manifest the competitive performance of our method.

To mitigate the impact of non-deterministic media access latencies in new memory technology devices, a recently proposed Non-Volatile Dual In-line Memory Module (NVDIMM) standard, NVDIMM-P uses novel out-of-order transaction commands. The previous DRAM simulators are unable to support this transaction protocol due to deterministic DDR timing. Also, existing NVDIMM simulators are customized for NAND flash memory, which are not generally applicable to emerging Non-Volatile Memory (NVM). In this letter, we present NMTSim, a transaction-command based and cycle accurate simulator for new memory technology devices. Strictly conforming to NVDIMM-P standard, NMTSim introduces a new memory controller with transaction handling and command issuing capabilities. To enable simulation for emerging NVM using DDR4 standard, we propose some new NVM timing parameters and incorporated them into DRAMSim2. Furthermore, DRAMSim2 is augmented with transaction handling and command scheduling logic to be the backend for the media controller. In addition, NMTSim incorporates an optimized transaction command issuing policy and an early notification mode to optimize access latency. We verify NMTSim using Intel Optane and characterize its performance using synthetic benchmarks with different read / write ratios.

Artificial neural networks (ANNs), a popular path towards artificial intelligence, have experienced remarkable success via mature models, various benchmarks, open-source datasets, and powerful computing platforms. Spiking neural networks (SNNs), a category of promising models to mimic the neuronal dynamics of the brain, have gained much attention for brain inspired computing and been widely deployed on neuromorphic devices. However, for a long time, there are ongoing debates and skepticisms about the value of SNNs in practical applications. Except for the low power attribute benefit from the spike-driven processing, SNNs usually perform worse than ANNs especially in terms of the application accuracy. Recently, researchers attempt to address this issue by borrowing learning methodologies from ANNs, such as backpropagation, to train high-accuracy SNN models. The rapid progress in this domain continuously produces amazing results with ever-increasing network size, whose growing path seems similar to the development of deep learning. Although these ways endow SNNs the capability to approach the accuracy of ANNs, the natural superiorities of SNNs and the way to outperform ANNs are potentially lost due to the use of ANN-oriented workloads and simplistic evaluation metrics. In this paper, we take the visual recognition task as a case study to answer the questions of "what workloads are ideal for SNNs and how to evaluate SNNs makes sense". We design a series of contrast tests using different types of datasets (ANN-oriented and SNN-oriented), diverse processing models, signal conversion methods, and learning algorithms. We propose comprehensive metrics on the application accuracy and the cost of memory & compute to evaluate these models, and conduct extensive experiments. We evidence the fact that on ANN-oriented workloads, SNNs fail to beat their ANN counterparts; while on SNN-oriented workloads, SNNs can fully perform better. We further demonstrate that in SNNs there exists a trade-off between the application accuracy and the execution cost, which will be affected by the simulation time window and firing threshold. Based on these abundant analyses, we recommend the most suitable model for each scenario. To the best of our knowledge, this is the first work using systematical comparisons to explicitly reveal that the straightforward workload porting from ANNs to SNNs is unwise although many works are doing so and a comprehensive evaluation indeed matters. Finally, we highlight the urgent need to build a benchmarking framework for SNNs with broader tasks, datasets, and metrics.

Nitroxide radicals have great applications in energy storage, catalysis, and biomedicine. The combination of nitroxide radicals and (bpy)copper is an efficient and green catalytic system that mimics galactose oxidase and uses oxygen as a primary oxidant. However, the separation and reuse of nitroxide radicals from the reaction have been challenging. Herein, we demonstrate the synthesis of a polyether-based gel with pendant 2,2,6,6-tetramethyl-1-piperidinyloxy (TEMPO) radicals and its application as a recyclable catalyst to oxidise primary alcohols to aldehydes in air. TEMPO-containing polyether gel is produced via anionic polymerization in a polar environment, driven by the hydrophobic π–π stacking of pyrene functionalities. The content of pyrene functional comonomers (i.e. 10 mol%), the polarity of polymerization solvents, and the chemical composition of the backbone are equally important for physical crosslinking and gel formation. This TEMPO-containing polyether gel showed the great capability of catalytically oxidising a variety of alcohols to aldehydes with (bpy)copper as a co-catalyst in air. The gel can be easily separated and recycled from the reaction for repeated catalysis without the leakage of TEMPO radicals.

Four new main-chain-twisted acceptor–donor–acceptor-type (A–D–A) non-fullerene acceptors (i-mO-4F, i-mO-4Cl, i-pO-4F, and i-pO-4Cl) were designed and synthesized, featuring the introduction of meta-hexyloxy-phenyl and para-hexyloxy-phenyl side-chains in the fused-ring core as well as 2-(5,6-difluoro-3-oxo-2,3-dihydro-1H-inden-1-ylidene)malononitrile and 2-(5,6-dichlorine-3-oxo-2,3-dihydro-1H-inden-1-ylidene)malononitrile as the end-capping groups. All four small molecules exhibited broad absorption spectra in the range of 300 nm to 820 nm with a corresponding small optical bandgap of 1.55 eV (i-mO-4F), 1.53 eV (i-mO-4Cl), 1.52 eV (i-pO-4F), and 1.48 eV (i-pO-4Cl), which ensured total complementary absorption with a wide bandgap polymer donor material (PBDB-T). Although i-mO-4Cl possessed a finely bathochromic-shifted absorption spectrum, its poor morphology with PBDB-T in the blend films led to a low power conversion efficiency (PCE) of 7.41%. In contrast, the optimal PBDB-T:i-mO-4F-, PBDB-T:i-pO-4F-, and PBDB-T:i-pO-4Cl-based devices achieved promising PCEs of 14.02%, 13.47%, and 10.98%, respectively. The obtained significantly different results for these two types of NFAs, on the one hand, demonstrate the synergistic effect of the hexyloxy-phenyl side-chain modification and non-planar main-chain strategy to construct highly efficient non-fullerene acceptors for polymer solar cells, and on the other hand, reveal the influence of the fluorinated and chlorinated end-groups on the morphologies and performances of the resultant main-chain-twisted NFAs.

Crossbar architecture has been widely used in neural network (NN) accelerators, involving conventional and emerging devices. It performs well on the fully connected layer through efficient vector–matrix multiplication. Whereas, the advantages degrade on the convolutional layer with huge data reuse, since the execution speed and resource overhead are imbalanced when using existing fully unfolded or fully folded mapping strategy. To address this issue, we propose a novel semi-folded mapping (SemiMap) framework for implementing the convolution on crossbars. It simultaneously folds the physical resources along the row dimension of feature maps (FMs) and unfolds them along the column dimension. The former reduces the resource overhead, and the latter maintains the parallelism. An FM slicing scheme is further proposed to enable the processing of large-size image. Via our mapping framework, a row-by-row streaming pipeline for intraimage dataflow and periodical pipeline for interimage dataflow are easy to be obtained. To validate the idea, we build a many-crossbar architecture with several designs to guarantee the overall functionality and performance. Based on the measurement data of a fabricated chip, a mapping compiler and a cycle-accurate simulator are developed for the hardware simulation of large-scale networks. We evaluate the proposed SemiMap on various convolutional NNs across different network scale. ${>} 35 {\times }$ resource saving and several hundred times cycle reduction are demonstrated compared to the existing fully unfolded and fully folded strategies, respectively. This paper jumps out of the current extreme mapping schemes, and provides a balanced solution on how to efficiently deploy the computational graphs with data reuse on many-crossbar architecture.

In response to the widespread bacterial threat, mechanical bactericidal nanostructures with various morphologies have been reported for years. However, the relationship between morphology and bactericidal properties is still yet to be elucidated due to the lack of a fair comparison under similar density of the nanostructures. For this purpose, an electrical-field assisted hydrothermal growth method were utilized to prepare the ZnO nanoarrays with similar array density (1.9×109 rod·cm2-2.4 ×109 rod·cm2) but gradient morphologies from hexagonal prism, hexagonal prismoid to hexagonal pyramid on stainless steel sheets. Moreover, in dark condition, a bactericidal activity was observed on the ZnO nanoarray surfaces within 30 min contact for both E. coli and S. aureus cells. The bactericidal rate was rapidly enhanced as the average tip width of the nanorods decreasing from 137 to 38 nm. These results suggest that the hexagonal pyramid ZnO nanoarrays have a rapid, efficient and broad-spectrum bactericidal activity, which could contribute to the next-generation aquatic pathogens control strategies.

Multi-index fusion has demonstrated impressive performances in retrieval task by integrating different visual representations in a unified framework. However, previous works mainly consider propagating similarities via neighbor structure, ignoring the high order information among different visual representations. In this paper, we propose a new multi-index fusion scheme for image retrieval. By formulating this procedure as a multilinear based optimization problem, the complementary information hidden in different indexes can be explored more thoroughly. Specially, we first build our multiple indexes from various visual representations. Then a so-called index-specific functional matrix, which aims to propagate similarities, is introduced for updating the original index. The functional matrices are then optimized in a unified tensor space to achieve a refinement, such that the relevant images can be pushed more closer. The optimization problem can be efficiently solved by the augmented Lagrangian method with theoretical convergence guarantee. Unlike the traditional multi-index fusion scheme, our approach embeds the multi-index subspace structure into the new indexes with sparse constraint, thus it has little additional memory consumption in online query stage. Experimental evaluation on three benchmark datasets reveals that the proposed approach achieves the state-of-the-art performance, i.e., N-score 3.94 on UKBench, mAP 94.1\% on Holiday and 62.39\% on Market-1501., 12 pages

Convolution neural networks (CNNs) have demonstrated superior capability in computer vision, speech recognition, autonomous driving, and so forth, which are opening up an artificial intelligence (AI) era. However, conventional CNNs require significant matrix computation and memory usage leading to power and memory issues for mobile deployment and embedded chips. On the algorithm side, the emerging binary neural networks (BNNs) promise portable intelligence by replacing the costly massive floating-point compute-and-accumulate operations with lightweight bit-wise XNOR and popcount operations. On the hardware side, the computing-in-memory (CIM) architectures developed by the non-volatile memory (NVM) present outstanding performance regarding high speed and good power efficiency. In this paper, we propose an NVM-based CIM architecture employing a Preset-XNOR operation in/with the spin–orbit torque magnetic random access memory (SOT-MRAM) to accelerate the computation of BNNs (PXNOR-BNN). PXNOR-BNN performs the XNOR operation of BNNs inside the computing-buffer array with only slight modifications of the peripheral circuits. Based on the layer evaluation results, PXNOR-BNN can achieve similar performance compared with the read-based SOT-MRAM counterpart. Finally, the end-to-end estimation demonstrates $12.3\times $ speedup compared with the baseline with 96.6-image/s/W throughput efficiency.

Monolithic three-dimensional (M3D) integration is viewed as a promising improvement over through-silicon-via-based 3-D integration due to its greater inter-tier connectivity, higher circuit density, and lower parasitic capacitance. With M3D integration, network-on-chip (NoC) communication fabric can benefit from reduced link distances and improved intra-router efficiency. However, the sequential fabrication methods utilized for M3D integration impose unique interconnect requirements for each of the possible partitioning schemes at transistor, gate, and block granularities. Further, increased cell density introduces contention of available routing resources. Prior work on M3D NoCs has focused on the benefits of reduced distances, but has not considered these process-imposed circuit complications. In this article, NoC topology decisions are analyzed in conjunction with these M3D interconnect requirements to provide an equivalent architectural comparison between M3D partitioning schemes.

Silicon (Si) is considered to be a plant growth and development regulator element as well as provide the regulatory response against various biotic stressors. However, the potential mechanism of Si enhancement to regulate plant disease resistance remains to be studied. Therefore, the current study evaluated the effects of Si application on the performance of sugarcane against Xanthomonas albilineans (Xa) infection. Si was applied exogenously (0, 3.85 and 7.70 g Si/kg soil) and the results show that plant height, stem circumference and leaf width of siliconized sugarcane have been improved, which effectively reduced the disease index (0.17–0.21) and incidence (58.2%−69.1%) after Xa infection. Lowest values of MDA (348.5 nmol g−1 FW) and H2O2 (3539.4 mmol/L) were observed in 7.70 g Si/kg soil followed by in 3.85 g Si/kg soil (MDA: 392.6 nmol g−1 FW and H2O2: 3134.6 mmol/L) than that of the control. Whereas, PAL enzyme activity (50.8 mmol/L), JA (230.2 mmol/L) and SA (2.7 ug mL−1) contents were significantly higher in 7.70 g Si/kg soil followed by in 3.85 g Si/kg soil (PAL: 46.3 mmol/L, JA: 182.7 mmol/L and SA: 2.4 ug mL−1) as compared to control. The lower MDA, H2O2 level and higher enzymatic activities were associated with the highest expression levels of their metabolic pathway associated genes i.e., ShMAPK1, ShLOX, ShPAL, ShAOS, ShAOC, ShC4H, ShCAT, Sh4CL and ShNPR1 (22.08, 15.56, 10.42, 3.35, 2.54, 2.14, 1.82, 1.67 and 1.22 folds, respectively) in 7.70 g Si/kg soil as compared to other experimental units and control. Overall, the results of current study indicates that siliconized sugarcane more actively regulates disease resistance through modulation of growth and MDA, H2O2, SA and JA associated metabolic pathways.

Despite the great success of High-Level Synthesis (HLS) tools, we observe several unresolved challenges: 1) the high-level abstraction of programming styles in HLS conceals optimization opportunities; 2) existing HLS tools do not provide flexible trade-offs among different objectives and constraints; 3) the actual quality of the resulting RTL designs is hard to predict. To this end, we propose an end-to-end framework, IRONMAN. The primary goal is to enable a flexible and automated design space exploration (DSE), which can provide either optimized solutions under user-specified constraints, or Pareto trade-offs among different objectives (e.g., resource types, area, and latency). IronMan consists of three components: GPP (a highly accurate graph-neural-network-based performance predictor), RLMD (a reinforcement-learning-based DSE engine that explores the optimized resource allocation strategy), and CT (a code transformer that assists RLMD and GPP by extracting data flow graphs from original HLS C/C++). Experimental results show that, 1) GPP achieves high prediction accuracy, reducing prediction errors of HLS tools by 10.9X in resource usage and 5.7X in timing; 2) RLMD obtains optimized or Pareto solutions outperforming genetic algorithm and simulated annealing by 12.7% and 12.9%, respectively; 3) IronMan can find optimized solutions perfectly matching various DSP constraints, with 2.54X fewer DSPs and up to 6X shorter latency than those of HLS tools. IronMan is also up to 400X faster than meta-heuristic techniques and HLS tools.

The purpose of this paper is to revisit the role of a Cl promoter in selectivity enhancement of ethylene epoxidation by a combined density functional theory and experimental study. The paper argues...

A polarization beam splitter (PBS) based on the plasmonic subwavelength grating (PSWG) is proposed and investigated. The PBS is composed by a directional coupler with a PSWG as the coupling region, which offers additional freedom for index tailoring. The mode properties are strongly modified by the unique structure of the PSWG resulting in selective coupling with the two polarization states in the neighbor waveguides. The calculations show that the insertion loss of PBS is less than 1 dB, and the extinction ratios of transverse electric and transverse magnetic polarizations are as high as 27 dB and 30 dB respectively with nearly 4-μm coupling region length. In addition, the fabrication tolerance of the device is investigated in detail.

Facial landmark localization plays a critical role in face recognition and analysis. In this paper, we propose a novel cascaded backbone-branches fully convolutional neural network~(BB-FCN) for rapidly and accurately localizing facial landmarks in unconstrained and cluttered settings. Our proposed BB-FCN generates facial landmark response maps directly from raw images without any preprocessing. BB-FCN follows a coarse-to-fine cascaded pipeline, which consists of a backbone network for roughly detecting the locations of all facial landmarks and one branch network for each type of detected landmark for further refining their locations. Furthermore, to facilitate the facial landmark localization under unconstrained settings, we propose a large-scale benchmark named SYSU16K, which contains 16000 faces with large variations in pose, expression, illumination and resolution. Extensive experimental evaluations demonstrate that our proposed BB-FCN can significantly outperform the state-of-the-art under both constrained (i.e., within detected facial regions only) and unconstrained settings. We further confirm that high-quality facial landmarks localized with our proposed network can also improve the precision and recall of face detection.

Emerging nonvolatile memories (NVMs), including resistive RAM (RRAM), phase-change memory (PCM), and magnetic RAM (MRAM), have opened up new pathways for Computing-In-Memory (CIM). Those NVM technologies can achieve energy-efficient computational operations with only minor modification of the peripheral circuits. Despite many advantages provided by computational NVMs, parallelism is not sufficiently explored in such CIM designs. To break through this limitation on performance gain, we propose a data-streaming design for the NVM-based CIM (e.g., DASM) by leveraging the underlying parallelism in the hardware. DASM benefits from the massive parallelism of data-streaming computing, reduction in data movement of the CIM, and the nonvolatility of memory arrays. Specifically, data streaming operations can be implemented with CIM bitwise operations in both read-out and write-in procedures. In addition, we use the multilevel power gating for the memory array and connections to further boost the performance. Finally, we study a case of inference process for the quantized deep-neural-network-based on the DASM design. DASM architecture achieves $47.8\times $ , $5.1\times $ , $2.1\times $ speedup compared to the NVIDIA Jetson TK1 embedded GPU board, Intel Xeon E5-2640 CPU, the state-of-the-art field-programmable gate array (FPGA) design, with much lower power consumption.

There are two general approaches to developing artificial general intelligence (AGI)1: computer-science-oriented and neuroscience-oriented. Because of the fundamental differences in their formulations and coding schemes, these two approaches rely on distinct and incompatible platforms2–8, retarding the development of AGI. A general platform that could support the prevailing computer-science-based artificial neural networks as well as neuroscience-inspired models and algorithms is highly desirable. Here we present the Tianjic chip, which integrates the two approaches to provide a hybrid, synergistic platform. The Tianjic chip adopts a many-core architecture, reconfigurable building blocks and a streamlined dataflow with hybrid coding schemes, and can not only accommodate computer-science-based machine-learning algorithms, but also easily implement brain-inspired circuits and several coding schemes. Using just one chip, we demonstrate the simultaneous processing of versatile algorithms and models in an unmanned bicycle system, realizing real-time object detection, tracking, voice control, obstacle avoidance and balance control. Our study is expected to stimulate AGI development by paving the way to more generalized hardware platforms. The ‘Tianjic’ hybrid electronic chip combines neuroscience-oriented and computer-science-oriented approaches to artificial general intelligence, demonstrated by controlling an unmanned bicycle.

Spiking neural networks (SNNs) that enables energy efficient implementation on emerging neuromorphic hardware are gaining more attention. Yet now, SNNs have not shown competitive performance compared with artificial neural networks (ANNs), due to the lack of effective learning algorithms and efficient programming frameworks. We address this issue from two aspects: (1) We propose a neuron normalization technique to adjust the neural selectivity and develop a direct learning algorithm for deep SNNs. (2) Via narrowing the rate coding window and converting the leaky integrate-and-fire (LIF) model into an explicitly iterative version, we present a Pytorch-based implementation method towards the training of large-scale SNNs. In this way, we are able to train deep SNNs with tens of times speedup. As a result, we achieve significantly better accuracy than the reported works on neuromorphic datasets (N-MNIST and DVSCIFAR10), and comparable accuracy as existing ANNs and pre-trained SNNs on non-spiking datasets (CIFAR10). To our best knowledge, this is the first work that demonstrates direct training of deep SNNs with high performance on CIFAR10, and the efficient implementation provides a new way to explore the potential of SNNs.

Die-stacked memories that integrate multiple DRAM dies into the processor package have reduced the interface bottleneck and improved efficiency, but demands for memory capacity and bandwidth remain unfulfilled. Additionally, the introduction of memory into the package further complicates heat removal. Memory power is therefore becoming a key architectural concern. To provide insight into these challenges, an architectural power model for High Bandwidth Memory is developed, validated, and used to provide detailed power profiles. Based on the resulting power trends, power is projected for potential future memory configurations with increased bandwidth and capacity. The results suggest that, without significant improvements in memory technology or architecture, the power utilization of in-package memories will continue to grow and limit the system power budget.

In regular perovskite solar cells (PSCs), the commonly used electron transport layer (ETL) is titanium oxide (TiO2). Nevertheless, the preparation of a high-quality TiO2 ETL demands an elevated-tem...

Despite some efforts have been made in the research of supramolecular hyperbranched polymers (SHPs) self-assemblies, the study which has not been consideration to date is the influence of incoming stimuli-responsive polymer chain on their self-assembly property undergo outer stimuli. The introduction of stimuli-responsive segments which could maintain their hydrophilic property are expected to affect the self-assembly behaviour of SHPs and expand their further biomedical application. In this paper, AB2-type macromolecular monomer, LA-(CD-PDMA)2, which consisted one lithocholic acid (LA) and two β-cyclodextrin terminated poly(2-(dimethylamino)ethyl methacrylate) segments (CD-PDMA) was synthesized. LA-(CD-PDMA)2 based SHP were obtained based on the host-guest inclusion interactions of CD/LA moietes and with PDMA as pH-responsive hydrophilic chains. As a control to study the influence of incoming PDMA chains, both LA-(CD-PDMA)2 based SHPs-1 and LA-CD2 based SHPs-2 self-assemblies were comparatively investiged through 2D 1H NMR ROESY, transmission electron microscopy (TEM) and dynamic light scattering (DLS). The results suggested that except for the higher drug loading efficiency LA-(CD-PDMA)2 based SHPs-1 pocessing, the release rates of SHPs-1 increased notably at pH 5.0 than that of pH 7.4 due to the repulsion and stretch of protonated PDMA chains while the release rates of SHPs-2 showed no obvious difference. Finally, basic cell experiments demonstrated that the SHPs based self-assemblies can be internalized into cancer cells, indicating their potential application in the drug delivery field.

It is well-known that the promoter can enhance the selectivity to ethylene oxide (EO) of Ag catalyzed ethylene epoxidation. However, the selectivity enhancement on different crystal planes of Ag catalysts derived from various promoters is still indistinct. In this work, in order to get an atomistic insight into the synergistic effect between crystal planes and promoters on catalytic performance of Ag catalysts, we study ethylene epoxidation on Ag (1 1 1), (1 1 0) and (1 0 0) surfaces with the promoters of Re, Cs and Cu by density functional theory calculations. It is found that selectivity enhancement introduced by the promoters on Ag (1 1 1) surfaces is more obvious compared with that on Ag (1 1 0) and (1 0 0) surfaces. The sequence of EO selectivity on Ag (1 1 0) surfaces is Re

The training of neural networks (NN) is usually time-consuming and resource intensive. The emerging metal-oxide resistive random-access memory (RRAM) device has shown potential for the computation of NN. RRAM crossbar structure and multibit characteristics can perform the matrix-vector product in high energy efficiency, which is the most common operation of NN. Two challenges exist for realizing training NN based on RRAM. First, the current architectures based on RRAM only support the inference in training NN and cannot perform the backpropagation (BP) and the weight update of training NN. Second, training NN requires enormous iterations to constantly update the weights for reaching the convergence. However, this weight update leads to large energy consumption because of the nonideal factors of RRAM. In this paper, we propose a training-in-memory based on RRAM (TIME) architecture and the peripheral circuit design to enable training NN on RRAM. TIME supports the BP and the weight update while maximizing the re-usage of peripheral circuits of the inference operation on RRAM. Meanwhile, a set of optimization strategies focusing on the nonideal factors are designed to reduce the cost of tuning RRAM. We explore the performance of both supervised learning (SL) and deep reinforcement learning (DRL) on TIME. A specific mapping method of DRL is also introduced to further improve energy efficiency. Simulation results show that in SL, TIME can achieve $5.3{\times }$ higher energy efficiency on average compared with DaDianNao, an application-specific integrated circuits (ASIC) in CMOS technology. In DRL, TIME can perform an average $126{\times }$ higher than GPU in energy efficiency. If the cost of tuning RRAM can be further reduced, TIME has the potential to boost the energy efficiency by two orders of magnitudes compared with ASIC.

van der Waals (vdW) p–n heterojunctions formed by two-dimensional nanomaterials exhibit many physical properties and deliver functionalities to enable future electronic and optoelectronic devices. ...