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To effectively compute convolutional layers, a complex design space must exist (e.g., the dataflow techniques associated with the layer parameters, loop transformation techniques, and hardware parameters). For efficient design space exploration (DSE) of various dataflow techniques, namely, the weight-stationary ( WS ), output-stationary ( OS ), row-stationary ( RS ), and no local reuse ( NLR ) techniques, the processing element (PE) structure and computational pattern of each dataflow technique are analyzed. Various performance metrics are calculated, namely, the throughput (in giga-operations per second, GOPS), computation-to-communication ratio ( CCR ), on-chip memory usage, and off-chip memory bandwidth, as closed-form expressions of the layer and hardware parameters. In addition, loop interchange and loop unrolling techniques with a double-buffer architecture are assumed. Many roofline model-based simulations are performed to explore relevant dataflow techniques for a wide variety of convolutional layers of typical neural networks. Through simulation, this paper provides insights into the trends in accelerator performance as the layer parameters change. For convolutional layers with large input and output feature map ( ifmap and ofmap ) widths and heights, the GOPS of the NLR dataflow technique tends to be higher than that of the techniques. For convolutional layers with low weight and ofmap widths and heights, the RS dataflow technique achieves optimal GOPS and on-chip memory usage. In the case of convolutional layers with small weight widths and heights, the GOPS of the WS dataflow technique tends to be high. In the case of convolutional layers with small ofmap widths and heights, the OS dataflow technique achieves optimal GOPS and on-chip memory usage.

With a target to maximize the throughput, a fast link rate adaptation algorithm for IEEE 802.11a/b/g/n/ac is proposed, which is basically preamble based and can adaptively compensate for the discrepancy between transmitter and receiver radio frequency performances by exploiting the acknowledgment signal. The target system is a 1 &times, 1 wireless local area network chip with no null data packet or sounding. The algorithm can be supplemented by automatic rate fallback at the initial phase to further expedite rate adaptation. The target system receives wireless channel coefficients and previous packet information, translates them to amended signal-to-noise ratios, and then, via the mean mutual information, selects the modulation and coding scheme with the maximum throughput. Extensive simulation and wireless tests are carried out to demonstrate the validity of the proposed adaptive preamble-based link adaptation in comparison with both the popular automatic rate fallback and ideal link adaptation. The throughput gain of the proposed link adaptation over automatic rate fallback is demonstrated over various packet transmission intervals and Doppler frequencies. The throughput gain of the proposed algorithm over ARF is 46% (15%) for a 1-tap (3-tap) channel over 10 m&ndash, 250 m (16 m&ndash, 160 m) normalized Doppler frequencies. Assuming a 3-tap channel and 30 m&ndash, 50 m normalized Doppler frequencies, the throughput of the proposed algorithm is about 31 Mbps, nearly the same as that of ideal link adaptation, whereas the throughput of ARF is about 24 Mbps, leading to a 30% throughput gain of the proposed algorithm over ARF. The firmware is implemented in C and on Xilinx Zynq 7020 (Xilinx, San Jose, CA, USA) for wireless tests.

A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is

A composite radio receiver back-end and digital front-end, made up of a delta-sigma analog-to-digital converter (ADC) with a high-speed low-noise sampling clock generator, and a fractional sample rate converter, are proposed and designed for a multi-mode reconfigurable radio. The proposed radio receiver architecture contributes to saving the chip area and thus lowering the design cost. To enable inter-radio access technology handover and ultimately software-defined radio reception, a reconfigurable radio receiver consisting of a multi-rate ADC with its sampling clock derived from a local oscillator (LO), followed by a rate-adjustable fractional sample rate converter for decimation, is designed. Clock phase noise and timing jitter are examined to support the effectiveness of the proposed radio receiver. A fractional sample rate converter is modeled and simulated with a cubic polynomial interpolator based on Lagrange method and its spectral-domain view is examined in order to verify its effect on al...

Sparse CNN (SCNN) accelerators tend to suffer from the bus contention of its scatter network. This paper considers the optimizations of the scatter network. Several network topologies and arbitration algorithms are evaluated in terms of performance and area.

A spatial data dependence graph (S-DDG) is newly proposed to model an accelerator dataflow. The pre-RTL simulator based on the S-DDG helps to explore the design space in the early design phase. The simulation results show the impact of memory latency and bandwidth on a convolutional neural network (CNN) accelerator.

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

In this letter, the accuracy of the reference signal received power (RSRP) measurement carried out by an LTE user equipment (UE) is analyzed. Assuming the measurement based on the averaged frequency-domain maximum likelihood estimate (FD-MLE), the closed-form expressions of the mean-error and mean-squared-error (MSE) are obtained to show the impact of the channel parameters, the cell ID, the subset size, and the signal-to-interference-plus-noise ratio (SINR). The numerical calculation results based on the closed-form expressions show that the optimum subset size tends to decrease with the SINR and delay spread.

Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5[Formula: see text]m W, and 0.06[Formula: see text]m W, respectively, at 10[Formula: see text]MHz in a 0.18[Formula: see text][Formula: see text]m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50[Formula: see text][Formula: see text]W/MHz with 10,800 gates in a 0.18[Formula: see text][Formula: see text]m CMOS process.

All-digital phase-locked loops (ADPLLs) based on the time-to-digital converter (TDC) and the frequency discriminator (FD) are modeled and analyzed in terms of quantization effects. Using linear models with quantization noise sources, theoretical analysis and simulation are carried out to obtain the output phase noise of each building block of the TDC-based ADPLL. It is newly derived that the TDC noise component caused by the delta-sigma modulator (DSM) and the finite resolution of the digitally controlled oscillator is not white. Namely, the in-band phase noise caused by the DSM-induced TDC is not white, which is due to the integrate-and-dump and subsampling operations of the TDC. This can give some insight into the design of low-noise ADPLLs. Some structures of delta-sigma FDs, which can serve as an alternative to the TDC, are also newly analyzed in terms of quantization noise, using the derived linear noise model.

Frequency dividers are used in frequency synthesizers to generate specific frequencies or clock (CK) waveforms. As consequences of their operating principles, frequency dividers often produce output waveforms that exhibit duty cycles other than 50%. However, some circuits and systems, including dynamic memory systems and data converters, which accommodate frequency divider outputs, may need symmetric or 50%-duty-cycle clock waveforms to optimize timing margins or to obtain sufficient timing reliability. In this review paper, design principles and methods are studied to produce symmetric waveforms for the in-phase (I) and quadrature (Q) outputs of high-speed CMOS frequency dividers with design considerations from the logic gate level down to the transistor level in terms of speed, reliability, noise, and latency. A compact and robust multi-gigahertz frequency divider with moduli 12, 14, and 16 to provide I and Q outputs with 50% duty cycle is proposed and designed using a 90-nm digital CMOS process technology with 1.2-V supply.