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Improving system lifetime and robustness is a key to advancing self-powered platforms for real world applications. A complete self-powered, battery-less, wearable platform requires a microwatt-power system-on-chip (SoC), operating reliably within this budget, capable of surviving long periods without charging, and recovering from power loss to its previous state. To meet these requirements, we designed a wireless sensing heterogeneous system-in-package (SiP) containing an ultra-low power (ULP) SoC, a non-volatile boot memory (NVM), and a 2.4 GHz frequency shift key (FSK) radio, all integrated with custom ULP interfaces. The SoC includes a fully integrated energy harvesting platform power manager (EH-PPM) to power the SiP and other commercial sensors. The EH-PPM is designed for small loads and powers the SoC and peripherals while drawing very low operating current. The SoC also includes a digital system data-flow for sensing applications, an analog front end for ECG signal acquisition, and a cold-boot management system (CBMS) for boot and recovery from the NVM. The CBMS enables integration of the SoC with the ULP NVM to create a wearable formfactor, self-powered system capable of recovery from power loss. The SoC also includes a radio interface tightly integrated with a compression accelerator to efficiently communicate with the FSK transmitter and reduce the FSK's transmission time. This tight integration between accelerators on the SoC and peripherals is another feature that reduces the system's power consumption by reducing the code size and number of memory accesses required to perform an operation. The SoC consumes 507 nW average power while running free-fall detection, 519 nW average power while measuring ambient temperature, and 1.02 μW during continuous ECG monitoring and post-processing.

The rapid development of the Internet-of-Things requires hardware that is both energy-efficient and flexible, and an ultra-low-power Field-Programmable-Gate-Array (FPGA) is a very promising solution. This paper presents a near/sub-threshold FPGA with low-swing global interconnect, folded switch box (SB), per-path voltage scaling, and power-gating. A fully programmable 512-look-up-table FPGA chip is fabricated in 130nm CMOS. When implementing a 4bit-adder, the measured energy of the proposed FPGA is 15% less than the normalized energy of the state-of-the-art. When implementing fifteen selected low-power applications, the estimated energy of the proposed FPGA is on average 75x lower than Microsemi IGLOO.

A 507nW self-powered SoC is demonstrated for ultra-low power (ULP) internet-of-things (IoT) applications. The SoC includes ULP system-in-package (SiP) interfaces that enable its harmonious integration with a radio transmitter (TX) and a non-volatile memory (NVM). The energy harvesting platform power manager (EH-PPM) powers the SoC as well as off-chip components and is optimized for low quiescent power. It supplies the SoC with 0.5V, 1.0V, and 1.8V and can also power ULP sensors and the SiP components while running an example shipping-integrity tracking algorithm. A power monitor (PM) cold-boots the SoC from NVM and adapts the system's power consumption. The tight integration between the SoC's blocks enables sub-μW operation.