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Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

Neuromorphic systems have shown improvements over the years, leveraging Spiking neural networks (SNN) event-driven nature to demonstrate low power consumption. As neuromorphic systems require high integration to form a functional silicon brain-like, moving to 3D integrated circuits (3D-ICs) with three-dimensional network on chip (3D-NoC) interconnect is a suitable approach that allows scalable design, shorter connections, and lower power consumption. However, highly dense neuromorphic systems also encounter the reliability issue where a single point of failure can affect the systems’operation. Because neuromorphic systems rely heavily on spike communication, an interruption or violation in the timing of spike communication can adversely affect the performance and accuracy of a neuromorphic system. This paper presents NASH,a a fault-tolerant 3D-NoC based neuromorphic system that incorporates as processing elements, lightweight spiking neuron processing cores (SNPCs) with spike-timing-dependent-plasticity (STDP) on-chip learning. Each SNPC houses 256 leaky integrate-and-fire (LIF) neurons and 65k synapses. Evaluation results on MNIST classification, using the fault-tolerant shortest-path K-means-based multicast routing algorithm (FTSP-KMCR), show that the NASH system can maintain high accuracy for up to 30% permanent fault in the interconnect with an acceptable area and power overheads when compared to other existing systems.aThis project is supported by the University of Aizu, Competitive Research Funding (CRF), Ref. UoA-P6-2020

3D-Network-on-Chips exploit the benefits of Network-on-Chips and 3D-Integrated Circuits allowing them to be considered as one of the most advanced and auspicious communication methodologies. On the other hand, the reliability of 3D-NoCs, due to the vulnerability of Through Silicon Vias, remains a major problem. Most of the existing techniques rely on correcting the TSV defects by using redundancies or employing routing algorithms. Nevertheless, they are not suitable for TSV-cluster defects as they can either lead to costly area and power consumption overheads, or they may result in non-minimal routing paths; thus, posing serious threats to the system reliability and overall performance. In this work, we present a scalable and low-overhead TSV usage and design method for 3D-NoC systems where the TSVs of a router can be utilized by its neighbors to deal with the cluster open defects. An adaptive online algorithm is also introduced to assist the proposed system to immediately work around the newly detected defects without using redundancies. The experimental results show the proposal ensure less than 2 percent of the routers being disabled, even with 50 percent of the TSV clusters defects. The performance evaluations also demonstrate unchanged performances for real applications under 5 percent of cluster defects.

In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and operating phases, most of the existing methods use a dedicated testing mechanism with long response time and prerequisite interruptions for online testing. This article presents an error correction code (ECC)-based method named “TSV on-communication test” (TSV-OCT) to detect and localize faults without halting the operation of TSV-based 3-D-IC systems. We first propose a statistical detector, a method to detect open and short defects in TSVs that work in parallel with data transactions. Second, we propose an isolation-and-check algorithm to enhance the localization ability of the method. Moreover, the Monte Carlo simulations show that the proposed statistical detector increases $\times 2$ the number of detected faults when compared to conventional ECC-based techniques. With the help of isolation and check, TSV-OCT localizes the number of defects up to $\times 4$ and $\times 5$ higher. In addition, the response time is kept below 65 000 cycles, which could be easily integrated into real-time applications. On the other hand, an implementation of TSV-OCT on a 3-D Network-on-Chip (NoC) router shows no performance degradation for testing while having a reasonable area overhead.

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

Thermal dissipation is one of the most critical challenges for stacking 3D-ICs, where the heat cannot easily transfer through several layers of silicon. As the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s mode [1], stacking 3D-ICs also confront the reliability threat. Notably, Copper has a higher activation energy than CMOS, which makes Copper Through-Silicon-Vias vulnerable with the thermal-accelerated failure. Therefore, this paper presents a platform where we investigate the thermal distribution, predict the reliability, and propose a method for efficiently insert spare TSVs to ensure lifetime reliability. To demonstrate our platform, we apply a TSV-based 3D-NoC (3D Network-on-Chip) under the PARSEC benchmarks. We also illustrate the thermal-aware TSV redundancies insertion using grid search and genetic algorithm to balance the number of TSVs and the target MTTF.

Spiking Neural Network (SNN) is the third generation of Neural Network (NN) mimicking the natural behavior of the brain. By processing based on binary input/output, SNNs offer lower complexity, higher density and lower power consumption. This work presents an efficient software-hardware design framework for developing SNN systems in hardware. In addition, a design of low-cost neurosynaptic core is presented based on packet-switching communication approach. The evaluation results show that the ANN to SNN conversion method with the size 784:1200:1200:10 performs 99% accuracy for MNIST while the unsupervised STDP archives 89% with the size 784:400 with recurrent connections. The design of 256-neurons and 65k synapses is also implemented in ASIC 45nm technology with an area cost of 0.205 $m m^2$.

Neuromorphic computing tries to model in hardware the biological brain which is adept at operating in a rapid, real-time, parallel, low power, adaptive and fault-tolerant manner within a volume of 2 liters. Leveraging the event driven nature of Spiking Neural Network (SNN), neuromorphic systems have been able to demonstrate low power consumption by power gating sections of the network not driven by an event at any point in time. However, further exploration in this field towards the building of edge application friendly agents and efficient scalable neuromorphic systems with large number of synapses necessitates the building of small-sized low power spiking neuron processor core with efficient neuro-coding scheme and fault tolerance. This paper presents a spiking neuron processor core suitable for an event-driven Three-Dimensional Network on Chip (3D-NoC) SNN based neuromorphic systems. The spiking neuron Processor core houses an array of leaky integrate and fire (LIF) neurons, and utilizes a crossbar memory in modelling the synapses, all within a chip area of 0.12mm2 and was able to achieves an accuracy of 95.15% on MNIST dataset inference.

Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the Network-on-Chip (NoC) paradigm with the high-performance and low-power cost of 3D-ICs. However, as technology scales down, the reliability issues are becoming more crucial, especially for complex 3D-NoC which provides the communication requirements of multi and many-core systems-on-chip. Reliability assessment is prominent for early stages of the manufacturing process to prevent costly redesigns of a target system. In this paper, we present an accurate reliability assessment and quantitative evaluation of a soft-error resilient 3D-NoC based on a soft-error resilient mechanism. The system can recover from transient errors occurring in different pipeline stages of the router. Based on this analysis, the effects of failures in the network's principal components are determined.

The Network-on-Chip (NoC) paradigm has been proposed as a favorable solution to handle the strict communication requirements between the increasingly large number of cores on a single chip. However, NoC systems are exposed to the aggressive scaling down of transistors, low operating voltages, and high integration and power densities, making them vulnerable to permanent (hard) faults and transient (soft) errors. A hard fault in a NoC can lead to external blocking, causing congestion across the whole network. A soft error is more challenging because of its silent data corruption, which leads to a large area of erroneous data due to error propagation, packet re-transmission, and deadlock. In this paper, we present the architecture and design of a comprehensive soft error and hard fault-tolerant 3D-NoC system, named 3D-Hard-Fault-Soft-Error-Tolerant-OASIS-NoC (3D-FETO). With the aid of efficient mechanisms and algorithms, 3D-FETO is capable of detecting and recovering from soft errors which occur in the routing pipeline stages and leverages reconfigurable components to handle permanent faults in links, input buffers, and crossbars. In-depth evaluation results show that the 3D-FETO system is able to work around different kinds of hard faults and soft errors, ensuring graceful performance degradation, while minimizing additional hardware complexity and remaining power efficient., Comment: arXiv admin note: text overlap with arXiv:2003.09616

The component’s failure in network-on-chips (NoCs) has been a critical factor on the system’s reliability. In order to alleviate the impact of faults, fault tolerance has been investigated in the recent years to enhance NoC’s robustness. Due to the vast selection of fault-tolerance mechanisms and critical design constraints, selecting and configuring an appropriate mechanism to satisfy the fault-tolerance requirements constitute new challenges for designers. Consequently, reliability assessment has become prominent for the early stages of manufacturing process to solve these problems. This paper approaches the fault-tolerance analysis by providing an analytical model to approximate the lifetime reliability and compares it with a system-level simulation. Based on the proposed approach, we measure the fault-tolerance efficiency using a new parameter, named reliability acceleration factor. The goal of this paper is to provide an efficient and accurate reliability assessment to help designers easily understand and evaluate the advantages and drawbacks of their potential fault-tolerance methods.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates, the sensitivity to thermal hotspots and stress issues due to the difference in temperature between layers are preventing TSV-based 3D-ICs from being widely and efficiently used. Due to defect clustering, 3D-ICs could have multiple defects in the same region which cannot be detected by using error correction codes while dedicated testing could take a significant number of testing cycles. This paper presents a 2D Parity Product Code (2D-PPC) with the ability to correct one fault and detect, at least, two faults. With the extension using Orthogonal Latin Square, 2D-PPC could detect multiple defects while reasonably increasing the area cost and latency.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs); however, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are threating TSV-based 3D-ICs. On the other hand, real-time applications demand short response time to the new occurrence faults which make online testing become a critical challenge. In order to solve this problem, this paper presents an online method named TSV-IaS which supports detecting and correcting open and short defect TSVs by isolating and shifting the signals of TSVs then analyzing the output syndromes. Furthermore, we also present an analytical analysis on detectability and response time of the proposal. Results show that with R redundant TSVs in a group, the proposed method can fully correct R defects and detect R+1 defects while keeping a low-cost structure. Monte-Carlo simulations also demonstrate a 100% detection rate with 32-cycles based tests.

3D-Network-on-Chips (3D-NoCs) are considered as one of the most advanced and auspicious communication methodologies for future IC designs by exploiting the benefits of Network-on-Chips (NoCs) and 3D-Integrated Circuits (3D-ICs). However, their reliability still remains a major problem due to the vulnerability of Through Silicon Vias (TSVs). Because most of the existing techniques rely on correcting the TSV defects by using redundancy or employing routing algorithms, the TSV-cluster defect tolerances encounter costly area and power consumption penalties. In order to solve this issue, we propose a highly scalable and low-overhead TSV management for 3D-NoC systems where the TSVs of a router can be utilized by its neighbors and an adaptive online algorithm is also performed to assist. With this proposal, we aim to maintain a graceful performance for 3D-NoCs without the need for redundant links or employing routing algorithms.

Three-Dimensional Networks-on-Chips (3D-NoCs) have been proposed as an auspicious solution, merging the high parallelism of the packet switched NoC paradigm with the high-performance and low-power of 3D-ICs. However, as feature sizes and power supply voltages continually decrease, the devices and interconnects have become more vulnerable to transient errors. Transient errors have severe consequences on system performance, such as deadlock, data corruption, packet loss and increased packet latency. In this paper, we propose a soft-error resilient 3D Network-on-Chip (SER-3DR-NoC) architecture and design targeted for safety-critical embedded applications. Evaluation results show that the SER-3DR-NoC is able to achieve a high level of transient error protection with a little performance degradation and a small power overhead.