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Multiple-input multiple-output (MIMO) beamforming array gain can make multi-antenna transmitters (TXs) more power efficient. However, these MIMO TXs require more complex digital predistortion (DPD). In this work, analytical expressions are derived for the power consumption of both MIMO power amplifier (PA) arrays and their respective DPD, taking into account the effects of precoding on PA output power and peak-toaverage power ratio (PAPR). It is shown that for complex DPD algorithms such as cross-over DPD (CO-DPD) in combination with wide bandwidths, the overall DPD power consumption can exceed the overall PA power consumption already for TXs for scenarios with more than two antennas.

This brief examines the theoretical interdependence of low-noise-amplifier (LNA) performance parameters to identify four figures of merit (FoMs) that enable the comparison of LNAs. FoM limits are also estimated to identify performance limitations and to quantify room for theoretical improvement. Finally, the results of a regression analysis on nearly 500 CMOS LNAs, published over the past 20 years, are compared to the identified trends, with the findings showing reasonable agreement despite the adoption of some simplifying assumptions.

A highly reconfigurable direct-conversion software-defined multiple-input multiple-output (MIMO) receiver with four RF inputs and four I/Q baseband outputs is proposed. It allows for digital MIMO but also analog interference rejection by spatial notch filtering through four flexible and simultaneous orthogonal beams. A segmented constant-Gm vector modulator (VM) with improved interference tolerance and wide RF frequency range targeting the sub-6-GHz bands is proposed. It exploits current-domain beamforming before $I$ – $V$ conversion by transimpedance amplifiers. A 0.7–5.7-GHz 22-nm fully depleted silicon-on-insulator (FD-SOI) prototype chip achieves >29 dB spatial filtering for a single notch and an ultrawideband 20-dB notch suppression bandwidth of 2.3 GHz at broadside excitation at an local oscillator (LO) frequency of 2.5 GHz. In the notches, an IIP3 of +16 dBm and B1dB of −11.5 dBm at a 41-dB gain is achieved, improving IIP3 and B1dB by 35 and 27 dB, respectively, by spatial filtering. A single-element noise figure (NF) of 5.5–7 dB is achieved on the VM constellation corners, degrading about 2 dB on the points nearby the biggest circle fitting into a square constellation. However, sub-3-dB system NF is potentially achievable, taking into account up to 6-dB improvement by the four-element beamforming. Given both gain and phase control provided by the VM, spatial patterns with up to three independent nulls can be synthesized with the four-element antenna array. The chip of 0.52 mm2 active area consumes 77–139 mW at an LO-frequency of 0.7–5.7 GHz from a 0.8-V supply.

The application of stacked-FETs in power amplifiers allows for a supply voltage higher than supported by the breakdown voltage of a single transistor. Potential benefits of the increased supply voltage are reduced supply currents and a lower matching ratio at the output of the amplifier. Furthermore, an increased output power per chip area is obtained due to the reduction in passive structures resulting in more area-efficient power combining. In this paper, the procedure for the design of integrated microwave stacked-FET is discussed. Several options for the correct distribution of RF voltage and current swings are investigated and the relationship between the number of stacked transistors and bandwidth is addressed. The procedure is demonstrated by the design of an S-band GaAs stacked-FET containing three transistors. This stacked-FET is applied in an S-band HPA that has a PAE of more than 40% at an output power of 20 W, which is more than twice the output power of any previously reported GaAs stacked-FET HPA.

A technique is proposed for increasing the data rate transmitted through an inductively coupled chip-to-chip link by resetting the channel state variables. This allows the data rate to be increased well beyond what is implied by the channel bandwidth. In the proposed scheme, the two sides of the link are resonated at the highest possible quality factor, maximizing link gain, and minimizing interference. The transmit signal is a binary matched pulse which maximizes the received signal for a given transmitter voltage limit. High-efficiency switching transmitters can be used for this type of signal. The proposed technique can be applied to communication links in which channel state variables are accessible for reset. For increasing the data rate, it is shown that the proposed state-variable reset technique results in a higher signal-to-noise ratio of the received signal and a higher energy efficiency compared to reducing the quality factor to widen the bandwidth, using equalization, or using multi-level signaling. The technique is demonstrated on a chip-to-chip link with coupled 1.5 mm $\times1.5$ mm planar inductors separated by 0.5 mm in a 0.18 $\mathrm {\mu m}$ CMOS process. 500 Mb/s data rate is achieved over a link which has a band-pass bandwidth of 185 MHz.

This paper presents an energy-/area-efficient digitally controlled oscillator (DCO)-based phase-tracking Receiver for Internet-of-Things (IoT) applications. The RX leverages the constant-envelope nature of frequency shift keying modulation adopted in many IoT protocols, e.g., IEEE802.15.4 and Bluetooth low energy (BLE), to enhance the energy efficiency and to reduce the chip area. The proposed RX, with the DCO acting as a local oscillator (LO) and binary frequency feedback, promotes low-power and low-voltage circuit design, while a data-aided carrier-frequency tracking ensures the received carrier stability without a power-/area-hungry phase-locked loop (PLL). The RX avoids a compromise between a power-hungry I/Q LO generation and the image rejection in traditional RXs. An equivalent mathematical model is further presented, which helps to analyze and optimize the frequency response of the proposed RX. Fabricated in 40-nm CMOS, the RX consumes 1.55 mW from a 0.85-V supply and has a −87-dBm sensitivity at 2 Mb/s, which leads to a 0.77-nJ/b energy efficiency and 178-dB RX sensitivity FoM.

—Digital Multiple-Input Multiple-Output (MIMO) receivers, exposed to strong co-channel interference, require high dynamic range Analog-to-Digital Converters (ADCs) and a highly linear RF front-end. Hybrid analog-digital beamforming can mitigate this co-channel interference by spatial filtering before the ADC and improve interference robustness. This paper demonstrates and characterizes this mitigation effect in detail utilizing Error Vector Magnitude (EVM) as a criterion. A 4-element 22 nm FD-SOI CMOS prototype MIMO Receiver chip is characterized with a linear 4-element dipole antenna array with half-wavelength spacing in the 2.4 GHz ISM-band. EVM measurements demonstrate the effectiveness of spatial filtering for co-channel interference mitigation and dynamic range extension. The receiver is exposed to interference while using different QAM formats (16-QAM to 256-QAM). It is demonstrated how interference reduces the acceptable-EVM input power range, while hybrid beamforming extends this range. This is done by extensive conductive measurements for reliable results, while also demonstrating an Over-the-Air (OTA) result

Merging developments in RFID and wireless sensor networks have increased the interest in using backscatter radio for tag-to-tag communication. Low power consumption is a major concern, often limiting the choice to incoherent receivers such as diode envelope detectors. Link budget calculations require receiver sensitivity specifications, however accurate characterizations are scarce. In this work, we show that the receiver sensitivity is strongly related to the exciter incident power. Full-range analysis of a zero-bias diode detector shows a decreasing noise factor at higher incident powers, which leads to improved sensitivity. On the other side, at strong incident powers, the phase noise of the exciter interferes with the received signal, setting an lower bound to the sensitivity of the backscatter receiver. This work proposes a semi-passive RFID tag capable of 1kbps to 10kbps data rates in the 434MHz band using off the shelf components. The tag has a low power consumption of 85μW during receive, 45μW during transmit and less than 4μW in sleep. The receiver sensitivity at 1kbps shows a 25dB variation as a function of exciter incident power between -50 to 10dBm, while a peak sensitivity of around -80dBm is measured at an incident power of -25dBm.

Power amplifiers (PAs) need digital predistortion (DPD) linearization to handle high-order complex modulation schemes in next-generation communication systems. While load variation is inevitable, DPD is generally designed considering only the nominal load impedance for PAs. This paper presents a polar class-E PA with an on-chip waveform characterizer enabling adaptive digital predistortion (ADPD) to preserve the linearity of the PA under load mismatch. The presented ADPD corrects both AM/AM and AM/PM distortions, which are prominent in the demonstrated PA, while simultaneously correcting for slow memory effects without the need for complex memory DPD algorithms. Load-pull measurements demonstrate that target error vector magnitude (EVM) and adjacent channel power ratio (ACPR) can be maintained in a significantly larger area on the Smith chart going from 50 Ω optimized static DPD to our ADPD for a 2 GHz 1024 QAM signal with 1 MSym/s symbol rate.

In this letter, we present a design of a linear array of tilted dipoles to achieve radiation patterns with asymmetric angular filtering characteristics. To realize the asymmetric radiation, the dipole elements are spaced by a distance larger than half a wavelength, thus allowing for grating lobes to occur in the visible region. Moreover, the dipoles are loaded with artificial dielectrics to increase the front-to-back ratio and consequently to enable higher gain in certain desired angular regions. Based on the design, a linear array with ten elements is manufactured and tested. The measured results show the ability of such an array to achieve stable gain from broadside up to 90° scanning while implementing a stopband angular filter for negative scanning angles. © 2002-2011 IEEE.

Upcoming Internet-of-Things (IoT) applications require low-power multi-standard RF receiver (RX) front-ends. Interference rejection becomes increasingly important as ever more devices compete in the scarce 10w-GHz spectrum. Typically, low-power RXs do not possess very steep filtering [1]–[6]. On the other hand, very selective RXs - e.g. using analog FIR or Filtering-by-Aliasing [7] - have very high power consumption, not suitable for IoT applications. A recent Analog Finite-Impulse-Response (AFIR) filter [8] shows promising results to improve channel filtering. [8] uses a much lower FIR update rate than [7] to considerably reduce power consumption. This comes at the cost of a filter alias, but the inherent windowed integration sinc filtering mitigates this filter alias. Achieving low RX Noise Figure (NF), while improving selectivity is challenging at ultra-low power, where all blocks tend to contribute significantly to the total power consumption [1]–[6].

In this article, we investigate the radiation and impedance properties of arrays of tilted dipoles. A spectral periodic method of moments (MoM) is developed for the analysis of infinite arrays with arbitrarily tilted dipole elements, in free space or with a backing reflector. With the aid of this analysis method, the radiation characteristics of arrays of stacked dipoles over a ground plane are studied, explaining the variation of the patterns as a function of the interelement distance and the angle of inclination of the elements. Finite linear arrays of tilted dipoles are also investigated, to assess the dependence of the array characteristics on the number of elements. The developed method can be used to design arrays with nonsymmetric radiation patterns for angular filtering or pattern shaping.

A five-layer frequency selective surface (FSS) composed of subwavelength elements with large harmonic rejection bandwidth is presented. The FSS design is based on an equivalent circuit model, where the interlayer interaction is only described with a single transmission line representing the fundamental Floquet wave. A prototype of the designed FSS is fabricated, and the measured response exhibits good stability over a wide conical incidence range up to 45°. The FSS is combined with a wide-scanning connected array of dipoles to implement a phased array with integrated filtering properties. A dispersion analysis is performed to define the distance between the array and the FSS that avoids the propagation of surface waves between the combined structures, allowing to maximize the radiation efficiency. The performance of the array combined with the FSS is experimentally characterized, showing high-order harmonic rejection better than 17 dB over a large bandwidth.

We report on the dependency of the optical power efficiency $\eta $ on the breakdown voltage ${V}_{\text {BR}}$ of avalanche-mode (AM) light-emitting diodes (LEDs) in silicon. Lateral p+-n-n+ LEDs have been designed in a 65-nm bulk CMOS technology, where ${V}_{\text {BR}}$ is varied between 2 and 9 V. This tunes both the magnitude and the spatial distribution of the reverse electric field, which governs AM electroluminescence. Experiments show that a maximum $\eta $ of $\sim 1.7 \times 10^{-6}$ is obtained for ${V}_{\text {BR}} \sim 6$ V. For ${V}_{\text {BR}} V, non-local avalanche results in a lower $\eta $ , while for ${V}_{\text {BR}} > 6$ V, a gradual reduction in $\eta $ with increasing ${V}_{\text {BR}}$ is obtained. This trend is compared with two recently proposed opto-electronic models. A maximum in $\eta $ at relatively low voltages is attractive for monolithic opto-electronic integration in silicon

Subthreshold amplifiers suffer from the limited voltage headroom which leaves little space for conventional analog techniques to enhance performance and efficiency. This paper presents an evolution process of implementing conventional structures with inverters, allowing ultralow-voltage operation with increased flexibility in adopting traditional circuit techniques. Based on the proposed inverter-based elementary structure and CMFB, both the Miller-compensated (MC) operational transconductance amplifier (OTA) and the feedforward-compensated (FFC) OTA achieve significantly improved performance as compared to previous works. The proposed amplifier techniques are verified in $\Delta \Sigma $ modulator (DSM) design, with MC-OTA for a DT-DSM and FFC-OTA for a CT-DSM, both fabricated in a 0.13- $\mu \text{m}$ CMOS. The 0.3-V DT-DSM achieves 74.1-dB SNDR, 83.4-dB SFDR and 20-kHz bandwidth with 79.3- $\mu \text{W}$ power, resulting in a Schreier figure of merit (FoM) of 158 dB. The 0.3-V CT-DSM achieves 68.5-dB SNDR, 82.6-dB SFDR, and 50-kHz bandwidth with 26.3- $\mu \text{W}$ power, leading to a Schreier FoM of 161 dB. Both DSMs exhibit highly competitive performance among sub-0.5-V designs, validating the proposed subthreshold amplifier techniques.

Low-power and low-jitter equalization techniques become increasingly crucial for the wire-line receivers operating at data rates more than tens of gigabits per second. This brief reports an inductorless and power-efficient 32-Gb/s hybrid analog equalizer. The hybrid analog equalizer utilizes a triple-gate control to achieve equalization over a range of channel loss resulting in an inductorless and area-efficient design. The triple-gate controls entail that a low-frequency equalization is achieved in addition to the intermediate and high-frequency equalization, at minimum area overhead. The prototype is realized in a 65-nm CMOS, occupying a compact active area of 0.013 mm2. The maximum equalization achieved is 21 dB at Nyquist with a measured peak-to-peak data jitter of 5.25 ps (0.17 unit interval) at 32 Gb/s for a 231 - 1 pseudorandom bit sequence signal. The measurement shows a vertical eye-opening recovery rate of up to 61% at 32 Gb/s, for a channel loss of 21 dB. The prototype exhibits a competitive power efficiency of 0.53 mW/Gb/s under a supply voltage of 1.2 V. MOE (Min. of Education, S’pore)